Integrated Circuit Design

Lecture Notes in Computer Science 1918 Edited by G. Goos, J. Hartmanis and J. van Leeuwen 3 Berlin Heidelberg New York Barcelona Hong Kong London Milan Paris Singapore Tokyo Dimitrios Soudris Peter Pirsch Erich Barke (Eds.) Integrated Circuit Design Power and Timing Modeling, Optimization and Simulation 10th International Workshop, PATMOS 2000 Göttingen, Germany, September 13-15, 2000 Proceedings 13 Series Editors Gerhard Goos, Karlsruhe University, Germany Juris Hartmanis, Cornell University, NY, USA Jan van Leeuwen, Utrecht University, The Netherlands Volume Editors Dimitrios Soudris Democritus University of Thrace, Dept. of Electrical & Computer Engineering 67100 Xanthi, Greece E-mail: [email protected] Peter Pirsch University of Hanover, Institute for Communication Theory and Signal Processing Appelstr. 4, 30167 Hanover, Germany E-mail: [email protected] Erich Barke University of Hanover, Institute for Microelectronic Systems Appelstr. 4, 30167 Hanover, Germany E-mail: [email protected] Cataloging-in-Publication Data applied for Die Deutsche Bibliothek - CIP-Einheitsaufnahme Integrated circuit design : power and timing modeling, optimization and simulation ; 10th international workshop ; proceedings / PATMOS 2000, Göttingen, Germany, September 13 - 15, 2000. Dimitrios Soudris . . . (ed.). - Berlin ; Heidelberg ; New York ; Barcelona ; Hong Kong ; London ; Milan ; Paris ; Singapore ; Tokyo : Springer, 2000 (Lecture notes in computer science ; Vol. 1918) ISBN 3-540-41068-6 CR Subject Classification (1998): B.7, B.8, C.1, C.4, B.2, B.6, J.6 ISSN 0302-9743 ISBN 3-540-41068-6 Springer-Verlag Berlin Heidelberg New York This work is subject to copyright. All rights are reserved, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, re-use of illustrations, recitation, broadcasting, reproduction on microfilms or in any other way, and storage in data banks. Duplication of this publication or parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer-Verlag. Violations are liable for prosecution under the German Copyright Law. Springer-Verlag Berlin Heidelberg New York a member of BertelsmannSpringer Science+Business Media GmbH © Springer-Verlag Berlin Heidelberg 2000 Printed in Germany Typesetting: Camera-ready by author, data conversion by Steingräber Satztechnik GmbH, Heidelberg Printed on acid-free paper SPIN: 10722793 06/3142 543210  Preface This workshop is the tenth in a series of international workshops. This year it takes place in Göttingen, Germany, and is organized by the University of Hannover. Göttingen has one the most famous German universities, where very well known scientists like Lichtenberg, Hilbert, Gauss and von Neumann studied, worked and taught. It also hosts several research institutes of the Max-Planck- Society. The first electronic tube calculator G1 was built in Göttingen in 1952 by H. Billing. Additionally, Göttingen was selected because it is adjacent to the world exposition EXPO 2000 in Hannover which gives an outlook into the 21st century covering the major topics of humankind, nature and technology. With respect to these inspiring surroundings the technical program of PAT- MOS 2000 includes 10 sessions dedicated to most important subjects of power and timing modeling, optimization and simulation at the dawn of the 21st cen- tury. The four invited talks address the European research activities in the work- shop fields, the evolving needs for minimal power consumption in the area of wireless and chipcard applications and design methodologies of very highly in- tegrated multimedia processors. The workshop is a result of the joint work of a large number of individuals, who cannot all be mentioned here. In particular, we would like to acknowledge the outstanding work of the reviewers, who did a competent job in a timely manner. We also have to thank the members of the local organizing committee for their effort in enabling the conference to run smoothly. Finally, we gratefully acknowledge the support of all organizations and institutions sponsoring the conference. September 2000 Peter Pirsch Erich Barke Dimitrios Soudris  Organization Organization Commitee General Co Chairs: Peter Pirsch (University of Hannover, Germany) Erich Barke (University of Hannover, Germany) Program Chair: Dimitrios Soudris (Democritus University of Thrace, Greece) Finance Chair: Lars Hedrich (University of Hannover, Germany) Publication Chair: Achim Freimann (University of Hannover, Germany) Audio-Visual Chair: Jörg Abke (University of Hannover, Germany) Local Arrangements Chair: Carsten Reuter (University of Hannover, Germany) Program Commitee D. Auvergne (University of Montpellier, France) J. Bormans (IMEC, Belgium) J. Figueras (University of Catalunya, Spain) C.E. Goutis (University of Patras, Greece) A. Guyot (INPG Grenoble, France) R. Hartenstein (University of Kaiserslautern, Germany) S. Jones (University of Loughborough, United Kingdom) P. Larsson-Edefors (University of Linköping, Sweden) E. Macii (Polytechnic of Torino, Italy) V. Moshnyaga (University of Fukuoka, Japan) W. Nebel (University of Oldenburg, Germany) J.A. Nossek (Technical University of München, Germany) A. Nunez (University of Las Palmas, Spain) M. Papaefthymiou (University of Michigan, United States) M. Pedram (University of Southern California, United States) H. Pfleiderer (University of Ulm, Germany) C. Piguet (CSEM, Switzerland) R. Reis (University of Porto Alegre, Brazil) M. Robert (University of Montpellier, France) A. Rubio (University of Catalunya, Spain) J. Sparsø (Technical University of Denmark, Denmark) A. Stempkowsky (Academy of Sciences, Russia) T. Stouraitis (University of Patras, Greece) J.F.M. Theeuwen (Philips, The Netherlands) A.-M. Trullemans-Anckaert (University of Louvain, Belgium) R. Zafalon (STMicroelectronics, Italy) VIII Organization Steering Commitee D. Auvergne (University of Montpellier, France) R. Hartenstein (University of Kaiserslautern, Germany) W. Nebel (University of Oldenburg, Germany) C. Piguet (CSEM, Switzerland) A. Rubio (University of Catalunya, Spain) J. Sparsø (Technical University of Denmark, Denmark) A.-M. Trullemans-Anckaert (University of Louvain, Belgium) Sponsoring Institutions European Commission Directorate – General Information Society IEEE Circuits and Systems Society  Table of Contents Opening Constraints, Hurdles, and Opportunities for a Successful European Take-Up Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 R. van Leuken, R. Nouta, A. de Graf (Delft University of Technology, The Netherlands) RTL Power Modeling Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques . . . . . . . . . . . . . . . . . . 3 M. Anton, M. Chinosi, D. Sirtori, R. Zafalon (STMicroelectronics, Italy) Power Models for Semi-autonomous RTL Macros . . . . . . . . . . . . . . . . . . . . . . 14 A. Bogliolo (University of Ferrara, Italy) E. Macii, V. Mihailovici, M. Poncino (Polytechnical University of Torino, Italy) Power Macro-Modelling for Firm-Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 G. Jochens, L. Kruse, E. Schmidt, A. Stammermann, W. Nebel (OFFIS Research Institute, Oldenburg, Germany) RTL Estimation of Steering Logic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 C. Anton, P. Civera, I. Colonescu, E. Macii, M. Poncino (Polytechnical University of Torino, Italy) A. Bogliolo (University of Ferrara, Italy) Power Estimation and Optimization Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 N.D. Zervas, S. Theoharis, A.P. Kakaroudas, G. Theodoridis, C.E. Goutis (University of Patras, Greece) D. Soudris (Democritos University of Thrace, Greece) Framework for High-Level Power Estimation of Signal Processing Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 A. Freimann (University of Hannover, Germany) X Table of Contents Adaptive Bus Encoding Techique for Switching Activity Reduced Data Transfer over Wide System Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 C. Kretzschmar, R. Siegmund, D. Müller (Chemnitz University of Technology, Germany) Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 G. Theodoridis, S. Theoharis, N.D. Zervas, C.E. Goutis (University of Patras, Greece) System-Level Design A Holistic Approach to System Level Energy Optimization . . . . . . . . . . . . . . 88 M.J. Irwin, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam (The Pennsylvania State University, USA) Early Power Estimation for System-on-Chip Designs . . . . . . . . . . . . . . . . . . . 108 M. Lajolo (NEC C&C Research Labs, Princeton, USA) L. Lavagno (University of Udine, Italy) M. Sonza Reorda, M. Violante (Polytechnical University of Torino, Italy) Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 R. Hartenstein, Th. Hoffmann, U. Nageldinger (University of Kaiserslautern, Germany) Transistor-Level Modeling Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 P. Maurine, M. Rezzoug, D. Auvergne (University of Montpellier, France) Impact of Voltage Scaling on Glitch Power Consumption . . . . . . . . . . . . . . . . 139 H. Eriksson, P. Larsson-Edefors (University of Linköping, Sweden) Degradation Delay Model Extension to CMOS Gates . . . . . . . . . . . . . . . . . . . 149 J. Juan-Chico, M.J. Bellido, P. Ruiz-de-Clavijo, A.J. Acosta, M. Valencia (Centro Nacional de Microelectrónica, Sevilla, Spain) Second Generation Delay Model for Submicron CMOS Process . . . . . . . . . . 159 M. Rezzoug, P. Maurine, D. Auvergne (University of Montpellier, France) Asynchronous Circuit Design Semi-modular Latch Chains for Asynchronous Circuit Design . . . . . . . . . . . . 168 N. Starodoubtsev, A. Bystrov, A. Yakovlev (University of Newcastle upon Tyne, UK)  Table of Contents XI Asynchronous First-in First-out Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 F. Pessolano (South Bank University, London, UK) J.W.L. Kessels (Philips Research Laboratories, Eindhoven, The Netherlands) Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 A.P. Kakaroudas, K. Papadomanolakis, V. Kokkinos, C.E. Goutis (University of Patras, Greece) VLSI Implementation of a Low-Power High-Speed Self-Timed Adder . . . . . 195 P. Corsonello, (University of Reggio Calabria, Italy) S. Perri, G. Cocorullo (University of Calabria, Italy) Power Efficient Technologies Low Power Design Techniques for Contactless Chipcards . . . . . . . . . . . . . . . . 205 H. Sedlak (Infineon Technologies, Munich, Germany) Dynamic Memory Design for Low Data-Retention Power . . . . . . . . . . . . . . . . 207 J. Kim, M.C. Papaefthymiou (University of Michigan, USA) Double-Latch Clocking Scheme for Low-Power I.P. Cores . . . . . . . . . . . . . . . . 217 C. Arm, J.-M. Masgonty, C. Piguet (CSEM, Switzerland) Design of Multimedia Processing Applications Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 S. Dutta (Philips Semiconductors, Sunnyvale, USA) Cost-Efficient C-Level Design of an MPEG-4 Video Decoder . . . . . . . . . . . . . 233 K. Denolf, P. Vos, J. Bormans, I. Bolsens (IMEC, Belgium) Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications . . . . . . . . . . . . . . . . . . . . 243 D. Soudris, A. Argyriou, M. Dasygenis, K. Tatas, A. Thanailakis (Democritus University of Thrace, Greece) N.D. Zervas, C.E. Goutis (University of Patras, Greece) Adiabatic Design and Arithmetic Modules Design of Reversible Logic Circuits by Means of Control Gates . . . . . . . . . . 255 A. De Vos, B. Desoete (University of Gent, Belgium) A. Adamski, P. Pietrzak, M. Sibiński, T. Widerski (Poliytechnical University of L ; ódź, Poland) XII Table of Contents Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 M. Alioto, G. Palumbo (University of Catania, Italy) An Adiabatic Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 C. Saas, A. Schlaffer, J.A. Nossek (Technical University of Munich, Germany) Logarithmic Number System for Low-Power Arithmetic . . . . . . . . . . . . . . . . . 285 V. Paliouras, T. Stouraitis (University of Patras, Greece) Analog-Digital Circuits Modeling An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 R. Jiménez, A.J. Acosta, E.J. Peralı́as, A. Rueda (Centro Nacional de Microelectrónica, Sevilla, Spain) PARCOURS – Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 A. Hermann, E. Barke (University of Hannover, Germany) M. Silvant (Simplex Solutions, Voiron, France) J. Schlöffel (Philips Semiconductors, Hamburg, Germany) Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 A.J. Acosta, R. Jiménez, J. Juan, M.J. Bellido, M. Valencia (Centro Nacional de Microelectrónica / University of Sevilla, Spain) Computer Aided Generation of Analytic Models for Nonlinear Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 T. Wichmann (University of Kaiserslautern, Germany) M. Thole (Infineon Technologies, Munich, Germany) Author Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337