psoc intro

PSoC 3 / PSoC 5 101: Architecture Overview Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 1 Section Objectives Objectives, you will: • Understand the high-level architecture of PSoC 3 / PSoC 5 • Understand the CPU, Digital, Analog & Programmable Routing / Interconnect Subsystems Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 2 PSoC 3 / PSoC 5 Platform Architecture Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 3 CPU Subsystem ARM Cortex-M3 • Industry’s leading embedded CPU company • Broad support for middleware and applications • Up to 80 MHz; 100 DMIPS • Enhanced v7 ARM architecture: • Thumb2 Instruction Set • 16- and 32-bit Instructions (no mode switching) • 32-bit ALU; Hardware multiply and divide • Single cycle 3-stage pipeline; Harvard architecture 8051 • Broad base of existing code and support • Up to 67 MHz; 33 MIPS • Single cycle instruction execution Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 4 CPU Subsystem High Performance Memory • Flash memory with ECC • High ratio of SRAM to flash • EEPROM Powerful DMA Engine • 24-Channel Direct Memory Access • Access to all Digital and Analog Peripherals • CPU and DMA simultaneous access to independent SRAM blocks On-Chip Debug and Trace • Industry standard JTAG/SWD (Serial Wire Debug) • On chip trace • NO MORE ICE Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 5 CPU Subsystem Clocking System • Many Clock Sources • Internal Main Oscillator • External clock crystal input • External clock oscillator inputs • Clock doubler output • Internal low speed oscillator • External 32 kHZ crystal input • Dedicated 48 MHz USB clock • PLL output • 16-bit Clock Dividers • 8 Digital • 4 Analog • PSoC Creator Configuration Wizard • PSoC Creator auto-derive clocking source/dividers Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 6 CPU Subsystem Dedicated Communication Peripherals • Full Speed USB device • 8 bidirectional data end points + 1 control end point • No external crystal required • Drivers in PSoC Creator for HID class devices • Full CAN 2.0b • 16 RX buffers and 8 TX buffers • I2C master or slave • Data rate up to 400 kbps • Additional I2C slaves may be implemented in UDB array • New peripherals will be added as family members are added to the platform: Ethernet, HS USB, USB Host… Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 7 CPU Subsystem Power Management • Industry’s Widest Operating Voltage • 0.5V to 5.5V with full analog/digital capability • High Performance at 0.5V • PSoC 3 @ 67 MHz; PSoC 5 @ 72 MHz • 3 Power Modes (Active, Sleep and Hibernate) Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 8 Designed for Low Power/Low Voltage On-board DMA Controller Direct memory transfer between peripherals offloads CPU operation, Highly configurable clock lowering power consumption tree Flexible, automated clock gating. Universal Digital Blocks Implement features in hardware that reduce CPU processing requirements, lowering power consumption Cached Operations Execution from flash memory is improved by caching instructions (PSoC 5 only) Precise CPU frequencies PLL allows 4,032 different frequencies; tunable power Integrated Analog, Digital and consumption Communication Peripherals Reduce external component counts and lower overall system power consumption Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 9 Low Power Modes Digital Analog Current Current Code Clock sources Wakeup Reset Power mode resources resources (PSoC 3) (PSoC 5) execution available sources sources available available 1.2 mA 2 mA Active Yes All All All N/A All @ 6MHz @ 6MHz IO, I2C, XRES, LVD, Low Speed and RTC, Sleep 1 uA 2 uA No I2C Comparator WDR 32 kHz Osc sleep timer, comparator Hibernate 200 nA 300 nA No None None None IO XRES, LVD Power Management Enabled in PSoC Creator • Provides easy to use control APIs for quick power management • Allows code and register manipulation for in-depth control Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 10 Digital Subsystem Universal Digital Block Array (UDBs) • Flexibility of a PLD integrated with a CPU • Provides hardware capability to implement components from a rich library of pre-built, 32-bit PWM documented, and characterized components GP Logic in PSoC Creator 16-bit PWM UART #1 GP Logic GP UART • PSoC Creator will synthesize, place, and UART #3 Logic #2 route components automatically. GP LCD Segment Drive Logic GP Logic • Fine configuration granularity enables high I2C Slave silicon utilization 16-bit Shift Reg. SPI Master • DSI routing mesh allows any function in the GP Logic UDBs to communicate with any other on-chip function/GPIO pin with 8- to 32-bit data buses Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 11 Digital Subsystem Optimized 16-bit Timer/Counter/PWM Blocks • Provides nearly all of the features of a UDB based timer, counter, or PWM • PSoC Creator provides easy access to these flexible blocks • Each block may be configured as either a full featured 16-bit Timer, Counter, or PWM • Programmable options • Clock, enable, reset, capture, kill from any pin or digital signal on chip • Independent control of terminal count, interrupt, compare, reset, enable, capture, and kill synchronization • Plus • Configurable to measure pulse widths or periods • Buffered PWM with dead band and kill Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 12 Analog Subsystem Configurable Analog System • Flexible Routing: All GPIO are Analog Input/Output • +/- 0.1% Internal Reference Voltage • Delta-Sigma ADC: Up to 20-bit resolution • 16-bit at 48 ksps or 12-bit at 192 ksps • SAR ADC: 12-bit at 1 Msps • DACs: 8 – 10-bit resolution, current and voltage mode • Low Power Comparators • Opamps (25 mA output buffers) • Programmable Analog Blocks • Configurable PGA (up to x50), Mixer, Trans-Impedance Amplifier, Sample and Hold • Digital Filter Block: Implement HW IIR and FIR filters • CapSense Touch Sensing enabled Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 13 Programmable Routing/Interconnect Input / Output System • Three types of I/O • GPIO, SIO, USBIO • Any GPIO to any peripheral routing • Wakeup on analog, digital or I2C match • Programmable slew rate reduces power and noise • 8 different configurable drive modes • Programmable input threshold capability for SIO • Auto and custom/lock-able routing in PSoC Creator Up to 4 separate I/O voltage domains • Interface with multiple devices using one PSoC 3 / PSoC 5 device Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 14 PSoC 3 / PSoC 5 Platform Architecture Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 15 Review You should now: • Understand the high-level architecture of PSoC 3 / PSoC 5 • Understand the CPU, Digital, Analog & Programmable Routing / Interconnect Subsystems Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 16 Lab 101: My First PSoC 3 Digital Design Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 17 Lab Objectives Objectives: • Blink an LED on the PSoC First Touch Kit • Experience the PSoC Creator Design Flow Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 18 Step 1: Start PSoC Creator Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 19 Step 2: Create a New Project Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 20 Step 3: Place/Configure Digital Pin Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 21 Step 3: Place/Configure Digital Pin Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 22 Step 4: Configure PSoC I/O Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 23 Step 5: Add main.c Code Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 24 Step 5: Add main.c Code Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 25 Step 6: Build Project Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 26 Step 7: Program/Debug Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 27 Step 8: Debug Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 28 PSoC 3 / PSoC 5 101: PSoC Creator Design Flow Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 29 Section Objectives Objectives, you will be able to: • Follow the PSoC Creator Design Flow and develop projects • Find and use the tools available within the software IDE • Compile, build and program PSoC 3 / PSoC 5 applications • Debug PSoC 3 / PSoC 5 applications Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 30 PSoC Creator Design Flow Configure • Start a new project • Place components • Configure components • Connect components Develop • Build hardware design and generate component APIs • Write application code utilizing component APIs • Compile, build and program Debug • Perform in-circuit debug using PSoC Creator Reuse • Capture working hardware/software designs as your own components for future use Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 31 Open PSoC Creator Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 32 PSoC Creator Software Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 33 Create a new project Select the platform Name the design Select the device* Select the sheet template* * Optional steps Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 34 PSoC Creator Design Canvas Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 35 Component Catalog Catalog Folders Analog ADC Amplifier DAC Digital Registers Functions Logic Communication Display System Catalog Preview Datasheet access Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 36 Adding Components to a Design Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 37 Pins, Logic and Clock Components Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 38 Component Configuration Double-click to open component configuration dialogs Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 39 Component Data Sheets Contents: • Features • General description of component • When to use component • Input/Output connections • Parameters and setup • Application Programming Interface • Sample firmware source code • Functional description • DC and AC electrical characteristics Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 40 Design-Wide Resource Manager (.cydwr) Clocks Interrupts • Set priority and vector DMA • Manage DMA channels System • Debug, boot parameters, sleep mode API generation, etc. Directives • Over-ride placement defaults Pins • Map I/O to physical pins and ports • Over-ride default selections Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 41 Interrupts Priority may be changed Defaults to 7 (lowest priority) Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 42 DMA Priority may be changed Defaults to 2 (0 & 1 can consume 100% of bandwidth) Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 43 System System settings Debug settings Voltage Configuration Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 44 System Clocking Tree Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 45 Clock Configurations Clocks are allocated to slots in the clock tree • 8 digital, 4 analog Clocks have software APIs Reuse existing clocks to preserve resources Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 46 Pin Editor Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 47 Connecting Components Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 48 Build Hardware Design Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 49 Build Process Generate a Configuration Design Elaboration Netlisting Verilog Logic Synthesis Technology Mapping Analog Place and Route Digital Packing Digital Placement Digital Routing <…there’s more…> Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 50 Build Process API Generation Compilation Configuration Generation Configuration Verification Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 51 Development Files Core Cypress Libraries (CyLib) Registers, macros, types (cytypes) Component addressing (cyfitter) Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 52 Supported Compilers Free Bundled compiler options PSoC 3: Cypress-Edition Keil™ CA51 Compiler Kit PSoC 5: GNU/CodeSourcery Sourcery G++™ Lite No code size restrictions, not board-locked, no time limit Fully integrated including full debugging support GNU Upgrade, more optimization/compiler-support options PSoC 3: Keil CA51™ Compiler Kit PSoC 5: Keil RealView® Microcontroller Development Kit Higher levels of optimization Direct support from the compiler vendor Upgrade Compiler Pricing Set and managed by our 3rd party partner, Keil Already own these compilers? No need to buy another license! Keil CA51 Compiler Kit ~$2,000 Keil RealView MDK ~$3,000-5,000 Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 53 Integrated Debugger JTAG and SWD connection • All devices support debug • MiniProg3 programmer / debugger Control execution with menus, buttons and keys Full set of debug windows • Locals, register, call stack, watch (4), memory (4) • C source and assembler • Components Set breakpoints in Source Editor Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 54 Debugger Windows Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 55 MiniProg3 • Program PSoC 1 devices 2x5 50mil • Program/Debug PSoC 3 / PSoC 5 devices ISSP/JTAG/SWD/ • Standard 50mil connector SWV/TracePort ribbon cable and • nTRST/XRES pin is used as the device connector reset (XRES) by default • nTRST is JTAG specific and rarely used ISSP connector Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 56  PSoC Development Kit (CY8CKIT-001) • Supports all PSoC architectures via processor modules • Integrated support of all required and optional chip connections • MiniProg3 should not supply power to PSoC Development Kit 3.3V, 5.0V and adjustable Independent digital, analog and IO supply 1.8V–5.0V regulators rails (current measurement supported) RS-232 Three expansion ports support 28 IO each + USB for target 45 IO PSoC Processor RF Module Radio header Modules 1 Pot, 2 buttons, 4 LEDs, 2x16 LCD CapSense Slider & Buttons Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 57 Review You should now be able to: • Follow the PSoC Creator Design Flow and develop projects • Find and use the tools available within the software IDE • Compile, build and program PSoC 3 / PSoC 5 applications • Debug PSoC 3 / PSoC 5 applications Introduction to PSoC 3 / PSoC 5 Workshop – Rev *H 58