High Speed Serial Serial Multiplier

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A High Speed Serial-Serial Multiplier (HS-SSM) using half grid cycle for Ortho Frequency Division Multiplexing (OFDM) is proposed. In half grid cycling the data is fed at the input both during positive and negative edge of the clock. So more than one partial product is computed in each cycle. The computation of more than one partial product in each cycle reduces total delay of multiplication. The proposed HS-SSM and state-of the art multipliers are designed using VHDL coding and simulated using ALTERA QUARTUS II. The experimental results revealed that the proposed HS-SS multiplier performed better in terms of delay reduction. This accounts for the best Power Delay Product (PDP) and Area Delay Product (ADP) of the proposed multiplier. A HS-SS multiplier using half grid technique is proposed. Extensive T comparison with the conventional and state-of-the art designs revealed the best performance of the proposed serial multiplier in terms of delay and PDP reduction. An implementation of the proposed multiplier design in OFDM block for signal processing revealed its suitability for high speed application. Copyright © 2013 Praise Worthy Prize S.r.l. - All rights reserved. Nomenclature IN Keywords: Flip Flop, Terms Generator, Multipliers, Partial Products, Latency High-speed floating-point operation is essential for R Digital Signal Processing (DSP), circuit simulation, CSA Carry Save Addition image processing and so on. In many cases, the system MBE Modified Booth Encoder performance depends on the floating-point multiplication PP Partial Product time of the mantissa. To enhance the performance of the HS - SS High Speed Serial Serial multiplier, a parallel architecture is desired to reduce the FIR Finite Impulse Response EP propagation delay. FF FlipFlop Multiplications were originally performed by CT Cycle Tracker iteratively utilizing the adder. As timing constraints TG Terms Generator became stricter with increasing clock rates, dedicated multiplier hardware implementations such as the array multiplier were introduced. Since then ever more I. Introduction sophisticated methods on how to implement Multiplication is an important arithmetic operation in multiplications have been proposed. ALUs used in processing architectures. Multiplications in this regime typically require a R The multiplier is a fundamental building block in precision of 8 or16 bits. From a delay perspective, Standard Digital Signal Processors and ASIC Digital algorithms place two constraints on multiplication: Signal Processors used for Digital Signal Processing latency and throughput. Latency is the real delay of (DSP). computing a function, a measure of how long after the Multiplication process is used in many Neural inputs to a device are stable, is the final result available computing and DSP applications like instrumentation on the outputs. Throughput is a measure of how many and measurement, communications, audio and video multiplications can be performed in a given amount of processing, Graphics, image enhancement, 3-D time. For a simple combinational multiplier, throughput rendering, Navigation, radar, GPS, and control is a function of latency. applications like robotics, machine vision, guidance. It is However, various techniques exist which can compute mainly used to implement algorithms like frequency several multiplications in parallel, e.g., through domain filtering (FIR and IIR), frequency-time pipelining. A more efficient method to increase the transformations (FFT), Correlation etc. throughput is to increase the number of computations. Most DSP tasks require real-time processing; it must Various schemes are possible: for example, perform these tasks speedily while minimizing Cost and pipelining/interleaving of data allows one functional unit Power. to compute several operations concurrently, while Manuscript received and revised September 2013, accepted October 2013 Copyright © 2013 Praise Worthy Prize S.r.l. - All rights reserved 2495  N. Saravanakumar, A. Nirmal Kumar, K. N. Vijeyakumar, M. K. Ananda Moorthy implementing multiple devices on one chip simply It uses Baugh–Wooley algorithm to avoid the sign increases the throughput by the number of additional extension problem. Hence serial-parallel systolic and units. These techniques tend to be more efficient than non-systolic multipliers with low AT2 complexity based latency reduction, because if one tries to lower the delay on the Booth’s multi-bit recoding are used [14]-[16]. of a circuit, diminishing returns are quickly encountered. Although the sampling frequency has been improved In the implementation of multipliers, the main phases in the serial-parallel multipliers and the total number of are generation of partial products, reduction of partial computational cycles is halved, one of the operands products using Carry Save Addition (CSA) and a carry needs to be loaded in parallel. Recently, there has not propagation adder for the computation of final results. It been any new development in serial-serial multiplier is obvious that the second phase, i.e., the reduction of the design due to the maturity of conventional architectures. partial products contributes most to the overall delay, We propose a new serial-serial multiplier for high area and power. Therefore it is highly desirable to reduce speed applications using the half grid technique in which the number of partial products before CSA stage. the multiplication operation is done both during positive This can be achieved by Modified Booth Algorithm to and negative clock cycle. reduce the height of PP matrix [5]. Another approach is to use higher order column compressors instead of full adders to increase the PP reduction ratio of CSA stage II. Materials and Methods [6]. The drawback of Modified Booth Encoder (MBE) Hardware implementation of the serial-serial T adds both area and delay overheads to the simple partial multiplication requires Generation of partial products, product generation process and higher order compressors Reduction of partial products and Final Vector Merging are slower and consume more power than the full adders. adder. This section proposes a HS-SS multiplier which Hence, a hybrid combination of both techniques are uses a new technique (Half grid cycling) for generating considered. Serial multipliers are popular for their low area, reduced power dissipation and are more suitable for bit serial processing applications with I/O constraints and on –chip serial-link bus architectures. They are broadly classified into two categories, namely serial-serial and serial-parallel multiplier. In a serial-serial multiplier both IN rows of partial products by feeding two serial inputs (multiplier and multiplicand) in parallel bit by bit, both starting from LSB. The proposed HS-SS architecture consists of Cycle Tracker (CT), Terms Generator (TG) and Vector merging Adder as shown in Fig. 1. Cycle Tracker is used to track the number of cycles for complete multiplication. In case of inputs (xn-1xn- R the operands are loaded in a bit-serial fashion, reducing 2.......x1x0) and Y (yn-1yn-2.....y1y0) bits x0 and y0 are the data input pads to two. On the other hand, a serial- propagated through in cycle 0, and these terms are sent parallel multiplier loads one operand in a bit-serial into the TG for term generation. For a cycle n, the TG fashion and the other is always available for parallel generates 2n+1 terms. The cycle is sequenced in the operation. order n=0, 1.....m-1 where m is the number of bits in EP A bit –serial multiplier was used, which features high input. Figure 2 shows the block diagram of CT AND TG throughput at the expense of truncated output [1]. The unit. During Cycle 0, x0 and y0 are propagated into the critical path of Structure I consists of an FA, a DFF, and TG and the product x0y0 is generated using ancillary an AND gate but it has a latency of cycles for an n x n AND gate and D FF. In Cycle 1, x1 and y1 are propagated multiplication and requires 2n cycles to complete one and the terms x1y0, x0y1, x1y1 are generated. These three multiplication. A fast CSAS multiplier capable of terms along with the carry generated in cycle 0 are fed producing 2n bit output in n clock cycles at the expense into the adder which results in partial product PP1 along of an extra RCA can also be used [2]. Serial multipliers with carry out. Thus in cycle n, the xn and yn are are also used for two’s complement functions [3]. A bit propagated and 2n+1 terms are generated. The proposed R serial architecture is suitable for signal processing technique involves bit by bit processing resulting in one applications [4]. A new architecture for serial-serial bit of output in every cycle. The partial product array and multiplication is proposed with 50% reduction in its compression for a 4 × 4 multiplication is shown in hardware without degrading the speed [7]. Fig. 3. Many attempts have been made to reduce either the hardware cost or latency but there is no improvement in the critical delay. To overcome this, a systolic serial multiplier was designed with a critical path comprising an FA, a 2:1 MUX, a D Flip Flop (FF) and an AND gate [8]. Two serial-serial architectures, Structure I and Structure II, can handle a sampling frequency close to that of the serial-parallel multiplier [9]. A Serial-Serial Multiplier suitable for higher operating frequencies [10]. A low complexity area x time ^2 (AT2 ) 2’s complement serial-parallel multiplier was proposed in [12]. Fig. 1. Proposed System for Serial-Serial Multiplication Copyright © 2013 Praise Worthy Prize S.r.l. - All rights reserved International Review on Computers and Software, Vol. 8, N. 10 2496  N. Saravanakumar, A. Nirmal Kumar, K. N. Vijeyakumar, M. K. Ananda Moorthy Using x0, y0 and the present input TG produces three terms x1 y0, x0 y1 and x1 y1. These three terms along with the carry out of first stage are input to adder section which results in bit p1 along with carry out. This process continues for four clock cycles to achieve the complete multiplication. In each stage the number of terms generated is given by the following formula 2n+1, where n is the cycle/stage number. The principle of working for a 4 × 4 multiplication is illustrated in Fig. 4. Fig. 2. Block Diagram of CT and TG Unit x3y3 x3y2 x3y1 x3y0 x2y0 x1y0 x0y0 PPO x2y3 x3y1 x2y1 x1y1 x0y1 STAGE 1 T x1y3 x1y2 x0y2 x0y3 PP1 s6 s5 s4 s3 s2 s1 s0 STAGE 2 c5 s6 c4 s5 c3 s4 c2 x0y3 s3 c1 s2 s1 s0 IN PP2 STAGE 3 c5 c4 c3 c2 c1 x0y3 PP7 PP6 PP5 PP4 PP3 R pp6-7 pp5 pp4 pp3 pp2 pp1 pp0 Fig. 4. Reduction and final addition of proposed Multiplier Fig. 3. Generation of partial products in an array multiplier The feature of our design is that in all the stages of IV. Results EP Partial Product (PP) compression we don’t compress The proposed HS-SS multiplier and its counterparts more than three terms in each column and thus partial were described using structural Verilog and synthesized product addition can be carried out easily with full and using Altera Quartus II. Lyon’s, conventional, half adders. Since we use CSA for PP reduction huge Kanapaulous and Meher et al designs are used for reduction in delay due to carry propagation can be comparison. achieved. V. Discussions III. Illustration of the Proposed Methodology From the synthesis results shown in Table I, it is R found that the area of the proposed HS-SS multiplier The multiplication of two four-bit fixed point numbers decreases by 13.6%, 21.1%, 17% and 5.9% compared to generates sixteen partial products and the final product is Lyon’s, conventional, Kanapaulous and Meher et al obtained by summing these partial products. In parallel designs respectively. multipliers, all partial products are generated and This is due to efficient TG unit which realizes the summed concurrently; however, this mode of operation partial products with less number of gates. The proposed requires substantial hardware resources. To reduce HS-SS multiplier demonstrates the better delay reduction hardware complexity of multiplier suitable for signal compared to all the circuits used for comparison. This is processing we propose a serial - serial multiplier using due to the presence of an AND gate and a DFF in the pipelining. The proposed multiplier is triggered both path of TG and efficient partial product reduction using during positive and negative cycle of the clock. Fig. 1 Dadda’s methodology. In addition the proposed HS-SS shows the block diagram of the proposed bit serial multiplier demonstrates a power reduction of 13.6%, multiplier. In first clock cycle the LSBs x0 of x and y0 of 9.7%, 9.7% and 9.7% compared to Lyon’s, conventional, y are fed to produce x0 y0 which is the LSB p0 of final Kanapaulous and Meher et al designs respectively. product. In the next clock cycle x1 and y1 become This is due to the reduced number of switching in the available at the input. proposed multiplier. Copyright © 2013 Praise Worthy Prize S.r.l. - All rights reserved International Review on Computers and Software, Vol. 8, N. 10 2497  N. Saravanakumar, A. Nirmal Kumar, K. N. Vijeyakumar, M. K. Ananda Moorthy TABLE I VII. Conclusion POWER, DELAY AND AREA ESTIMATES OF PROPOSED HS-SS MULTIPLIER AND STATE-OF THE ART DESIGNS FOR AN 8 × 8 This paper developed a methodology for design of MULTIPLICATION high speed multiplier for serial multiplication. PROPOSED HS-SS CONVENTIONAL By making the circuit to operate both during positive KANAPAULOUS MULTIPLIERS / PARAMETRES MEHER ET AL MULTIPLIER and negative edge of the clock, the speed of LYON’S (1976) (1985) (1985) (2011) multiplication is increased. By using efficient partial product generation technique the proposed serial serial multiplier achieves better performance in terms of power and delay reductions compared to the state-of- the-art Area 147 161 153 135 127 designs. The minimal delay of the proposed multiplier (No.of design demonstrates the best PDP performance blocks) suggesting its suitability for portable VLSI Delay (ns) 47.1 40.5 45.8 38.40 30.5 Power 138.4 132.48 132.32 132.48 119.5 implementation. The implementation of the proposed (mW) serial multiplier in OFDM revealed its functionality. PDP 6518.6 5365.44 6060.26 5087.2 3644.75 (mW-ns) References T [1] R.F. Lyon, Two’s compliment pipeline multipliers, IEEE Trans VI. Implementation of Proposed HS-SSM Commun., Vol .COM-24 no 4 pp 418-425, April 1976. in Ortho Frequency Division [2] R.Gnanasekaran, On a bit- serial input and bit serial output multiplier IEEE Trans. Comput Vol C-32 no.9 pp 878 -880 Sept Multiplexing 1983. To verify the functionality of the proposed HS-SS multiplier, we have implemented it in auto-correlator unit (shown in Fig. 5) used in Orthogonal Frequency Division Multiplexing (OFDM) ([13], [16]-[21]). We have fed the unit with a sinusoidal input, whose other input is the time shifted version of the original signal. Input data taken from MATLAB and the time shifted sample are IN [3] [4] [5] L.Dadda, On Serial- input multipliers for two’s complement functions IEEE Trans. Comput Vol 38 no 9, pp 1341-1345 Sept 1989. N.Kanapoulos, A bit serial architecture for digital signal processing, IEEE Trans. Circuits Sysf. Vol. CAS -32 no 3, pp 289- 291 ,1985 A.D.Booth,A.D, A signed binary multiplication technique , Quarterly J.Mechan, Appl. Math. Vol 4, no 2, pp 236 -240, Aug 1951 R represented using word length of 8-bits. [6] R.Menon and D.Radhakrishanan, High Performance 5:2 Fig. 6 shows the output of autocorrelator unit compressor CMOS 4-2 and 5-2 compressor for fast arithmetic circuits IEEE Trans. Circuits Systs. I Reg Papers Vol 51, no 10, implemented with the proposed HS-SS multiplier and pp 1985 -1997, Oct 2004. standard multiplier. From the output waveform it can be [7] A.Aggoun, A.Ashur and M.K.Ibrahim, Area-time efficient seen that the proposed HS-SS multiplier performs similar serialserial multipliers, in Proc. IEEE Conf. Circuits Syst. EP to the standard multiplier thus verifying its functionality. (ISCAS), Geneva, Switzerland, 2000, pp. 585–588. [8] K.Z.Pekmestzi, P.Kalivas and N.Moshopoulos, Long unsigned number systolic serial multipliers and squarers, IEEE Trans. Circuits Syst. II, Brief Papers, Vol. 48, no. 3, pp. 316–321, Mar. 2001. [9] O.Nibouche, A.Bouridarie and M.Nibouche, New architectures for serial-serial multiplication, in Proc. IEEE Conf. Circuits Syst. (ISCAS), Sydney, Australia, 2001, Vol. 2, pp. 705–708. [10] M.R.Meher, C.C.Jong and C.H.Chang, A High Bit Rate Serial- Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters, IEEE Transactions on Very Large Scale Integration Fig. 5. Block diagram of Auto-correlator unit (VLSI) Systems, Vol. 19, no. 10, pp no,1733-1745 October 2011. R [11] P.Denyer and D.Renshaw, VLSI Signal Processing: A Bit-Serial Approach, Addison-Wesley, 1985. [12] S.Sunder, F.El-Guibaly and A.Antoniou, Two’s-complement fast serial-parallel multiplier, in Proc. Inst. Elect. Eng.—Circuits Devices Syst., Vol. 142, 1995. [13] I.Hussian and C.Prasanna Raj, Design and implementation of low power and high speed autocorrelator and CORDIC Architecture for OFDM, IACSIT International Journal of Engineering and Technology, Vol. 3, No. 3, 2011. [14] H.Saleh, A.H.Khalil, M.A.Ashour and A.Salama, Novel serial- parallel multipliers, IEEE Proc-Circuits Devices Syst., Vol. 148, no. 4, pp. 183–189, Aug. 2001. [15] Sriadibhatla Sridevi, Appsani V. V. S. Chowdary, Low Power Pilpelined FIR Filter with Enhanced Row Bypassing Multiplier, (2011) International Journal on Communications Antenna and Fig. 6. Output of Auto-correlator implemented Propagation (IRECAP), 1 (1), pp. 132-135. with proposed HS-SS multiplier [16] Ghandi F. Manasra, Mais S. Ibrahim, Yaser H. Abdallah, Bit Error Rate Reduction Using Spatial-Temporal Diversity by Employing OFDM Techniques, (2011) International Journal on Copyright © 2013 Praise Worthy Prize S.r.l. - All rights reserved International Review on Computers and Software, Vol. 8, N. 10 2498  N. Saravanakumar, A. Nirmal Kumar, K. N. Vijeyakumar, M. K. Ananda Moorthy Communications Antenna and Propagation (IRECAP), 1 (4), pp. 353-365. [17] Mattera, D., Tanda, M., Preamble-based synchronization for OFDM/OQAM systems, (2011) European Signal Processing Conference, pp. 1598-1602. [18] Mattera, D., Tanda, M., Data-aided synchronization for OFDM/OQAM systems, (2012) Signal Processing, 92 (9), pp. 2284-2292. [19] Mattera, D., Tanda, M., A new method for blind synchronization for OFDM/OQAM systems, (2011) ISPA 2011 - 7th International Symposium on Image and Signal Processing and Analysis, art. no. 6046578, pp. 46-51. [20] Mattera, D., Tanda, M., Blind symbol timing and CFO estimation for OFDM/OQAM systems, (2013) IEEE Transactions on Wireless Communications, 12 (1), art. no. 6397549, pp. 268-277. [21] Mattera, D., Tanda, M., Bellanger, M., Frequency-spreading implementation of OFDM/OQAM systems, (2012) Proceedings of the International Symposium on Wireless Communication Systems, art. no. 6328353, pp. 176-180. Authors’ information T N. Saravana Kumar obtained his Bachelor’s degree in Electrical and Electronics Engineering from Madurai Kamaraj University Coimbatore. Then he obtained his Master’s degree in VLSI Design from Government College of Technology, Coimbatore. Currently, he is a Assistant Professor (Senior Grade) in Electrical and Electronics Engineering, Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu, India. His specializations include Digital Signal Processing, VLSI Design and Control Systems. Dr. A. Nirmalkumar completed his graduation IN R and post graduation in Electrical Engg from Calicut and Kerala University in 1972 &1976 respectively. Completed his Doctorate from Bharathiar University in 1992. He is currently working as a Principal in Karpagam Engineering College, Coimbatore, Tamil Nadu, India. His area of specialization includes Power EP converters for renewable energy application and drives. He has more than 30 years of teaching experience. He is guiding at present 20 research scholars. He is the recipient of Institution of Engineers Gold Medal for the year 1989. He has many publications in national and international journals to his credit. K. N. Vijeyakumar received the Bachelor’s degree in Electronics and Communication Engineering and Master’s degree in Applied Electronics from Anna University, Chennai. He is currently an Assistant Professor of R Electronics and Communication Engineering in Anna University Regional Centre, Coimbatore, Tamil Nadu, India. His research interests include low power design, ultra-low voltage design, image processing, signal processing and nanotechnology devices. He is a member of IEEE and IE. He has published about 9 reserch papers Anandamoorthy Manicka Kubendran received the B.E. degree from RVS College of Engg. and Tech, Anna University of Technology, Tiruchirappalli, India, in 2007, and M.E. degree from Anna University Regional Centre Coimbatore, Anna University, Chennai, India, in 2013. His research interest includes design of high-speed arithmetic circuits for image and signal processing, Low power VLSI design and wireless communication. Copyright © 2013 Praise Worthy Prize S.r.l. - All rights reserved International Review on Computers and Software, Vol. 8, N. 10 2499  International Review on Computers and Software (IRECOS) (continued from outside front cover) A Case Study of Using RM-ODP in Mobile Cloud Computing Applications 2428 by M. Jebbar, A . Sek k ak i, O. Benammar Spam Detection and E limination of Messages from Twitter 2438 by Sajin S. Chandran, Murugappan S. Improving Search Results Through Reducing Replica in User Profile 2444 by P. Srinivasan, K. Batri An E valuation of the Movie Song Browser System Among IT and Non-IT Users 2453 by Munauwarah, Nazlena Mohamad A li, Hyowon L ee An Access Control Model of Web Services Based on Multifactor Trust Management 2460 T by R. Joseph Manoj, A . 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Jayak umari Abstracting and Indexing Information: Cambridge Scientific Abstracts (CSA/CIG) Academic Search Complete (EBSCO Information Services) Elsevier Bibliographic Database - SCOPUS Index Copernicus (Journal Master List): Impact Factor 6.14 Autorizzazione del Tribunale di Napoli n. 59 del 30/06/2006  T IN R EP R 1828-6003(201310)8:10;1-A Copyright © 2013 Praise Worthy Prize S.r.l. - All rights reserved