Field Programmable Gate Array Applications- A Scientometric Review

computation Article Field Programmable Gate Array Applications— A Scientometric Review Juan Ruiz-Rosero 1, * , Gustavo Ramirez-Gonzalez 1 and Rahul Khanna 2 1 Departamento de Telemática Universidad del Cauca, Calle 5, No. 4-70, Popayan, Cauca 190002, Colombia; [email protected] 2 Intel Corporation, 2111 NE 25th Ave., Hillsboro, OR 97124, USA; [email protected] * Correspondence: [email protected]; Tel.: +57-(2)-820-9900


Received: 9 September 2019; Accepted: 25 October 2019; Published: date
 Abstract: Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications. Keywords: FPGA; Field Programmable Gate Array; applications; digital control; networking; security; machine learning; big data; image processing; ScientoPy 1. Introduction A Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that contains logic blocks whose interconnection and functionality can be configured by a customer or a designer after manufacturing [1]. In this way, we can build inside an FPGA from a simple logic gate to a complex systems on chip or even a artificial intelligence system. As a result, FPGAs have been used for many different application such as digital signal processing [2–4], image processing [5–7], cryptography [8–10], parallel processing [11,12], fault tolerance systems [13–15], low power systems [16,17], simulation [18–20], digital control [21–23], artificial intelligence [24–26], networking [27,28], big data [29–32], among others. Nowadays, we found several literature reviews and survey papers for different FPGAs applications like industry [33–35], power Electronics [36], fault tolerance [14,37–39], partial reconfiguration [40], photovoltaic systems [41], Sensors system based [42,43], network infrastructure security [44], LDPC (low-density parity-check) decoders [45], CORDIC algorithms [46], cryptography [8,47], deep learning [48–51], digital modulation techniques [52], low power design [53], robotic controllers [54], automotive safety [55], digital filters [56,57], Unmanned Aerial Vehicles (UAV) [58,59] and random number generators [60]. Similarly, we found books that summarize FPGAs’ applications for scientific research [61,62]. These previous studies found in the related papers show the review of specific topics inside FPGA applications and the related books review some FPGAs’ Computation 2019, xx, 5; doi:10.3390/computationxx010005 www.mdpi.com/journal/computation Computation 2019, xx, 5 2 of 115 applications with practical examples but do not include the top applications like image processing and machine learning. Thus, the propose of this study is to provide an extensive overview of the top FPGAs’ applications by a scientometric review, covering publications related to FPGA from 1992 to 2018. Correspondingly, in this paper, the main FPGAs’ applications are divided into eleven main categories and five subcategories. Figure 1 shows an overview of this paper. Section 2 presents the materials and methods used to extract the bibliographic dataset, preprocessing steps and type of analysis performed. Sections 3 to 13 show the eleven FPGAs’ applications categories, Section 14 illustrates the relationship between the main FPGA-based applications and implementations and Section 15 discusses the main findings of this study. Paper organization 2. Materials and Methods 3. Digital Control 4. Communication Interfaces 4.1. Parallel 4.2. Serial 5. Networking 6. Computer Security 6.1. Cryptography Techniques 7. Machine Learning 8. Digital Signal Processing 8.1. Digital Filters 9. Image and Video Processing 9.1. Compression Standards 10. Big Data 11. Computer Algorithms 12. Other Implementations 13. Other Applications 14. Applications Mapping 15. Discussion Figure 1. Organization of the paper. 2. Materials and Methods In this section, we describe the dataset collection, including the preprocessing steps and the review methodology that we used to analyze the dataset collected for this review. 2.1. Dataset Collection We built the dataset using two bibliographic databases: Clarivate Web of Science (WoS) and Scopus. The search string for this analysis was: “Field-programmable gate array*” OR “Field programmable gate array*” OR “FPGA*”. We applied this string to the topic search in WoS and Scopus, which includes title, abstract, author’s keywords and KeyWords Plus R (for WoS). With this search criteria, we downloaded the data set within a day on 19th March 2019. Then, we preprocessed it in ScientoPy. Figure 2 shows the preprocess brief graph that presents the entire loaded documents for each database and the removed duplicated documents, respectively. Since the ScientoPy preprocessing script keeps WoS documents over Scopus documents, after the duplication removal, we see more documents from WoS than Scopus databases. Computation 2019, xx, 5 3 of 115 Documents kept Removed dupl. WoS 2% Scopus 63% 0 20000 40000 60000 80000 Total loaded documents, with percentage of removed documents Figure 2. Field Programmable Gate Array (FPGA) total loaded documents from Clarivate Web of Science (WoS) and Scopus databases, with the percentage of removed documents after duplication removal filter. Table 1 shows the brief preprocessing table generated by ScientoPy. This table describes the input dataset including in the second column (Number) the number of publications after and before the duplication removal filter per database, and the third column (Percentage) the relative percentages (see table description for detailed information about these percentages). Loaded papers represents the total number of documents loaded from both databases. Omitted papers by document type are the number of documents outside the default documents type filter (only including conference papers, articles, reviews, proceedings papers and articles in press). Papers after omitted papers removed are the number of documents inside the default documents type filter. Loaded papers from WoS/Scopus are the number of documents from each database after the omitted papers had been removed. Duplicated papers found are the duplicated total number of documents that have been found and removed. Removed duplicated papers from WoS/Scopus are the number of documents removed from each database after the duplication removal. Total number of papers after rem. dupl. are the number of documents after duplication removal by the preprocessing. Finally, Papers from WoS/Scopus are the whole number of documents from WoS and Scopus, respectively, after the duplication removal. The duplication removal filter used by ScientoPy is based on the DOI match or if the DOI is not present in the documents’ title and documents’ first author last name match. Table 1. FPGA dataset preprocess brief table. Omitted papers by document type, Loaded papers from WoS/Scopus and Duplicated papers found percentage relative to Loaded papers. Removed duplicated papers from WoS/Scopus percentages relative to Loaded papers from WoS/Scopus respectively. Papers from WoS/Scopus percentage relative to Total number of papers after rem. dupl. Information Number Percentage Loaded papers 127,597 Omitted papers by document type 3621 2.8% Papers after omitted papers removed 123,976 Loaded papers from WoS 51,010 41.1% Loaded papers from Scopus 72,966 58.9% Duplicated removal results: Duplicated papers found 46,592 37.6% Removed duplicated papers from WoS 836 1.6% Removed duplicated papers from Scopus 45,756 62.7% Total number of papers after rem. dupl. 77,384 Papers from WoS 50,174 64.8% Papers from Scopus 27,210 35.2% Computation 2019, xx, 5 4 of 115 2.2. Review Methodology Manual scientific reviews such as systematic and literature reviews have limitations to cover a vast research area such as FPGAs based applications completely. For this reason, we used a scientometric review methodology. Using ScientoPy, we extracted and analyzed the top applications and implementations based in FPGAs [63]. We took the total 77,384 papers’ bibliographic information to perform a scientometric analysis with ScientoPy to extract the first 5000 top author’s keywords. Then, we extracted the author’s keywords related to FPGAs’ applications from this list to arrange them into eleven different categories (digital control, communication interface, networking, computer security, machine learning, digital signal processing, image and video processing, computer algorithms, other implementations and other applications). Then, we analyze in depth each category by extracting with ScientoPy the statistical graph corresponding to the most used author’s keywords for each topic. In that way, for instance, in the Machine learning section, we got the ScientoPy statistical graph for the top author’s keywords related to machine learning techniques developed in FPGAs. The author’s keywords that we present in the graphs represent the group of similar author keywords that belong to the same topic, such as abbreviations, plural/singular words or dashes between words. For example, in machine learning, we got the “support vector machine” phrase (enclosing: support vector machine, SVM, support vector machines) or in Computer security/Cryptography we got RSA (enclosing: RSA, Rivest-Shamir-Adleman (RSA), Rivest-Shamir-Adleman, Rivest Shamir Adleman). For the topic trending analysis, we use here two indicators. The Average Documents per Year (ADY) that is the average number of documents published in each specific topic in the last three years (2016–2018). This indicator represents the topic absolute-number of publications growth and generally is high when we have a high positioned topic. Unfortunately, this is not a good indicator of a new trending topic, in which absolute growth is generally low but its relative growth is high. For these cases, we have the second indicator called Percentage of Documents in the Last Years (PDLY) that represents the percentage of documents published in the last three years (2016–2018) for a specific topic relative to the total number of documents published for this topic. Therefore, we extracted the statistical graphs from ScientoPy using these indicators, with graphs divided into two categories: • Parametric evolution graph: this graph has two parts. The first part (left side) presents the accumulative number of documents (or papers) versus the publication year of each topic (in this case author’s keywords). With this graph, we can observe the starting year at the line’s start and the total number of documents at the line’s end. In some graphs, we put the Y-axes on a logarithmic scale to note the starting year of each topic easily. On the right side, we get the parametric plot. Here, we present the ADY and PDLY of each topic, to show the growth of the total number of documents (ADY) and the relative growth (PDLY) in the last years. • Trending bar graph: if we need to analyze many topics in a specific section (usually more than ten topics), we use this kind of graph. Here we present the different topics in the Y-axis related to the total number of documents per topic in the X-axis with bars. Also, here we highlight in orange in the bar the documents published in the last three years (in this case 2016 to 2018), including the PDLY value. Finally, for the analysis of the topics, we include the definition of each topic, the specific implementations or applications with FPGAs related to the topics and the citation of the papers that includes the related implementation or application. Here, we cited the most relevant to the application, the ones with more citations and the newest papers for each specific application. 3. Digital Control Digital control uses digital systems to act as system controllers to control a system in an optimum manner without delay or overshot and ensuring stability [64]. Implementation of this kind of controllers in FPGAs allows highly parallel, high-speed processing and shorter delays. Most of Computation 2019, xx, 5 5 of 115 the documents listed here are related to fuzzy control and Proportional Integral Derivative (PID) control. Nevertheless, sensorless control has the highest PDLY and model predictive control has the highest ADY (see Figure 3). Fuzzy control has been implemented in FPGAs to comply with the requirements of high-sampling-frequency control systems such as permanent-magnet synchronous motor drives [65], vehicle semi-active suspension system [66] or Continuous Variable Camshaft Timing (CVCT) system [67]. PID implementations in FPGAs allows high-speed and high-precision systems developed for DC-DC voltage converters [68,69], nuclear fast reactors [70] and even for the controller of the magnetic suspension mass comparator system (MSMC) used for the redefinition of the kilogram at the National Institute of Standards and Technology [71]. 105 Fuzzy control Average documents per year, 2016 - 2018 (doc./year) PID Model predictive control 8 90 Adaptive control Accumulative Number of Documents Sensorless control 75 Distributed control 6 60 45 4 30 2 15 0 0 1992 1995 1998 2001 2004 2007 2010 2013 2016 2019 0% 10% 20% 30% 40% Publication year Percentage of documents published in the last years 2016 - 2018 Figure 3. Digital control top implementations in FPGA research. The Model Predictive Control (MPC) uses a model to predict the process output at future time instants to calculate a control sequence for minimizing an objective function [72]. MPC is a quadratic programming (QP) problem, where two critical factors determine the success of MPC applications: the availability of a suitable plant model and the ability to solve the quadratic programming problem within the prescribed sampling period [73]. The QP implementation in FPGAs provides an accurate real-time closed-loop simulation that meets the control deadlines [74]. This kind of implementations includes torque control at very low and zero speed [75], three-phase inverters [76,77] or spacecraft rendezvous in elliptical orbits [78]. In the adaptive control, the controller adapts to a controlled system with parameters that can vary or are uncertain, such as an airplane where its mass change as a result of the fuel consumption [79]. These control systems have been implemented using FPGAs in robotics applications [80–83], tunnel lighting systems [84], microgrids [85] and chaotic systems [86,87]. Sensorless control publications involve, for example, electrical motor speed and position control techniques that do not need a physical sensor. These techniques estimate the rotor position and speed by using algorithmic estimator techniques divided into two—the high-frequency injection method and the estimation-based techniques [88]. The estimation-based techniques use the Extended Kalman Filter (EKF) for position estimation due to its ability to extract the needed data from a random-noisy environment [89]. Real-time system based on FPGAs are used to implement the EKF matrix operations [89], vector controller [90,91] and FPGA’s oversampling technique for a flux observer [92–94]. Distributed control techniques are designed to process decentralized systems for distributed cells, where each cell processes different types of information. Each cell has autonomy in local optimization and also all integrate a large complex system [95]. FPGA-based distributed control techniques Computation 2019, xx, 5 6 of 115 have been used for applications like micro-electromechanical systems arrays for air-flow planar micro-manipulation [96], music playing robots [97–99], telescopes control [100] and for reconfigurable FPGA-based systems [101–103]. 4. Communication Interfaces The communication interfaces allow the data transmission and reception between the FPGA-based systems and its peripherals or storage devices. For this review, we have divided these interfaces into two (parallel and serial interfaces). 4.1. Parallel Parallel communication interfaces in FPGAs are used for high speed data acquisition, communication protocols and memory interfaces. As seen in Figure 4, the most used case are the image and video capture interfaces. First, the Charge-Coupled Device (CCD) is an image sensor used for different kind of applications (image [104], video [105], X-rays [106] and astronomical [107]). FPGAs’ implementations has involved the CCD interface for high speed data acquisition [108–110], noise reduction [111,112], ultra-high resolution [113,114], among others. CMOS image Sensors interface are also widely implemented in FPGA for high frame rate processing [115,116], exposure control [117–119] and dynamic range [120,121]. 4.0 CCD Average documents per year, 2016 - 2018 (doc./year) 80 CMOS image sensor PCI 3.5 70 VGA Accumulative Number of Documents SDRAM 3.0 DDR2 60 DDR DDR3 2.5 50 DDR4 HBM 2.0 40 1.5 30 20 1.0 10 0.5 0 0.0 1992 1995 1998 2001 2004 2007 2010 2013 2016 2019 0% 25% 50% 75% 100% Publication year Percentage of documents published in the last years 2016 - 2018 Figure 4. Parallel communication interfaces top implementations in FPGA research. PCI (Peripheral Component Interconnect) is one of the older interfaces used for FPGA communications. According to Figure 4, publications related to this topic started in 1996 [122] and finished in 2016, due to this interface being replaced by the PCI Express. The VGA (Video Graphics Array) implementations include video and color scaling [123,124], video capturing [125] and real-time display [126,127]. The memory interfaces for FPGAs have grown in a similar time that these interfaces have emerged. For instance, in 2004, the FPGAs were used for monitoring the SDRAM (Single Data Rate Synchronous Dynamic Random-Access Memory) data retention under electromagnetic irradiation environments [128,129]. The DDR (Double Data Rate) implementation also started in 2004 with the design of a memory scheduler [130]. DDR2 implementations started in 2008 with the design of a high-speed camera system, capable of capturing 500 frames per second [131]. DDR3 documents started in 2013 with the design of a 3D volumetric display system, which uses the DDR3 memory as a high-capacity high-bandwidth video frame buffer [132]. DDR4 implementations started in Computation 2019, xx, 5 7 of 115 2016, with the study of thermal and energy-efficient in the memory interface design for 28nm FPGAs [133,134]. Finally, in 2017, Gandhi et al. show the integration challenges for FPGA and HBM (High Bandwidth Memory) via an interposer interface [135]. These last two implementations (DDR4 and HBM) have 100% of PDLY for the last three years, which indicates that they are trending topics for the last three years. 4.2. Serial Drive to higher bandwidth interfaces in computing devices has resulted in a major adoption of the serial communication interfaces [136]. That also has been reflected in FPGAs’ research. Figure 5 shows a high increase in publication related to serial communication interfaces. Implementations for Ethernet physical layer in FPGAs are popular nowadays in next-generation Gigabit Ethernet implementations [137,138]. Also, precision delay measurement techniques have been developed to support the IEEE 1588 Precision Time Protocol [139–143]. Similarly, a security network processor was developed using FPGA for high-performance online security protocols processing [144,145]. Ethernet 14 Average documents per year, 2016 - 2018 (doc./year) 100 MIMO USB PCIE 12 Accumulative Number of Documents RFID UART CAN 10 SPI 10 I2C SATA 8 6 4 1 2 0 0 1992 1995 1998 2001 2004 2007 2010 2013 2016 2019 0% 20% 40% 60% Publication year Percentage of documents published in the last years 2016 - 2018 Figure 5. Serial communication interfaces top implementations in FPGA research. The multiple-input and multiple-output (MIMO) is the communication method implemented in FPGAs’ research with the highest ADY. FPGAs allows real-time MIMO-OFDM (MIMO Orthogonal frequency-division multiplexing) transceivers implementations for multiple streams [146–148]. Also, channel estimation for MIMO uses FPGAs for efficient hardware resource utilization [149] and fast prototyping algorithms [150,151]. The USB (Universal Serial Bus) interface has been widely used for FPGAs’ boards to a host computer communications [152–156]. In the same way, some authors have built FPGA security systems for monitoring and detecting USB cable attacks [157] and also for building cryptography systems to add security to USB devices [158]. PCI Express (PCI-E) is nowadays the most used interface for high-performance communication between FPGAs and host-CPU (host - Central Processing Unit) [159,160], GPUs (Graphic Processing Units) [161,162] or other FPGAs [163,164]. On the other hand, other researchers have worked with FPGAs and RFID (Radio Frequency Identification) for security analysis and RFID new implementations [165–167], hardware UART (Universal Asynchronous Receiver/Transmitter) implementation and simulation [168–170], CAN (Controller Area Network) bus routers [171] and gateways [172]. SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Circuit) communications are mostly used for FPGA to MEMS (Microelectromechanical systems) communications [173,174]. Computation 2019, xx, 5 8 of 115 Finally, SATA (Serial Advanced Technology Attachment) interface has been implemented in FPGAs for high-speed data storage [175–177]. 5. Networking According to our dataset, the FPGAs have been used for networking applications since 1994. Figure 6 shows the top FPGA-based applications for networking. In Software Defined Radio (SDR), the components that have been traditionally implemented in hardware (such as mixers, filters and modulators) are instead implemented in software (computers or embedded systems) [178]. The SDN (Software-Defined Networking) implementations based on FPGA includes OFDM modulators [179–183], BPSK (Binary Phase Shift Keying) modulators [184,185], QPSK (Quadrature Phase Shift Keying) modulators [184,186], GNSS (Global Navigation Satellite System) and GPS (Global Positioning System) receivers [187–190], CDMA (Code-Division Multiple Access) [191] and QAM (Quadrature Amplitude Modulation) modulators [192,193]. SDR 35 Average documents per year, 2016 - 2018 (doc./year) NoC Routing 100 Cognitive Radio 30 Accumulative Number of Documents Beamforming LTE 25 Packet Classification ZigBee WiMAX 20 10 SDN 5G 15 10 1 5 0 0 1992 1995 1998 2001 2004 2007 2010 2013 2016 2019 0% 20% 40% 60% 80% Publication year Percentage of documents published in the last years 2016 - 2018 Figure 6. Networking top implementations in FPGA research. Network on chip (NoC) is a paradigm which aims to solve the communication issues between the CPU units of the next generation of many core System on Chip (SoC). Some FPGA-based implementations to solve NoC problems include network switches typologies [194–199], buffer handling [200,201], router implementations [196,202–207] and NoC simulators [208–210]. Routing applications are the first that have been implemented in FPGAs for networking, starting in 1994 [211]. These includes packet processing [212,213], NetFPGA platform to prototyping networking devices (switches and routers) [214–216] and parallel routing [217–222]. Cognitive radio tries to solve the spectral congestion by using the best wireless channels in its vicinity to avoid user interference and congestion [223]. In this area, FPGAs have been using for spectrum sensing [224–237], reconfigurable antennas [238,239] and adaptive codec [240]. Beamforming is a signal processing technique for directional signal transmission or reception in sensor arrays [241]. This keyword is correlated for FPGAs applications to beamforming in radio communications systems and beamforming in ultrasound imaging. In this section, we are analyzing the first one. For radio communications systems, beamforming applications with FPGAs consist of band Infinite Impulse Response (IIR) beam filters [242,243] and beamforming Direction Of Arrival (DOA) estimation [244]. Long-Term Evolution (LTE) applications related with FPGAs started in 2010 [245,246] and these include the implementation of the Physical Downlink Shared Channel (PDSCH) [247,248], Physical Downlink Control Channel (PDCCH) [249,250], efficient implementation of a parallel-pipelined Computation 2019, xx, 5 9 of 115 configurable FFT/IFFT (Fast Fourier Transform / Inverse Fast Fourier Transform) processor [251–254]. FPGAs play a crucial role in networking packet classification, because, due to the scalable and parallel models than can be built inside these systems, efficient and high-speed packet classification systems have been designed [255–259]. These systems have been applied to firewalls [260,261] and OpenFlow capable switches [262]. ZigBee is a high-level communication protocol based on the IEEE 802.15.4 standard used in personal area networks such as home automation, smart farming and other low power and low bandwidth applications [263]. FPGA applications in this protocol includes more efficient ZigBee transceivers and MAC (Medium Access Control) protocol implementations [264–268] and data encryption in security improvement for ZigBee networks [269–271]. 5G (5th Generation) is the latest generation of cellular mobile communications that aims at the high data rate, improve the latency and the energy-saving [272]. WiMAX (Worldwide Interoperability for Microwave Access) is a wireless technology to provide last mile Internet broadband access [273] and it was a candidate for 4G communications, in competition with LTE. FPGA implementations for this technology includes OFDM transceiver [274,275], SDR [276–278] and Viterbi decoders [279–281]. Nevertheless, WiMAX lost the competition for 4G. As a result, we see it as the lowest ADY on this list. Software-Defined Networking (SDN) is a network management approach that enables programmatically efficient network configuration to improve network performance and monitoring [282]. For SDN we can find implementations in FPGA related to ultra low latency data center services [283], Software Defined Hardware Counters (SDHC) for dynamic network statics [284], high speed network (10Gbps) performance evaluation [285], packet arrival time measurement [286] and anomaly-based intrusion detection [287]. Similarly, as for SDR, in SDN we found several implementation based on NetFPGA platform [215,285,286,288–293]. FPGAs’ applications for 5G have the highest PDLY (see Figure 6). These applications have helped to enable this new technology from 2014 with implementations like the antenna testbed for massive MIMO [294,295], transceiver modulator/demodulator enablers [296–299], time delay and latency estimation [300,301] and beam direction of arrival estimation [302] 6. Computer Security Computer security or cybersecurity aims to protect confidentiality, integrity and availability of data and assets used in cyberspace [303]. Figure 7 shows the top FPGAs’ applications for computer security with their number of documents and the PDLY. The first one is fault tolerance with near to 400 documents. This is a feature that enables a system to continue operating properly in the event of a failure [304] and it is widely used for space [305–310], automotive [311,312] and robot controllers applications [313,314]. NASA defines Single Event Upset (SEU) as “radiation-induced errors in microelectronic circuits caused when charged particles (usually from the radiation belts or from cosmic rays) lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs”. Then SEUs are random software errors of a transient nature in integrated circuits but are not generally non-destructive to hardware [315]. FPGAs have been used to built fault tolerance systems against the SEU [316–319]. Another security topic is fault injection, which involves inserting faults into a particular target at a determined time in the process and monitoring the results to determine its behavior in response to this generated fault [320]. Implementations of this kind in FPGAs help to efficiently analyze the performance of fault tolerance systems [320–324]. Side-channel attacks (SCA) refers to any attack based on information leaked for a cryptographic module that performs encryption or decryption of secret parameters via power dissipation, electromagnetic radiation or operating times as side-channel information [325]. FPGAs’ research in this area covers FPGAs’ vulnerabilities to SCA [326–328], security resistant designs against SCA [329–334] and hardware Trojan detection [335–337]. Physically Unclonable Function (PUF) is a noisy function that when queried with a challenge x, it generates a response y that depends on both x and the unique device-specific intrinsic physical properties of the object that contains the PUF [338]. In that way, the PUF is used as a digital fingerprint to identify a semiconductor device. FPGAs’ applications for PUF Computation 2019, xx, 5 10 of 115 have the highest PDLY (62% of the documents published in the last three years) and these includes Ring Oscillator (RO) based physical unclonable function [339–343] and PUF strong evaluation [344–347]. Fault tolerance 30% Single event upset 24% Fault injection 37% Side-channel attacks 39% Physical Unclonable Function 62% Triple modular redundancy 36% Front-end electronics for detector readout 35% Fault detection 32% Fault diagnosis 32% Low-density parity-check 31% Built-In Self Test 22% Hash function 23% Cyclic Redundancy Check 18% Before 2016 Intrusion detection 20% Between 2016 - 2018 0 100 200 300 400 Total number of documents, with percentage of documents published in the last years 2016 - 2018 Figure 7. Security top applications in FPGA research Triple Modular Redundancy (TMR) is a fault-tolerance method, in which at least three systems perform a process and the result is processed by a majority voting system to produce a single output [348]. FPGAs are the perfect system to implement TMR due to its parallel design architecture. Applications of TMR in FPGAs covers novel design techniques of TMR [349–352] and TRM SRAM based systems [353–355], among others. FPGAs’ systems can capture and process information at a very high speed compared with conventional systems. For this reason, FPGAs’ systems have been widely used as front-end Electronics for detector readout calorimeters [356–358], neutrino detectors [359,360] and even particle tracking systems for the Large Hadron Collider (LHC) [361–365]. Other applications in our top list related to FPGAs are fault detection systems [366–371], fault diagnosis [372–377], Low-Density Parity-Check (LDPC) implementations for error correcting code in transmission [378–381], magnetic storage systems [382,383], Built-In Self Test (BIST) [344,384–388], hash function implementations [389–394], parallel and high speed Cyclic Redundancy Check (CRC) implementations [395–398] and efficient intrusion detection systems [399–404]. 6.1. Cryptography Techniques Cryptography techniques are created for securing digital information, transactions and distributed computations from third parties or the public that attempt to read private messages [405]. Figure 8 shows the top FPGAs’ cryptography techniques implementations. Advanced Encryption Standard (AES), also know as Rijndael, is the most popular encryption technique that researches have implemented in FPGAs, with 510 documents. These implementations have been made to increase the encryption speed [406–410], generate small footprint and cheap designs [167,411,412], test the encryption against fault injections/attacks [413,414] and to improve the fault detection/tolerance systems [366,415,416]. Elliptic Curve Cryptography (ECC) is increasingly used in practice to instantiate public-key cryptography protocols, based on the algebraic structure of elliptic curves over finite fields [417]. In FPGAs’ cryptography applications, it has the second ADY, with an average of 27 documents per year (2016 to 2018). FPGAs’ implementations of these cryptography techniques includes efficient ECC processors [418–420], side-channel attack resistant implementations [329,331] and high speed implementations [421,422]. Computation 2019, xx, 5 11 of 115 AES Average documents per year, 2016 - 2018 (doc./year) ECC 50 RSA Accumulative Number of Documents 100 Viterbi decoder Block cipher Stream cipher 40 DES SHA-3 S-Box 30 10 20 1 10 0 0 1992 1995 1998 2001 2004 2007 2010 2013 2016 2019 10% 15% 20% 25% Publication year Percentage of documents published in the last years 2016 - 2018 Figure 8. Cryptography top implementations in FPGA research. RSA (Rivest–Shamir–Adleman) is one of the first public-key cryptography algorithm and it is based on the practical difficulty of the factorization of the product of two large prime numbers [423]. For RSA we found different FPGAs’ implementations such as efficient or accelerated architectures [424–426], side-channel attacks resistant [427,428], tiny footprint [429] and Vedic mathematics based implementation [430]. Other cryptography techniques implemented in FPGAs are the Viterbi decoder with reconfigurable capabilities [279], high speed Viterbi decoders [431,432], steam cipher chaos-based techniques [433–436] and lightweight block cipher [437–439]. The Data Encryption Standard (DES) is an old encryption standard that is insecure for modern applications but has influenced in the advancement of modern cryptography [440]. FPGAs have been used to built cryptanalysis to crack a DES key [440–442], for DES pipelined implementations [443] and speed/power efficient implementations [444–446]. In 2008, the NIST (National Institute of Standards and Technology) started the competition for the new cryptographic Secure Hash Algorithm (SHA-3) [447]. Figure 8 shows that the implementations in FPGAs for SHA-3 started in 2009 with test and comparatives for SHA-3 candidates [448–453]. On October 2012, the Keccak cryptographic function was selected as the winner of the competition [454] and then implementations for the Keccak SHA-3 started in FPGAs [455], such as high throughput/performance [456–459], IoT focused applications [457] and compact implementations [460]. Finally, S-Box (Substitution-Box) is a substitution transformation used to obscure the relationship between the key and a encrypted text [461]. S-Box technique has been implemented in FPGAs for high throughput processing [462–464], memory efficient [465–468], low latency [469] and low power implementations [470–472]. 7. Machine Learning Machine learning is one of the top FPGA-based applications. Figure 9 shows the most implemented machine learning techniques for this architecture, where the neural network is the top one. These neural network implementations have been applied to pattern recognition [473–476], photovoltaic optimizations [25], modeling [477,478], controllers [479] and diagnostics [372]; power quality [480,481]; robotics control [482], robotics object detection and manipulation [483] and finally robotics object seeking [484]. Secondly, genetic algorithm applications include image processing [485–488], task scheduling [489–491], frequency estimation for digital relaying in power electrical systems [492–495] and mobile robots path planning [496–499]. Computation 2019, xx, 5 12 of 115 Neural network Average documents per year, 2016 - 2018 (doc./year) Genetic algorithm 60 Support vector machine Accumulative Number of Documents 100 Spiking neural network AdaBoost 50 40 10 30 20 1 10 0 0 1992 1995 1998 2001 2004 2007 2010 2013 2016 2019 10% 20% 30% 40% Publication year Percentage of documents published in the last years 2016 - 2018 Figure 9. Machine learning top implementations in FPGA research. Support Vector Machine (SVM) are widely used for classification and regression analysis [500]. The implementation of this technique in FPGAs is one of the newest, starting in 2002 (see Figure 9). The SVM has been used in FPGAs alongside the Histogram of Oriented Gradients (HOG) for object classifications in image processing [501–505]. Other SVM applications include facial expression recognition [506–508], network traffic classification [509], melanoma detection [510–512], arrhythmias detection [513,514], epilepsy detection [515] and stress detection [516]. The spiking Neural Netw. are a more biologically realistic model, with spiking neurons that transfer the information in the precise timing of spikes or a sequence of them [517]. For FPGAs, this machine learning technology has the highest PDLY (51% in the last three years). Some applications of this technique in FPGAs include character recognition [518,519], sound recognition [520,521] and other patterns/object recognition [522,523]. The AdaBoost technique (short for Adaptive Boosting) improves the performance of a weak learning and classifier algorithm into a strong one. This machine learning technique is the newest that has been implemented with FPGAs in our list (starting in 2005). It has been widely applied for image processing in face detection [524–528] and also for human detection [501,529]. 8. Digital Signal Processing Digital Signal Processing (DSP) is the performing of signal processing using digital techniques by a computing device [530]. Figure 10 shows the top DSP techniques implemented in FPGAs without covering digital filters, which are covered in the next sub section. Fast Fourier Transform (FFT) is the most implemented DSP technique in FPGAs, with near to 677 documents related to it. Here, we found CORDIC-based FFT [531–536], double-precision floating-point FFT [537], OFDM systems based in FFT [538–542], radix-2 FFT [543,544] and radix-4 FFT [533,545–547] implementations. The Discrete Wavelet Transform (DWT) is a wavelet transform by a certain orthonormal series generated by a discrete wavelet to capture both frequency and location information [548]. The DWT have been implemented in FPGAs for image and video compression [549–553], digital watermarking [554,555], EEG (Electroencephalography) signal processing [556–558] and general image processing [559–561]. Computation 2019, xx, 5 13 of 115 Fast Fourier Transform 25% Discrete Wavelet Transform 24% Time-to-digital converter 32% Discrete cosine transform 22% Total Harmonic Distortion 42% Interpolation 24% Lifting scheme 21% Convolution 23% Before 2016 Jitter 19% Between 2016 - 2018 0 100 200 300 400 500 600 700 Total number of documents, with percentage of documents published in the last years 2016 - 2018 Figure 10. Digital signal processing top implementations in FPGA research. Time-to-digital converters (TDC) are designed to measure a time interval and convert it into digital output [562]. FPGAs’ implementations of TDCs offer high accuracy in time measurement. These technique has been used for Positron Emission Tomography (PET) [563–566], Light Detection And Ranging (LIDAR) [567,568] and high speed ADC (Analog-to-digital converter) [569,570]. Discrete Cosine Transform (DCT) implementations in FPGAs have been applied to MPEG-based video encoders [571–573], JPEG encoders [574,575], for the Pierre Auger cosmic rays observatory front end detectors [576–579] and recently to image mosaicing systems [580]. Total Harmonic Distortion (THD) is a measure of the effective value of the harmonic components of a distorted waveform and it is commonly used for a quick measure of distortion [581]. THD implementations in FPGA have the highest PDLY in this category (43% of documents in the last three years) and these have been implemented in FPGAs for multilevel inverters [582–585], AC (Alternating Current) LED (Light-Emitting Diode) drivers [586–589]. Interpolation with FPGAs have been used for video scaling [590–592] and motion estimator for High Efficient Video Coding (HEVC) encoder [593–595]. Other digital signal processing implementations in FPGAs includes lifting scheme for efficient and modular DWT [596–599], efficient convolution techniques [600–602] and 3D convolution [603]. Finally, in our list is the jitter detection (deviation from true periodicity of a presumably periodic signal) using FPGAs [604], which includes jitter studies for 5G communications [301], Multi-Gigabit FPGA-Embedded Serial Transceivers [605], clock oscillators [606] and random number generators based on clocks signal jitter [607–609]. 8.1. Digital Filters A digital filter is a filter that operates on digital signals to perform mathematical operations to reduce or enhance certain aspects of that signal [610]. Figure 11 shows the top digital filters techniques implemented in FPGAs. Finite Impulse Response (FIR) filter is a filter where the output is computed as a weighted, finite term sum of past, present and perhaps future values of the filter input [611]. FPGAs have been used for efficient implementation of FIR filters using distributed arithmetic [612–615] and for high speed/low power implementations [616–618]. The Kalman filter uses a series of measurements observed over time, which include statistical noise and other inaccuracies, to produce an estimate of unknown variables [619]. FPGAs were used for high performance/efficiency implementation of Computation 2019, xx, 5 14 of 115 Kalman filters [620–622], IMU (Inertial Measurement Unit) Sensors fusion [623–625] and real-time filtering [626–628]. FIR Average documents per year, 2016 - 2018 (doc./year) Kalman filter 100 Median filter 25 LMS Accumulative Number of Documents CIC Filter IIR Matched filter 20 10 15 10 1 5 0 0 1992 1995 1998 2001 2004 2007 2010 2013 2016 2019 15% 20% 25% 30% Publication year Percentage of documents published in the last years 2016 - 2018 Figure 11. Digital filters top implementations in FPGA research. Median filters implementation in FPGAs includes application for image processing [629–632], low power median filters [633,634] and high speed/real-time applications [635–637]. The Least Mean Squares (LMS) filter is an adaptive filter that finds the adequate filter coefficients to produce the least mean square error of the difference between the desired and the actual signal [638]. The LMS filters have been used in FPGAs for active noise cancellation in headphones [639], echo cancellation [640–642] and non invasive fetal ECG (Electrocardiogram) [643,644]. Other digital filters implementations in FPGAs include Cascaded integrator–comb (CIC) filter [645–649], Infinite Impulse Response (IIR) filters [650–653] and matched filter [654–658]. 9. Image and Video Processing Image and video processing techniques comprise the use of computer algorithms to perform video/image acquisition, compression, preprocessing, segmentation, representation, extraction, recognition and interpretation [659]. These techniques involve one of the most important applications in FPGAs. Figure 12 shows the top image and video processing techniques implemented in FPGAs, without including image and video/image compression standards that we include in the following subsection. First, stereo vision tries to infer the scene geometry from two or more images taken simultaneously from slightly different viewpoints [660]. This is the top image/video processing technique in FPGAs with 161 documents and includes real-time stereo vision implementations [661–664], Census transform [665,666], 3D reconstruction systems [667,668] and even the use of this technique with FPGAs for the Mars rovers navigation systems [669,670]. Face detection and recognition is the second topic in this list. Applications related to this topic in FPGAs include face detection with Haar classifiers [671–674], real-time/high speed face detection/recognition [675–680], AdaBoost based face detection [524,527,681] and Viola-Jones based face detection algorithm [682–684]. Edge detection aims to identify points in an image at which the brightens or other image characteristics changes sharply. FPGAs’ implementations for edge detection cover implementations based in Sobel operator [685–689], Canny algorithm [690–692], applications for real time processing [693–697], image segmentation [698,699], DNA (Desoxyribonucleic Acid) microarray image processing [700,701] and object detection [702–704]. Computation 2019, xx, 5 15 of 115 Stereo vision 29% Face detection 25% Edge detection 32% Digital watermarking 27% Image enhancement 22% Image segmentation 19% Object tracking 20% Object detection 32% Optical flow 16% Before 2016 Hough transform 27% Between 2016 - 2018 0 25 50 75 100 125 150 175 Total number of documents, with percentage of documents published in the last years 2016 - 2018 Figure 12. Image and video compressing processing top techniques implementations in FPGA research. Digital watermarking is the act of hiding information in multimedia data, such as image, video or audio, for content protection or authentication [705]. FPGAs in digital watermarking have been used for real time watermarking detection in video [706,707], Discrete Cosine Transform (DCT) based digital image watermarking [708–710] and Discrete Wavelet Transform (DWT) based digital image/audio watermarking [555,711,712]. Image enhancement is used “to improve interpretability or perception of info available within the images, making it suitable for human vision, as well as to provide improved input to the other automated image processing techniques” [713]. FPGAs’ implementations for this technique include histogram equalization [714–717], retinex image enhancement [718–720], Infrared Focal Plane Arrays (IRFPA) image enhancement [721,722] and telescopes’ atmospheric turbulence mitigation [723,724]. Other image processing applications that use FPGAs are image segmentation [725–729], object tracking [730–734], object detection [735–739] (real time object detection [740–742], moving objects detection [743–745], pedestrian detection [746–749] and background identification [750–752]), optical flow [753–757] and Hough transform [758–762]. 9.1. Compression Standards Images and videos need substantial storage space. A single uncompressed 12 megapixels image with 24-bit color depth requires 36 MB to be stored in PPM format (portable pixmap file format). A full HD video with 24-bit color depth and 60 fps requires 356 MB/s ((24/8) × 1920 × 1080 × 60 = 355.957 MB/s) or 1.22 TB/h. If that were the case, a 3 Gbps Internet connection speed would be required to watch online full HD videos. For this reason, image and video codecs store the information with compression standards that reduce the required storage size significantly. FPGAs’ implementations of these compression standards allow real-time coding of complex algorithms. To the present day H.264 is the most popular standard for video codding related to FPGAs’ implementations (see Figure 13). The research of FPGAs’ implementations for this codec started in 2003 [763] and some implementations are related to motion estimation [764–768], intra-prediction [767,769–772], quantization [773,774] and DCT (Discrete Cosine Transform) [775,776]. Computation 2019, xx, 5 16 of 115 H.264 20.0 Average documents per year, 2016 - 2018 (doc./year) 100 H.265 JPEG2000 17.5 Accumulative Number of Documents JPEG MPEG-4 MPEG-2 15.0 12.5 10 10.0 7.5 5.0 1 2.5 0 0.0 1992 1995 1998 2001 2004 2007 2010 2013 2016 2019 0% 20% 40% 60% Publication year Percentage of documents published in the last years 2016 - 2018 Figure 13. Image and video compressing codecs top implementations in FPGA research. High-Efficiency Video Coding (HEVC) or H.265 is considered the successor of the H.264 video codec for higher resolution video applications [777,778]. This new codec is doubling the compression ration of its predecessor [779–781]. FPGA implementations and tests of this codec started in 2012 and today has the highest ADY and PDLY (50% of the documents published in the last three years, see Figure 13). One of the most critical challenges for H.265 is the efficient implementation of CABAC (Context-based Adaptive Binary Arithmetic Coding) that the research community considered as a well-known throughput bottleneck due to its strong data dependencies [782–784]. MPEG-2 (Moving Picture Experts Group) implementations in FPGAs started in 1996 [785] and MPEG-4 in 2003 [786]. The MPEG-2’s ADY is close to zero, which indicates that there have been almost no publications in this topic from 2016. Similarly, MPEG-4 has a low ADY of 0.3 documents/year, with research documents focused on the AAC (Advanced Audio Coding) implementation [787–789]. On the other hand, image compressing standards implementation in FPGAs started with JPEG (Joint Photographic Experts Group) in 1996 [790]. JPEG2000 implementations started in 2003 [791–793] and surpassed JPEG the same year. JPEG2000 standard uses a wavelet-based method to provide better rate-distortion performance than the original JPEG [794]. The embedded wavelet coding algorithm know as EBCOT (Embedded Block Coding with Optimized Truncation of bit-stream), used for JPEG2000 standard, has been widely implemented in FPGAs for parallel optimization [795–800]. 10. Big Data Dumbill defines big data as the “data that exceeds the processing capacity of conventional database systems” [801]. Big data systems are focused on analyzing efficiently this kind of data with not conventional systems, which are boosted by FPGA-based applications. Figure 14 shows the leading big data techniques evolution graph related to FPGAs’ research. Computation 2019, xx, 5 17 of 115 21 MapReduce Average documents per year, 2016 - 2018 (doc./year) Hadoop Spark 4 18 Apache Flink Accumulative Number of Documents Apache Mesos Phoenix MapReduce 15 3 12 2 9 6 1 3 0 0 1992 1995 1998 2001 2004 2007 2010 2013 2016 2019 0%25% 50% 75% 100% Publication year Percentage of documents published in the last years 2016 - 2018 Figure 14. Big data top implementations in FPGA research. MapReduce is a programming model for processing and generating large big data sets with a parallel or distributed algorithms [802]. FPGAs have been used to accelerate MapReduce algorithms by different frameworks such as FPMR (FPGA MapReduce) [803], MrHeter for heterogeneous data centers [804] and Melia based on OpenCL [805]. Other accelerators for MapReduce include scalable data center FPGA-based accelerators (HLSMapReduceFlow [806]), coarse-grained reconfigurable architecture acceleration [807], energy-efficient accelerators [808,809] and others [810,811]. Hadoop (also known as Apache Hadoop) is an open-source framework for distributed storage and distributed processing on huge data sets into computer clusters [812]. For Hadoop, FPGAs’ applications include energy-efficient acceleration of big data analytics [809], FPGA-accelerated Hadoop cluster for deep learning computations [813], process streaming data from SSDs (Solid State Drives) using FPGAs [814] and low-power Hadoop cluster [815]. Spark (also known as Apache Spark) is an open-source distributed general-purpose cluster computing system framework from Apache that supports in-memory computing, which enables it to process data faster compared to disk-based engines like Hadoop [816]. FPGAs’ applications related to Spark have the highest relative growth, with 100% of the publications in the last three years. For Spark, FPGAs have been used to accelerate the Spark process [31,32,817] and deep convolutional Neural Netw. for the Spark environment [818]. Other big data frameworks accelerated by FPGAs are Apache Flink in heterogeneous hardware [819], Apache Mesos for cluster management for the HetSpark framework [820] and Phoenix MapReduce in multi-core FPGA’s systems [821]. 11. Computer Algorithms FPGAs have a high capability to accelerate computer algorithms due to the parallel decomposition characteristics of some of them. This section shows the computer algorithms that are not enclosed in the previous sections. Figure 15 shows the top 10 algorithms implemented in FPGAs. CORDIC (for COordinate Rotation DIgital Computer) algorithm makes it possible to multiply and divide numbers by only shifting and adding steps. Also, it performs rotations to compute sine, cosine and arctangent functions [822]. The CORDIC algorithms implementations in FPGAs have been used for FFT processing [531,532,823], OFDM [824,825] and DCT transform [826,827]. Hardware floating point implementations in FPGAs are common for high performance FFT applications [828–831], floating point based Neural Netw. [832,833] and double precision floating point modules [834–837]. On the other hand, in Distributed Arithmetic (DA), multiplication is performed using precomputed lookup tables instead of the logic, reducing the cycles required to compute a final result [838]. FPGAs’ implementations of DA have been used for FIR filters [612,613,839–841], discrete cosine transform [842–845] and wavelet transform [560,846–848]. Another FPGAs’ computer algorithm Computation 2019, xx, 5 18 of 115 implemented in FPGAs is the Smith-Waterman algorithm [849–852] and its implementation for DNA sequence analysis [853,854]. CORDIC 25 Average documents per year, 2016 - 2018 (doc./year) Floating Point Distributed arithmetic 100 Smith-Waterman algorithm Accumulative Number of Documents String matching 20 Fixed-point arithmetic Vedic mathematics Trigger algorithms Montgomery algorithm 15 10 10 5 1 0 0 1992 1995 1998 2001 2004 2007 2010 2013 2016 2019 0% 20% 40% 60% Publication year Percentage of documents published in the last years 2016 - 2018 Figure 15. Top algorithms implementations in FPGA research. String matching algorithms tries to find the position where patterns are found within a larger string or text [855]. For FPGAs we found string matching implementations for network intrussion detection [856–858], deep packet inspection [859] and string matching algorithms based in bloom filter [860,861]. Fixed-point arithmetic algorithms have been used in FPGA for accuracy-guaranteed bit-width optimization [862,863], Jacobi SVD (Singular Value Decomposition) [864], Lanczos tridiagonalization [865,866] and deep belief networks [867,868]. Vedic mathematics is a system based on 16 sutras or aphorisms used for mathematical mental calculation operations [869]. Vedic mathematics algorithms have been implemented in FPGAs for faster [870–873] and energy efficient [874–876] multiplication operations. Other algorithms implemented in FPGAs are the trigger algorithms [877–880], trigger algorithms for the ATLAS experiment [881–884] and Montgomery algorithm for cryptography applications [885–888]. 12. Other Implementations Figure 16 shows other top implementation techniques in FPGAs’ research. Pulse Width Modulation (PWM) technique is one of the most used strategies for controlling the AC output of power electronic converter by varying the duty cycle of a converter switches [889]. FPGAs’ implementations for PWM includes application for inverters [890–893], digital control for power converters [21,894–897] and total harmonic distortion reduction [898–901]. A Finite-State Machine (FSM) is a representation of an abstract machine that can be or can change into a state that represents a possible situation. This change from one to another state is called transition and occurs in response to an external input [902]. Implementations of FSMs in FPGAs include low power FSMs [903,904] and engineering education [905,906]. Computation 2019, xx, 5 19 of 115 PWM 31% Finite state machine 23% Scheduling 24% Cellular Automata 29% PLL 27% Ring oscillator 52% SVPWM 28% LFSR 30% FIFO 17% RNS 31% DMA 29% SIMD 17% Systolic arrays 12% Before 2016 Bloom Filter 30% Between 2016 - 2018 0 50 100 150 200 250 300 Total number of documents, with percentage of documents published in the last years 2016 - 2018 Figure 16. Other top implementations techniques in FPGA research. In computing, “scheduling is the method by which work is assigned to resources that complete the work” [907]. Scheduling in FPGAs has been used for reconfigurable computing [908–910], real-time applications [911–913] and heterogeneous embedded systems [909,914,915]. According to Wolfarm, cellular automata consist of many identical simple components, that together are capable of complex behavior [916]. Alongside FPGAs, cellular automata has been used for cryptography [917–923], random number generation [924–927], systems modeling [928–937] and simulation [938–940]. Phase-Locked Loop (PLL) “synchronizes the frequency of the output signal generated by an oscillator with the frequency of a reference signal by means of the phase difference of the two signals” [941]. In FPGAs the PLLs have been used for motor speed control [942–944], demodulator synchronization [945–947] and jitter detection [607,948–952]. Ring oscillator in this list has the highest PDLY, with 52% of the documents published in the last three years. A ring oscillator is a cascaded combination of delay stages, connected in a close loop chain to generate an oscillating output [953]. FPGAs’ implementations of ring oscillators include physical unclonable functions [339,342,954–957], time to digital converters [958–962] and random number generators [609,963–972]. Other implementations techniques in FPGAs covered in this top are SVPWM (Space Vector Pulse Width Modulation) [973–979], LFSR (Linear-Feedback Shift Register) [980–985], FIFO (First-In First-Out) [986–994], RNS (Residue Number System) [995–1001], DMA (Direct Memory Access) [1002–1005], SIMD (Single Instruction Multiple Data Stream) [1006–1009], systolic arrays [1010–1014] and bloom filter [860,1015–1020]. 13. Other Applications In this section, we present other FPGAs’ applications not covered previously. Figure 17 shows the top other applications. Computation 2019, xx, 5 20 of 115 Simulation 26% Low power 23% WSN 19% Robotics 24% Optimization 27% Modeling 25% Data compression 26% Internet of Things 85% Hardware-In-the-Loop 44% Inverter 24% GPS 16% Positron emission tomography 18% Bioinformatics 24% Fuzzy logic 20% Radar 32% Electrocardiography 35% Adaptive optics 22% UAV 32% MEMS 23% Simulated annealing 19% Ultrasound 14% Virtualization 35% UWB 6% Stepper motor 22% Before 2016 Between 2016 - 2018 0 100 200 300 400 Total number of documents, with percentage of documents published in the last years 2016 - 2018 Figure 17. Other top applications in FPGA research. Simulation is the top of this list and it refers to an approximate imitation of the operation of a process or system [1021]. In this area, we found FPGAs’ usage for the simulation of different systems, such as the described following: • Power Electronics [1022–1056] • Multiprocessors/multicore architectures [19,1057–1061] • Neural biological systems [1062–1065] • Single even upsets (SEU) [1058,1066–1069] • Photovoltaic systems [477,1070–1078] • Read-out detectors [1079–1081] • Electrical machines [1082–1089] • Distribution grids [1090–1095] • Vehicles [1096–1101] • BPSK and QPSK modulators [1102,1103] • Microprocessors cache [1104,1105] • Fuel cells [1106,1107] • Synthetic Aperture Radar (SAR) echo simulation [1108,1109] • Wind farms, turbines [1110,1111] • RFID tags [1112,1113] • Biochemical reaction [1114] • MEMS (Microelectromechanical Systems) [1115] • Nanoscale devices [1116] • Quantum computers [1117] • HPC (High-Performance Computing) power consumption [1118] Low power applications are the second in this other applications list, which include low power applications for image processing [1119–1124], H.264 encoding [769,771,1125–1129], finite state machine [904,1130], memory design [1131–1133] and AES encryption [1134–1137]. The WSN Computation 2019, xx, 5 21 of 115 (Wireless Sensor Networks) comprises wireless Sensors that have a sensing comportment, on-board processing, communication and storage capabilities to cooperatively monitor a large physical environments [1138]. FPGAs have been used in WSN for elliptic curve cryptography implementations in sensor nodes [1139–1144], energy efficient sensor nodes [1145–1147], ZigBee MAC layer functions realization [268,1148] and ZigBee physical layer blocks simulation [1149]. Next, robotics applications (including mobile robots) in FPGAs involves: • Localization [1150–1156] • Trajectory/path planing [498,1157–1163] • Visual servoing [483,1164–1169] • Navigation [11,1153,1170–1173] • Stereo vision [1173–1177] • Object/person follower/tracking [1168,1178–1180] • Ultrasonic Sensors [1181–1185] • Robot Operating System (ROS) [1153,1186–1189] • Educational [1190–1192] • Motion control [1193–1195] • Vector rotation [1183,1196,1197] • Obstacle avoidance [1198–1200] • Arm robot joints control [1201,1202] • Mapping [1203] • Collaborative robotics [1204] • Spatial cognition [1205] • Velocity estimation [1206] Optimization applications in FPGAs enclose power optimization [1207–1209], CRC (Cyclic Redundancy Check) look-up table [1210], pipelines [1211,1212], Particle Swarm Optimization (PSO) [1213–1215], SM3 hash algorithm [1216], FIFO stack [1217], matrix multiplication [1218], torque ripple [1219], memory usage [1220], banking model [1221] and thermoelectric coolers [1222]. Modeling is the use of mathematical models as an idealization of a real-world phenomenon, for predicting the value of a variable at some time in the future [1223]. Similarly to simulation, FPGAs have been used in several modeling applications: • Control systems [1224–1228] • Power Electronics [1028,1086,1229–1232] • Network on chip [1233,1234] • Thermomechanical systems [1235,1236] • Employees behavior and interactions in workplace [928] • Computer networks [1237,1238] • Arousal content [1239] • FIFO stack [1217] • HPC power consumption [1118] • Meteorological systems [1240] • UAV (Unmanned Aerial Vehicle), vehicles and mobile robots [1241,1242] • Renewable energy systems [1225,1243,1244] • RF (Radio Frequency) power amplifier [1245] • Urban traffic [937] Data compression is a reduction in the number of bits needed to represent the data [1246]. In FPGAs data compression has been implemented in the LZ77 algorithm [1247–1250], Huffman coding [1251–1253], LZW (Lempel–Ziv–Welch) algorithm [1248,1254–1257] and hardware accelerator compressing techniques [1247,1249,1258–1261]. Internet of Things (IoT) connects billions of devices to the Internet, devices that combine sensing, computation and communication techniques to deliver remote data collection and system control [1262]. IoT in this list is the application with the highest Computation 2019, xx, 5 22 of 115 PDLY, with 85% of the documents published in the last three years. For IoT applications, FPGAs have been used in improving devices security [1263–1265], data encryption [460,1144,1266–1268], edge computing [1269–1271], FPGA-based gateways [1272,1273] and fog computing platforms [1274,1275]. Finally other FPGAs applications in this list includes Hardware-In-the-Loop (HIL) [34,1115,1276– 1282], GPS (Global Positioning System) [1283–1298], Positron Emission Tomography (PET) [1299–1324], bioinformatics [1325–1342], fuzzy logic [1343–1353], radar [658,1354–1363], Electrocardiography [1364–1381], adaptive optics [1382–1394], Unmanned aerial vehicles [496,1395–1402], MEMS [174,1403–1411], simulated annealing [1412–1420], ultrasound [1421–1432], virtualization [1433–1438], UWB (Ultra-wideband) [1156, 1439–1444] and stepper motor applications [1445–1462]. 14. Applications Mapping In this section, we describe the co-occurrence mapping for the different FPGAs’ applications. For this purpose, we used the pre-processed output dataset generated by ScientoPy (which includes the merged datasets from WoS and Scopus in the Scopus data format) as an input to generate a network map in VOSviewer [1463]. In VOSviewer, we created an author keywords co-occurrence map, with a thesaurus file that merges the different variants of the applications names and filters the first 100 author’s keywords that are not related to FPGA-based applications or implementations. Finally, we selected the first merged 35 author’s keywords based on the total link strength values to generate the network map (see Figure 18). In this figure, we find five clusters described as follows. The yellow cluster indicates applications related to signal processing. The purple cluster is related to the applications that are related to low power implementations. Then, the green cluster contains applications related to security implementations. Next, the blue cluster shows high-performance and high-reliability systems. Finally, the red cluster points out real-time applications. For the signal processing cluster (yellow color) we find relations that indicates for intance that MIMO is supported by OFDM [146,148,1464–1466] and OFDM is supported by FFT implementations [538,540,1467,1468]. The FFT implementations are supported by CORDIC [531–534] and also are designed as low power implementations [532,1469]. For the security cluster (green color), we found that AES has an strong relationship with security, encryption, cryptography and also with low power implementations [470,1134]. Similarly, we found that FPGAs’ implementations have helped to add security to WSN nodes [1139–1141] and low power processing capabilities [1470–1472]. In the red cluster, we find FPGAs’ applications focused in real-time implementations, such as data acquisition [565,1473–1475], simulations [1022,1024,1082,1476], Neural Netw. [1477–1479] and image processing [1480–1487]. Finally, the blue cluster shows that the fault tolerance and high reliability systems are based in fault injection impelmentations [1488,1489] and single event upset tolerance mechanisms [1490–1492]. In addition, other relevant relations are shown in colored lines, like digital control with PWM [1493,1494], simulation with modeling [1057,1118,1495] and performance with algorithms [1496–1498]. Computation 2019, xx, 5 23 of 115 fault injection single event upset reliability simulation algorithms modeling fault tolerance digital control robotics performance genetic algorithm image processing pwm real-time security adc dwt neural network data acquisition machine learning encryption fir aes fsm sdr wsn fft low power mimo floating point ecc cryptography h.264 ofdm cordic Figure 18. Co-occurrence network mapping of author keywords related to FPGAs’ applications. Colors represent groups of applications that are relatively strongly linked to each other. The size of the node signifies the number of documents related and the width of the lines represent the strength of the relationship between two nodes. 15. Discussion FPGAs have a wide range of applications, from real-time data processing to neural network implementations. In this review we divided these applications into eleven categories and in each category we presented the applications with most documents related to them, totaling 150 applications described in this review. For digital control we found that the most important control techniques are implemented in FPGAs, like fuzzy control [1499–1502], PID [69,1503,1504], model predictive control [73,76,1505], adaptive control [80,81,1506], sensorless control [1507–1509] and distributed control [96,99,101]. These digital control techniques were implemented in FPGAs due the high speed response that a hardware digital control FPGA-based implementation can achieve and its reconfiguration capability, allowing control application to high speed system such as induction motors [1507,1510–1512], torque control [75,1513,1514], Brushless DC (Direct Current) motors [1515–1517], current control [1518,1519], among others [65,1520–1523]. The communications interfaces implemented for or with FPGAs have developed at the same rate that these interfaces have grown for other technologies, like computer or mobile interfaces. The implementations of these communication interfaces in FPGAs aims to high speed/real-time data capturing systems [565,1524–1531], security network processors [144,145], image capturing [108,113,1532–1534] and latest generation memory controller (DDR4 [133,134], HBM [135]). For networking, we found in this study that the FPGAs were used for the initial prototype and implementations of the new generation network standard like LTE [245,247,1535] and recently 5G [295,301,1536,1537]. Also, the FPGAs have been used for high-performance packet classification [257,258,1538–1540], Software Defined Radio (SDR) [186,1541,1542] and Network (SDN) [288,1543,1544], cognitive radio [224,225,238], Computation 2019, xx, 5 24 of 115 Network on Chip (NoC) [1545–1547] and other network standards such as ZigBee [1548–1550] and WiMAX [279,1551,1552]. Computer security was one of the largest topic covered in this paper. FPGAs help to ensure the security of different systems with fault tolerance mechanism [14,1553,1554], single event upset recovery/ mitigation [1555,1556] and emulation [321,1488], side channel attacks protection [330–332,1557,1558] and detection [1559–1561], physical unclonable function implementations [339,1562,1563], triple modular redundancy [1564–1566] and intrusion detection [399,1567,1568]. The applications and systems protected by these security techniques in FPGAs includes military [326,1569], space [308,1492,1570,1571] and medical [314,1572,1573] systems. Similarly, FPGAs have had an important role in the diverse cryptography techniques implementations. Different techniques like AES, ECC, RSA, SHA and others have been implemented in FPGAs for high throughput encoding/decoding [407,1574–1576], reconfigurable cryptographic processors [1577–1579] and low power consumption implementations [470,472,1580,1581]. Machine learning techniques implementations in FPGAs include in this paper Neural Netw., genetic algorithms, support vector machine, spiking neural network and AdaBoost. These have been implemented for image processing [527,1582,1583], pattern recognition [476,1584], real-time processing [671,1477,1585], melanoma cancer detection [510,511,1586,1587], speech recognition [1587,1588] and so forth. Digital signal processing techniques implementations in FPGAs covers FFT [537,1589–1593], DWT [597,1594–1597], time-to-digital converters [1598–1602], DCT [580,1603–1605] and digital filters like FIR filter [56,612,1606–1608], Kalman filter [620,1609–1611], median filter [1612,1613], LMS [1614–1616] and others. For image and video processing, FPGAs have boosted different applications allowing real-time processing for stereo vision systems [661,667,1617–1619], face detection/recognition [675,677,679], object tracking [732,1620,1621] and digital watermarking for intellectual property protection [706,1622,1623]. These kind of applications have been used for different systems such as the Mars rovers computer vision [669,670], autonomous vehicles vision [1624–1629], atmospheric turbulence mitigation for telescope pictures reconstruction [723,724], among others. In addition, we found image and video compression standards implemented in FPGAs, from JPEG [1630], to most recent video compression standard H.265 [593]. The implementation in FPGAs of the different blocks that integrate the compression standards or codecs (intra prediction [1631–1633], Context-adaptive binary arithmetic coding (CABAC) [783,1634], DCT [775,1635], Context-adaptive variable-length coding (CAVLC) [1636–1638], etc.) allowed real-time [1639–1641] and low power [1125,1127,1129,1642] encoding. Similarly, big data processes have been accelerated with FPGAs [29], using Apache Hadoop [813,1643] and Apache Spark [31,32,1644]. Other computer algorithms implemented in FPGAs described in this review includes CORDIC [1645–1647], floating point [831,1648,1649], distributed arithmetic [1650,1651] and so on. Similarly, other implementations techniques for FPGAs found here were PWM [890,1652,1653], finite state machines [1654–1656], scheduling [1657–1660], cellular automata [924,932], PLLs [950,1661,1662], ring oscillators [339,962,1663], and so forth. Finally, we summarized other FPGAs’ applications which include simulation [1028,1040,1048,1057], low power consumption [16,1664,1665], WSNs [42,1666,1667], robotics [1150,1173,1668,1669], optimization [1208,1209,1670], modeling [937,1028,1671], Internet of things [1265,1266,1672], data compression [1673–1675], among others. As noted above, FPGAs cover a vast range of applications in modern computing systems. These results summarize the top applications based on FPGAs, including evolution, trendings and co-relations. In this way, new evolving applications are shown here the trends of future technologies such as cryptographic standards (SHA-3), video compression algorithms (H.265) and even new generation networks like 5G. Similarly, another type of applications could inspire the developers in different and more efficient ways to solve actual problems, such as cancer detection systems, indoor location using the time of arrival or more efficient big data processing techniques. This paper shows extensive background information on FPGA-based applications to researchers, graduate students, stakeholders, industry, journals and funding agencies. The overview of the Computation 2019, xx, 5 25 of 115 FPGA-based accelerated applications mentioned here allows the researchers and industry to improve the efficiency of actually implemented systems. Also, the accelerated algorithms and techniques implementations allow the adoption of FPGAs for the acceleration of new kinds of applications. Finally, this work was limited to scientific publications in the two central databases (Scopus and WoS). Future research could examine these applications related to commercial and industrial ones, analyzing and comparing these applications trends with other sources like Google Analytics and others. Author Contributions: J.R.-R., G.R.-G., and R.K. proposed the concept of this research. R.K. contributed to the design of the different sections. J.R.-R. and G.R.-G. designed the scientometric analysis. J.R.-R. wrote the paper. Funding: This work was funded by the Departamento Administrativo de Ciencia, Tecnología e Innovación (647-2014), and by the Universidad del Cauca (501100005682). Conflicts of Interest: The authors declare no conflict of interest. References 1. Trimberger, S. Field-Programmable Gate Array Technology; Springer US: New York, NY, USA, 2012. 2. Hamouda, M.; Blanchette, H.F.; Al-Haddad, K.; Fnaiech, F. An Efficient DSP-FPGA-Based Real-Time Implementation Method of SVM Algorithms for an Indirect Matrix Converter. IEEE Trans. Ind. Electron. 2011, 58, 5024–5031. doi:10.1109/TIE.2011.2159952. 3. Pozniak, K.; Czarski, T.; Romaniuk, R. Functional analysis of DSP blocks in FPGA chips for application in TESLA LLRF system. In Proceedings of the 12th IEEE-SPIE Symposium on Photonics and Web Engineering, Warsaw Univ Technol Resort, Wilga, Poland, 21–25 May 2003. 4. Huang, J.B.; Xie, Z.W.; Liu, H.; Sun, K.; Liu, Y.C.; Jiang, Z.N. DSP/FPGA-based controller architecture for flexible joint robot with enhanced impedance performance. J. Intell. Robot. Syst. 2008, 53, 247–261. doi:10.1007/s10846-008-9240-7. 5. Diaz, J.; Ros, E.; Pelayo, F.; Ortigosa, E.; Mota, S. FPGA-based real-time optical-flow system. IEEE Trans. Circuits Syst. Video Technol. 2006, 16, 274–279. doi:10.1109/TCSVT.2005.861947. 6. Kalomiros, J.A.; Lygouras, J. Design and evaluation of a hardware/software FPGA-based system for fast image processing. Microprocess. Microsyst. 2008, 32, 95–106. doi:10.1016/j.micpro.2007.09.001. 7. Hegarty, J.; Brunhaver, J.; DeVito, Z.; Ragan-Kelley, J.; Cohen, N.; Bell, S.; Vasilyev, A.; Horowitz, M.; Hanrahan, P. Darkroom: Compiling High-Level Image Processing Code into Hardware Pipelines. ACM TRansactions Graph. 2014, 33. doi:10.1145/2601097.2601174. 8. Rajagopalan, S.; Amirtharajan, R.; Upadhyay, H.; Rayappan, J. Survey and analysis of hardware cryptographic and steganographic systems on FPGA. J. Appl. Sci. 2012, 12, 201–210. doi:10.3923/jas.2012.201.210. 9. Kean, T. Cryptographic rights management of FPGA intellectual property cores. In Proceedings of the FPGA 2002: Tenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, 24–26 February 2002. 10. Chen, D.D.; Mentes, N.; Vercauteren, F.; Roy, S.S.; Cheung, R.C.C.; Pao, D.; Verbauwhede, I. High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems. IEEE Trans. Circuits Syst. -Regul. Pap. 2015, 62, 157–166. doi:10.1109/TCSI.2014.2350431. 11. Tsai, C.C.; Huang, H.C.; Chan, C.K. Parallel Elite Genetic Algorithm and Its Application to Global Path Planning for Autonomous Robot Navigation. IEEE Trans. Ind. Electron. 2011, 58, 4813–4821. doi:10.1109/TIE.2011.2109332. 12. Jarvinen, K.; Skytta, J. On parallelization of high-speed processors for elliptic curve cryptography. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2008, 16, 1162–1175. doi:10.1109/TVLSI.2008.2000728. 13. Keymeulen, D.; Zebulum, R.; Jin, Y.; Stoica, A. Fault-tolerant evolvable hardware using field-programmable transistor arrays. IEEE Trans. Reliab. 2000, 49, 305–316. doi:10.1109/24.914547. 14. Cheatham, J.A.; Emmert, J.M.; Baumgart, S. A survey of fault tolerant methodologies for FPGAs. ACM Trans. Des. Autom. Electron. Syst. 2006, 11, 501–533. doi:10.1145/1142155.1142167. 15. Emmert, J.M.; Stroud, C.E.; Abramovici, M. Online fault tolerance for FPGA logic blocks. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2007, 15, 216–226. doi:10.1109/TVLSI.2007.891102. Computation 2019, xx, 5 26 of 115 16. Li, F.; Lin, Y.; He, L.; Cong, J. Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. In Proceedings of the ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004, Monterey, CA, USA, 22–24 February 2004. 17. Zhou, Y.; Thekkel, S.; Bhunia, S. Low Power FPGA Design Using Hybrid CMOS-NEMS Approach. In Proceedings of the 12th International Symposium on Low Power Electronics and Design, Portland, OR, USA, 27–29 August 2007. 18. Lee, D.; Luk, W.; Villasenor, J.; Cheung, P. A Gaussian noise generator for hardware-based simulations. IEEE Trans. Comput. 2004, 53, 1523–1534. doi:10.1109/TC.2004.106. 19. Tan, Z.; Waterman, A.; Avizienis, R.; Lee, Y.; Cook, H.; Patterson, D.; Asanovic, K. RAMP Gold: An FPGA-based Architecture Simulator for Multiprocessors. In Proceedings of the 47th Design Automation Conference (DAC), Anaheim, CA, USA, 13–18 June 2010. 20. Hasanzadeh, A.; Edrington, C.S.; Stroupe, N.; Bevis, T. Real-Time Emulation of a High-Speed Microturbine Permanent-Magnet Synchronous Generator Using Multiplatform Hardware-in-the-Loop Realization. IEEE Trans. Ind. Electron. 2014, 61, 3109–3118. doi:10.1109/TIE.2013.2279128. 21. Buccella, C.; Cecati, C.; Latafat, H. Digital Control of Power Converters-A Survey. IEEE Trans. Ind. Inform. 2012, 8, 437–447. doi:10.1109/TII.2012.2192280. 22. de Castro, A.; Zumel, P.; Garcia, O.; Riesgo, T.; Uceda, J. Concurrent and simple digital controller of an AC/DC converter with power factor correction based on an FPGA. IEEE Trans. Power Electron. 2003, 18, 334–343. doi:10.1109/TPEL.2002.807106. 23. Shu, Z.; Guo, Y.; Lian, J. Steady-state and dynamic study of active power filter with efficient FPGA-based control algorithm. IEEE Trans. Ind. Electron. 2008, 55, 1527–1536. doi:10.1109/TIE.2008.917151. 24. Mellit, A.; Kalogirou, S.A. Artificial intelligence techniques for photovoltaic applications: A review. Prog. Energy Combust. Sci. 2008, 34, 574–632. doi:10.1016/j.pecs.2008.01.001. 25. Punitha, K.; Devaraj, D.; Sakthivel, S. Artificial neural network based modified incremental conductance algorithm for maximum power point tracking in photovoltaic system under partial shading conditions. Energy 2013, 62, 330–340. doi:10.1016/j.energy.2013.08.022. 26. Juang, C.; Chen, J. Water bath temperature control by a recurrent fuzzy controller and its FPGA implementation. IEEE Trans. Ind. Electron. 2006, 53, 941–949. doi:10.1109/TIE.2006.874260. 27. Uchida, T. Hardware-based TCP processor for Gigabit Ethernet. In Proceedings of the IEEE Nuclear Science Symposium/Medical Imaging Conference, Honolulu, HI, USA, 26 October–3 November 2007. 28. Bomel, P.; Crenne, J.; Ye, L.; Diguet, J.P.; Gogniat, G. Ultra-Fast Downloading of Partial Bitstreams through Ethernet. In Proceedings of the 22nd International Conference on Architecture of Computing Systems, Delft Univ Technol, Delft, The Netherlands, March 10–13, 2009. 29. Wang, C.; Li, X.; Zhou, X. SODA: Software Defined FPGA based Accelerators for Big Data. In Proceedings of 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 9–13 March 2015. 30. Rouhani, B.D.; Songhori, E.M.; Mirhoseini, A.; Koushanfar, F. SSketch: An Automated Framework for Streaming Sketch-based Analysis of Big Data on FPGA. In Proceedings of the 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Vancouver, BC, Canada, 3–5 May 2015. 31. Ghasemi, E.; Chow, P. Accelerating Apache Spark with FPGAs. Concurr.-Comput.-Pract. Exp. 2019, 31. doi:10.1002/cpe.4222. 32. Ghasemi, E.; Chow, P. Accelerating Apache Spark Big Data Analysis with FPGAs. In Proceedings of the 2016 Intl IEEE Conferences on Ubiquitous Intelligence & Computing, Advanced and Trusted Computing, Scalable Computing and Communications, Cloud and Big Data Computing, Internet of People, and Smart World Congress (UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld), Toulouse, France, 18–21 July 2016. 33. Monmasson, E.; Cirstea, M.N. FPGA design methodology for industrial control systems - A review. IEEE Trans. Ind. Electron. 2007, 54, 1824–1842. doi:10.1109/TIE.2007.898281. 34. Rodriguez-Andina, J.J.; Valdes-Pena, M.D.; Moure, M.J. Advanced Features and Industrial Applications of FPGAs-A Review. IEEE Trans. Ind. Inform. 2015, 11, 853–864. doi:10.1109/TII.2015.2431223. 35. Ahmed, S.; Sassatelli, G.; Torres, L.; Rouge, L. Survey of new trends in industry for programmable hardware: FPGAs, MPPAs, MPSoCs, structured ASICs, eFPGAs and new wave of innovation in FPGAs. In Proceedings Computation 2019, xx, 5 27 of 115 of the 20th International Conference on Field Programmable Logic and Applications, Milano, Italy, 31 August–2 September 2010. doi:10.1109/FPL.2010.66. 36. Naouar, M.W.; Monmasson, E.; Naassani, A.A.; Slama-Belkhodja, I.; Patin, N. FPGA-based current controllers for AC machine drives - A review. IEEE Trans. Ind. Electron. 2007, 54, 1907–1925. doi:10.1109/TIE.2007.898302. 37. Doumar, A.; Ito, H. Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: A survey. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2003, 11, 386–405. doi:10.1109/TVLSI.2002.801609. 38. Harikrishna, B.; Ravi, S. A Survey on Fault Tolerance in FPGAs. In Proceedings of the 7th International Conference on Intelligent Systems and Control (ISCO), Coimbatore, India, 4–5 January 2013. 39. Nidhin, T.S.; Bhattacharyya, A.; Behera, R.P.; Jayanthi, T. A Review on SEU Mitigation Techniques for FPGA Configuration Memory. IETE Tech. Rev. 2018, 35, 157–168. doi:10.1080/02564602.2016.1265905. 40. Papadimitriou, K.; Dollas, A.; Hauck, S. Performance of Partial Reconfiguration in FPGA Systems: A Survey and a Cost Model. ACM Trans. Reconfigurable Technol. Syst. 2011, 4. doi:10.1145/2068716.2068722. 41. Mellit, A.; Kalogirou, S.A. MPPT-based artificial intelligence techniques for photovoltaic systems and its implementation into field programmable gate array chips: Review of current status and future perspectives. Energy 2014, 70, 1–21. doi:10.1016/j.energy.2014.03.102. 42. de la Piedra, A.; Braeken, A.; Touhafi, A. Sensor Systems Based on FPGAs and Their Applications: A Survey. Sensors 2012, 12, 12235–12264. doi:10.3390/s120912235. 43. Garcia, G.J.; Jara, C.A.; Pomares, J.; Alabdo, A.; Poggi, L.M.; Torres, F. A Survey on FPGA-Based Sensor Systems: Towards Intelligent and Reconfigurable Low-Power Sensors for Computer Vision, Control and Signal Processing. Sensors 2014, 14, 6247–6278. doi:10.3390/s140406247. 44. Chen, H.; Chen, Y.; Summerville, D.H. A Survey on the Application of FPGAs for Network Infrastructure Security. IEEE Commun. Surv. Tutor. 2011, 13, 541–561. doi:10.1109/SURV.2011.072210.00075. 45. Hailes, P.; Xu, L.; Maunder, R.G.; Al-Hashimi, B.M.; Hanzo, L. A Survey of FPGA-Based LDPC Decoders. IEEE Commun. Surv. Tutor. 2016, 18, 1098–1122. doi:10.1109/COMST.2015.2510381. 46. Andraka, R. Survey of CORDIC algorithms for FPGA based computers. ACM, New York, NY, United States, 1998, pp. 191–200. In Proceedings of the Proceedings of the 1998 ACM/SIGDA 6th International Symposium on Field Programmable Gate Arrays, FPGA, Monterey, CA, USA, 22–24 February 1998. 47. Singh, A.; Prasad, A.; Talwar, Y. SCADA Security Issues and FPGA implementation of AES - A Review. In Proceedings of the 2nd IEEE International Conference on Next Generation Computing Technologies (NGCT), UnivPetr & Energy Studies, Dehradun, India, 14–16 October 2016. 48. Venieris, S.I.; Kouris, A.; Bouganis, C.S. Toolflows for Mapping Convolutional Neural Netw. on FPGAs: A Survey and Future Directions. ACM Comput. Surv. 2018, 51. doi:10.1145/3186332. 49. Mittal, S. A survey of FPGA-based accelerators for convolutional neural networks. Neural Comput. Appl. 2018. doi:10.1007/s00521-018-3761-1. 50. Blaiech, A.G.; Khalifa, K.B.; Valderrama, C.; Fernandes, M.A.; Bedoui, M.H. A Survey and Taxonomy of FPGA-based Deep Learning Accelerators. J. Syst. Archit. 2019. doi:https://doi.org/10.1016/j.sysarc.2019.01.007. 51. Shawahna, A.; Sait, S.M.; El-Maleh, A. FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review. IEEE Access 2019, 7, 7823–7859. doi:10.1109/ACCESS.2018.2890150. 52. Popescu, S.; Budura, G.; Gontean, A. Review of PSK and QAM - digital modulation techniques on FPGA. In Proceedings of the 2010 International Joint Conferences on Computational Cybernetics and Technical Informatics, Timisoara, Romania, 27–29 May 2010. doi:10.1109/ICCCYB.2010.5491254. 53. Sun, F.; Wang, H.; Fu, F.; Li, X. Survey of FPGA low power design. In Proceedings of the 2010 International Conference on Intelligent Control and Information Processing, Dalian, China, 13–15 August 2010. doi:10.1109/ICICIP.2010.5565246. 54. Alkhafaji, F.; Hasan, W.; Isa, M.; Sulaiman, N. Robotic controller: ASIC versus FPGA - A review. J. Comput. Theor. Nanosci. 2018, 15, 1–25. doi:10.1166/jctn.2018.7119. 55. Muralidar, D.; Silambarasan, R. A review about different automotive safety system using FPGA. J. Chem. Pharm. Sci. 2016, 9, 3353–3355. Computation 2019, xx, 5 28 of 115 56. Jyoti.; Kumar, A.; Sangwan, A. Designing of FIR filter using FPGA: A review. In Proceedings of the 3rd International Conference on Nanoelectronics, Circuits and Communication Systems, NCCS 2017, 11–12 November 2017. doi:10.1007/978-981-13-0776-8_46. 57. Amulya, K.; Sadashivappa, G. Design and Implementation of a Reconfigurable Digital Down Converter for 4G Systems Using MATLAB and FPGA- A Review. In Proceedings of the 2018 IEEE Conference on Emerging Devices and Smart Systems, ICEDSS 2018, Tamilnadu, India, 2–3 March 2018. doi:10.1109/ICEDSS.2018.8544271. 58. Bouhali, M.; Shamani, F.; Dahmane, Z.E.; Belaidi, A.; Nurmi, J. FPGA Applications in Unmanned Aerial Vehicles - A Review. In Proceedings of the 13th International Symposium on Applied Reconfigurable Computing (ARC), Delft, The The Netherlands, 3–7 April 2017. doi:10.1007/978-3-319-56258-2_19. 59. Sharma, B.L.; Khatri, N.; Sharma, A. An Analytical Review on FPGA Based Autonomous Flight Control System for Small UAVs. In Proceedings of the International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), Palnchur, India, 3–5 March 2016. 60. Bakiri, M.; Guyeux, C.; Couchot, J.F.; Oudjida, A.K. Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses. Comput. Sci. Rev. 2018, 27, 135–153. doi:10.1016/j.cosrev.2018.01.002. 61. Sadrozinski, H.F.W.; Wu, J. Applications of Field-Programmable Gate Arrays in Scientific Research, 1st ed.; Taylor & Francis, Inc.: Bristol, PA, USA, 2010. 62. Rao, S. Field Programmable Gate Array and Applications. Available online: https://patents.google.com/ patent/US5208491A/en (accessed on 8 November 2019). 63. Ruiz-Rosero, J.; Ramirez-Gonzalez, G.; Viveros-Delgado, J. Software survey: ScientoPy, a scientometric tool for topics trend analysis in scientific publications. Scientometrics 2019, 121, 1165–1188. 64. Bakshi, U.; Bakshi, V. Control Systems Engineering. Available online: https://www.researchgate.net/ publication/265168969_Control_Systems_Engineering (accessed on 8 November 2019). 65. Kung, Y.S.; Fung, R.F.; Tai, T.Y. Realization of a Motion Control IC for X-Y Table Based on Novel FPGA Technology. IEEE Trans. Ind. Electron. 2009, 56, 43–53. doi:10.1109/TIE.2008.2005667. 66. Del Campo, I.; Echanobe, J.; Basterretxea, K.; Bosque, G. Scalable architecture for high-speed multidimensional fuzzy inference systems. J. Circuits Syst. Comput. 2011, 20, 375–400. doi:10.1142/S0218126611007359. 67. Qin, W.; Zhou, J.; Li, C. Research of Continuous Variable Camshaft Timing system based on fuzzy-PID control method. In Proceedings of the 2011 2nd International Conference on Mechanic Automation and Control Engineering, Hohhot, China, 15–17 July 2011. 68. Hwu, K.I.; Yau, Y.T. Performance Enhancement of Boost Converter Based on PID Controller Plus Linear-to-Nonlinear Translator. IEEE Trans. Power Electron. 2010, 25, 1351–1361. doi:10.1109/TPEL.2009.2036727. 69. Chander, S.; Agarwal, P.; Gupta, I. FPGA-based PID controller for DC-DC converter. In Proceedings of the 2010 Joint International Conference on Power Electronics, Drives and Energy Systems & 2010 Power India, New Delhi, India, 20–23 December 2010. 70. Sivaramakrishna, M.; Upadhyay, C.; Nagaraj, C.; Madhusoodanan, K. Development of pid controller algorithm over FPGA for motor control in failed fuel location module in Indian fast reactors. In Proceedings of the 2011 3rd International Conference on Electronics Computer Technology, ICECT 2011, Kanyakumari, India, 8–10 April 2011. 71. Stambaugh, C. The control system for the magnetic suspension comparator system for vacuum-to-air mass dissemination. Acta IMEKO 2017, 6, 75–79. 72. Camacho, E.; Bordons, C.; Alba, C. Model Predictive Control; Advanced Textbooks in Control and Signal Processing; Springer: London, UK, 2004. 73. Ling, K.V.; Yue, S.P.; Maciejowski, J.M. A FPGA implementation of model predictive control. In Proceedings of the American Control Conference 2006, Minneapolis, MN, USA, 14–16 June 2006. 74. Hartley, E.N.; Jerez, J.L.; Suardi, A.; Maciejowski, J.M.; Kerrigan, E.C.; Constantinides, G.A. Predictive Control Using an FPGA With Application to Aircraft Control. IEEE Trans. Control. Syst. Technol. 2014, 22, 1006–1017. doi:10.1109/TCST.2013.2271791. Computation 2019, xx, 5 29 of 115 75. Morales-Caporal, R.; Pacas, M. Encoderless Predictive Direct Torque Control for Synchronous Reluctance Machines at Very Low and Zero Speed. IEEE Trans. Ind. Electron. 2008, 55, 4408–4416. doi:10.1109/TIE.2008.2007025. 76. Curkovic, M.; Jezernik, K.; Horvat, R. FPGA-Based Predictive Sliding Mode Controller of a Three-Phase Inverter. IEEE Trans. Ind. Electron. 2013, 60, 637–644. doi:10.1109/TIE.2012.2206360. 77. Ramirez, R.O.; Espinoza, J.R.; Melin, P.E.; Reyes, M.E.; Espinosa, E.E.; Silva, C.; Maurelia, E. Predictive Controller for a Three-Phase/Single-Phase Voltage Source Converter Cell. IEEE Trans. Ind. Inform. 2014, 10, 1878–1889. doi:10.1109/TII.2014.2332062. 78. Hartley, E.N.; Maciejowski, J.M. Field programmable gate array based predictive control system for spacecraft rendezvous in elliptical orbits. Optim. Control. Appl. Methods 2015, 36, 585–607. doi:10.1002/oca.2117. 79. Ioannou, P.A.; Sun, J. Robust Adaptive Control; Prentice-Hall, Inc.: Upper Saddle River, NJ, USA, 1995. 80. Huang, H.C.; Tsai, C.C. FPGA Implementation of an Embedded Robust Adaptive Controller for Autonomous Omnidirectional Mobile Platform. IEEE Trans. Ind. Electron. 2009, 56, 1604–1616. doi:10.1109/TIE.2008.2009524. 81. Huang, H.C.; Tsai, C.C.; Lin, S.C. Adaptive Polar-Space Motion Control for Embedded Omnidirectional Mobile Robots with Parameter Variations and Uncertainties. J. Intell. Robot. Syst. 2011, 62, 81–102. doi:10.1007/s10846-010-9438-3. 82. Wu, T.F.; Huang, H.C.; Tsai, P.S.; Hu, N.T.; Yang, Z.Q. Adaptive Fuzzy CMAC Design for an Omni-Directional Mobile Robot. In Proceedings of the 10th International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP), Waseda Univ, Kitakyushu, Japan, 27–29 August 2014. 83. Suzuki, S.; Nonami, K. Nonlinear adaptive control for small-scale helicopter. J. Syst. Des. Dyn. 2011, 5, 866–880. 84. Li, L.R.; Wang, Z.H.; Li, Z.; Lu, Q.; Ma, G.X. The Adaptive Control Method of the Energy-efficient Tunnel Lighting System. In Proceedings of the International Conference oInternational Conference on Advances in Management Engineering and Information Technology (AMEIT), Bangkok, Thailand, 28–29 June 2015. 85. Trivedi, A.; Singh, M. L-1 Adaptive Droop Control for AC Microgrid With Small Mesh Network. IEEE Trans. Ind. Electron. 2018, 65, 4781–4789. doi:10.1109/TIE.2017.2772211. 86. Rajagopal, K.; Karthikeyan, A.; Srinivasan, A.K. FPGA implementation of novel fractional-order chaotic systems with two equilibriums and no equilibrium and its adaptive sliding mode synchronization. Nonlinear Dyn. 2017, 87, 2281–2304. doi:10.1007/s11071-016-3189-z. 87. Karthikeyan, R.; Prasina, A.; Babu, R.; Raghavendran, S. FPGA implementation of novel synchronization methodology for a new chaotic system. Indian J. Sci. Technol. 2015, 8. doi:10.17485/ijst/2015/v8i11/71775. 88. Quang, N.K.; Hieu, N.T.; Ha, Q.P. FPGA-Based Sensorless PMSM Speed Control Using Reduced-Order Extended Kalman Filters. IEEE Trans. Ind. Electron. 2014, 61, 6574–6582. doi:10.1109/TIE.2014.2320215. 89. Idkhajine, L.; Monmasson, E. Optimized FPGA-based Extended Kalman Filter application to an AC drive sensorless speed controller. In Proceedings of the 2010 International Symposium on Power Electronics, Electrical Drives, Automation and Motion, SPEEDAM 2010, Pisa, Italy, 14–16 June 2010. doi:10.1109/SPEEDAM.2010.5545150. 90. Pantea, A.; Aroquiadassou, G.; Mabwe, A.; Martis, C. Real-time sensorless vector control of induction machines using an FPGA board. In Proceedings of the 21st International Symposium on Power Electronics, Electrical Drives, Automation and Motion, SPEEDAM 2012, Sorrento,Italy, 20–22 June 2012. doi:10.1109/SPEEDAM.2012.6264393. 91. Maalouf, A.; Le Ballois, S.; Monmasson, E.; Midy, J.Y.; Bruzy, C. FPGA-based sensorless control of brushless synchronous starter generator at standstill and low speed using high frequency signal injection for an aircraft application. In Proceedings of the ICELIE/IES Industry Forum/37th Annual Conference of the IEEE Industrial-Electronics-Society (IECON), Melbourne, Australia, 7–10 November 2011. 92. Ma, Z.; Gao, J.; Kennel, R. FPGA Implementation of a Hybrid Sensorless Control of SMPMSM in the Whole Speed Range. IEEE Trans. Ind. Inform. 2013, 9, 1253–1261. doi:10.1109/TII.2012.2221132. 93. Ma, Z.; Kennel, R. System-on-Chip sensorless control of PMSM combining signal injection and flux observer. In Proceedings of the 2012 IEEE 7th International Power Electronics and Motion Control Conference - ECCE Asia, IPEMC 2012, Harbin, China, 2–5 June 2012. doi:10.1109/IPEMC.2012.6259006. Computation 2019, xx, 5 30 of 115 94. Jezernik, K.; Rodic, M. Torque Sensorless Control of Induction Motor; IEEE: 6, 2008; pp. 2283–2288. In Proceedings of the 13th International Power Electronics and Motion Control Conference, Poznan, Poland, 1–3 September 2008. doi:10.1109/EPEPEMC.2008.4635603. 95. Wolfram, S. Cellular Automata And Complexity: Collected Papers; CRC Press: Boca Raton, FL, USA, 2018. 96. Chapuis, Y.A.; Zhou, L.; Fukuta, Y.; Mita, Y.; Fujita, H. FPGA-based decentralized control of arrayed MEMS for microrobotic application. IEEE Trans. Ind. Electron. 2007, 54, 1926–1936. doi:10.1109/TIE.2007.898297. 97. Li, Y.F.; Chuang, L.L. Controller design for music playing robot - applied to the anthropomorphic piano robot. In Proceedings of the IEEE 10th International Conference on Power Electronics and Drive Systems (PEDS), Kitakyushu, Japan, 22–25 April 2013. 98. Li, Y.F. FPGA-based module design for PM linear motor control-applied to music playing robot. In Proceedings of the IEEE International Symposium on Industrial Electronics (ISIE), Taipei, Taiwan, 28–31 May 2013. 99. Li, Y.F. FPGA-Based Distributed Control Module Design for Music Playing Robot - Applied to the Anthropomorphic Piano Robot Control. J. Chin. Soc. Mech. Eng. 2013, 34, 143–150. 100. Costillo, L.; Ramos, J.; Ibanez, J.; Aparicio, B.; Herranz, M.; Garcia, A. New control system for the 1.5m and 0.9m telescopes at Sierra Nevada Observatory. In Proceedings of the Advanced Software and Control for Astronomy, Orlando, FL, USA, 24–26 May 2006. doi:10.1117/12.671308. 101. Cherif, S.; Trabelsi, C.; Meftali, S.; Dekeyser, J.L. High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGA. In Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, DASIP 2011, Tampere, Finland, 2–4 November 2011. doi:10.1109/DASIP.2011.6136896. 102. Trabelsi, C.; Meftali, S.; Dekeyser, J.L. Distributed control for reconfigurable FPGA systems: a high-level design approach. In Proceedings of the 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), York, UK, 9–11 July 2012. 103. Trabelsi, C.; Meftali, S.; ben Atitallah, R.; Dekeyser, J.L. Model-Driven design flow for distributed control in reconfigurable FPGA systems. In Proceedings of the 8th Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8–10 October 2014. 104. Sarpotdar, M.; Mathew, J.; Safonova, M.; Murthy, J. A generic FPGA-based detector readout and real-time image processing board. In Proceedings of the Conference on High Energy, Optical, and Infrared Detectors for Astronomy VII, Edinburgh, UK, 26–29 June 2016. doi:10.1117/12.2233292. 105. Bendapudi, S.; Kashyap, G.K.; Lithin, M.G.; Subhajit, M.; KrishnamPrasad, B.; Shashikala, T.H. Design of Video Processor for Multi-head Star Sensor. In Proceedings of the 2nd International Symposium on Physics and Technology of Sensors, Pune, India, 8–10 March 2015. 106. Strauss, M.; Westbrook, E.; Naday, I.; Coleman, T.; Westbrook, M.; Travis, D.; Sweet, R.; Pflugrath, J.; Stanton, M. CCD-based detector for protein crystallography with synchrotron X-rays. Nucl. Instrum. Methods Phys. Res. Sect. A: Accel. Spectrom. Detect. Assoc. Equip. 1990, 297, 275–295. 107. Bredthauer, G. Archon: A modern controller for high performance astronomical CCDs. In Proceedings of the 5th Conference on Ground-Based and Airborne Instrumentation for Astronomy, Montreal, Canada, 22–26 June 2014. doi:10.1117/12.2058402. 108. Liu, S.; Zhao, K.S.; Long, Z.C.; Feng, L. Embedded CCD acquisition system based on ARM and FPGA. Guangdianzi Jiguang/J. Optoelectron. Laser 2007, 18, 1296–1298. 109. Wang, B.; Bai, Y.L.; Ou-Yang, X.; Liu, B.Y.; Bai, X.H.; Zhao, J.P. Spectrum data acquisition system based on linear CCD. Guangzi Xuebao/Acta Photonica Sin. 2010, 39, 441–445. doi:10.3788/gzxb20103903.0441. 110. Zhang, Y.; Jin, M.; Zhang, Y.; Liu, H. Development of High-speed and Highly Integrated CCD Laser Range Sensor Based on FPGA. In Proceedings of the 11th World Congress on Intelligent Control and Automation, Shenyang, China, 29 June–4 July 2014. 111. Kasprowicz, G.; Czyrkowski, H.; Dabrowski, R.; Dominik, W.; Mankiewicz, L.; Pozniak, K.; Romaniuk, R.; Sitek, P.; Sokolowski, M.; Sulej, R.; Uzycki, J.; Wrochna, G. New low noise CCD cameras for “Pi of the Sky” project. In Proceedings of the Conference on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2006, Wilga, Poland, 29 May–4 June 2006. doi:10.1117/12.714861. 112. Burd, A.; Czyrkowski, H.; Dabrowski, R.; Dominik, W.; Grajda, M.; Kasprowicz, G.; Mankiewicz, L.; Stankiewicz, S.; Wrochna, G. Low noise CCD cameras for wide field astronomy. In Proceedings of the Computation 2019, xx, 5 31 of 115 Conference on Photonics, Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments IV, Wilga, Poland, 30 May–5 June 2005. doi:10.1117/12.674872. 113. Xu, W.H.; Wu, H.D. Design of ultra-high resolution CCD imaging systems. Guangxue Jingmi Gongcheng/Optics Precis. Eng. 2012, 20, 1603–1610. doi:10.3788/OPE.20122007.1603. 114. Zhiyong, L.; Weihua, Y.; Xiance, D. The analog front end of ultra-high resolution CCD design based on AD9920A. In Proceedings of the 8th International Conference on Intelligent Computation Technology and Automation (ICICTA), Nanchang, China, 14–15 June 2015. doi:10.1109/ICICTA.2015.234. 115. Li, F.N.; Wang, Y.J.; Zhang, T.; Sun, H.H. Design of high-speed high-resolution CMOS camera acquisition system based on AM41V4 sensor. Chin. J. Liq. Cryst. Disp. 2015, 30, 492–498. doi:10.3788/YJYXS20153003.0492. 116. Sun, H.; Cai, R.; Wang, Y. Design and implementation of high-speed digital CMOS camera driving control timing and data interface. In Proceedings of the Sixth International Symposium on Instrumentation and Control Technology: Sensors, Automatic Measurement, Control and Computer Simulation, Beijing, 13–15 October 2006. doi:10.1117/12.717638. 117. Ge, Z.W.; Yao, S.Y.; Xu, J.T.; Su, X.H. A fast automatic exposure control method for CMOS image sensor. Tianjin Daxue Xuebao (Ziran Kexue yu Gongcheng Jishu Ban)/J. Tianjin Univ. Sci. Technol. 2010, 43, 854–859. 118. An, R.; Chen, Y.; Xie, J. Exposure algorithm for CMOS image sensor with adaptive dynamic range. Hongwai yu Jiguang Gongcheng/Infrared and Laser Eng. 2013, 42, 88–92. 119. Liu, Y.; Wu, Z.; Liu, C.; Zhu, X.; Liu, G. Study on an Auto Exposure Algorithm Applied in CMOS Image Sensor for Security Monitoring. Bandaoti Guangdian/Semicond. Optoelectron. 2017, 38, 283–287. doi:10.16818/j.issn1001-5868.2017.02.027. 120. Yang, W.C.; Wen, D.S.; Chen, S.D.; Wang, H. Spatial transient light detection based on high-speed CMOS image sensor. Guangzi Xuebao/Acta Photonica Sin. 2010, 39, 764–768. doi:10.3788/gzxb20103904.0764. 121. Yang, D.; Hu, X.; Li, J. Multiple slope integration based on CMOS image sensor. Hongwai Yu Jiguang Gongcheng/Infrared Laser Eng. 2012, 41, 1499–1502. 122. Fross, B.; Donaldson, R.; Palmer, D. PCI-based WILDFIRE reconfigurable computing engines. In Proceedings of the High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, Boston, MA, USA, 20–21 November 1996. doi:10.1117/12.255813. 123. Mizuno, K.; Noguchi, H.; He, G.; Terachi, Y.; Kamino, T.; Kawaguchi, H.; Yoshimoto, M. Fast and low-memory-bandwidth architecture of SIFT descriptor generation with scalability on speed and accuracy for VGA video. In Proceedings of the 20th International Conference on Field Programmable Logic and Applications, FPL 2010, Milano, Italy, 31 August–2 September 2010. 124. Zhang, J.M.; Jiang, X.Y.; Zhang, Z.L. Gray-scale control of synchronous VGA display by OLED matrix. Guangdianzi Jiguang/J. Optoelectron. Laser 2006, 17, 131–134. 125. Gao, K.; Cai, J.; Zhang, L.; Sheng, R.n. A SoPC-Based Mini VGA Video Capture and Storage System. In Proceedings of the 2010 3rd International Conference on Biomedical Engineering and Informatics (BMEI 2010), Yantai Univ, Yantai, China, 16–18 October 2010. doi:10.1109/BMEI.2010.5639844. 126. Sajjanar, S.; Mankani, S.K.; Dongrekar, P.R.; Kumar, N.S.; Mohana.; Aradhya, H.V.R. Implementation of Real Time Moving Object Detection and Tracking on FPGA for Video Surveillance Applications. In Proceedings of the IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), Natl Inst Technol Karnataka, Mangalore, India, 13–14 August 2016. 127. Murali, K.B.; Tejaswi, P.; Madhumati, G.; Vinay, K.K. Real time delay application for digital circuits with peripheral based digital clock using FPGA. Int. J. Appl. Eng. Res. 2014, 9, 5115–5124. 128. Bertazzoni, S.; Di, G.D.; Salmeri, M.; Mongiardo, L.; Florean, M.; Salsano, A.; Wyss, J.; Rando, R. TID test for SDRAM based IEEM calibration system. In Proceedings of the 2004 Nuclear Science Symposium, Medical Imaging Conference, Symposium on Nuclear Power Systems and the 14th International Workshop on Room Temperature Semiconductor X- and Gamma- Ray Detectors, Rome, Italy, 16–22 October 2004. 129. Bunkowski, K.; Kassamakov, I.; Krolikowski, J.; Kierzkowski, K.; Kudla, M.; Maenpaa, T.; Pozniak, K.; Rybka, D.; Tuominen, E.; Ungaro, D.; Zabolotny, W. Irradiation effects in electronic components of the RPC Trigger for the CMS Experiment. In Proceedings of the 12th IEEE-SPIE Symposium on Photonics and Web Engineering, Warsaw Univ Technol Resort, Wilga, Poland, 21–25 May 2003. doi:10.1117/12.568897. 130. Marek, T.; Novotny, M.; Crha, L. Design and implementation of the memory scheduler for the PC-based router. FIELD-Program. Log. Appl. Proc. 2004, 3203, 1133–1135. Computation 2019, xx, 5 32 of 115 131. Park, S.H.; An, J.S.; Tae-Seok, O.; Kim, I.H. Design of high speed camera based on cmos technology - art. no. 679414. In Proceedings of the 4th International Conference on Metronics and Information Technology (ICMIT 2007), Gifu, Japan, 5–6 December 2007. 132. Osmanis, K.; Valters, G.; Osmanis, I. 3D Volumetric Display Design Challenges. In Proceedings of the NORCHIP Conference, Vilnius, Lithuania, 11–12 November 2013. 133. Singla, D.; Sachdeva, M.; Malhotra, D.; Singh, H. Thermal and energy efficient RAM design on 28nm for electronic devices. Indian J. Sci. Technol. 2016, 9. doi:10.17485/ijst/2016/v9i21/94832. 134. Kalia, K.; Pandey, B.; Hussain, D.M.A. SSTL Based Thermal and Power Efficient RAM Design on 28nm FPGA for Spacecraft. In Proceedings of the 6th International Conference on Smart Grid and Clean Energy Technologies (ICSGCE), Univ Elect Sci & Technol China, Chengdu, China, 19–22 October 2016. 135. Gandhi, J.; Ang, B.; Lee, T.; Liu, H.; Kim, M.; Lee, H.; Refai-Ahmed, G.; Shi, H.; Ramalingam, S. 2.5D FPGA-HBM integration challenges. Adv. Microelectron. 2017, 44, 12–16. 136. Meixner, A.; Kakizawa, A.; Provost, B.; Bedwani, S. External Loopback Testing Experiences with High Speed Serial Interfaces. In Proceedings of the 2008 IEEE International Test Conference, Santa Clara, CA, USA, 28–30 October 2008. doi:10.1109/TEST.2008.4700557. 137. Kono, M.; Kanbe, A.; Toyoda, H. A 400-Gb/s and Low-power Physical-layer Architecture for Next-generation Ethernet. In Proceedings of the IEEE International Conference on Communications (ICC), Kyoto, Japan, 5–9 June 2011. 138. Kono, M.; Kanbe, A.; Toyoda, H.; Nishimura, S. A Novel 400-Gb/s (100-Gb/s x 4) Physical-Layer Architecture Using Low-Power Technology. IEICE Trans. Commun. 2012, E95B, 3437–3444. doi:10.1587/transcom.E95.B.3437. 139. Jansweijer, P.P.M.; Peek, H.Z. Measuring propagation delay over a coded serial communication channel using FPGAs. Nucl. Instrum. Methods Phys. Res. Sect. A: Accel. Spectrometers Detect. Assoc. Equip. 2011, 626, S169–S172. doi:10.1016/j.nima.2010.04.126. 140. Exel, R.; Bigler, T.; Sauter, T. Asymmetry Mitigation in IEEE 802.3 Ethernet for High-Accuracy Clock Synchronization. IEEE Trans. Instrum. Meas. 2014, 63, 729–736. doi:10.1109/TIM.2013.2280489. 141. Freire, I.; Sousa, I.; Klautau, A.; Almeida, I.; Lu, C.; Berg, M. Analysis and Evaluation of End-to-End PTP Synchronization for Ethernet-based Fronthaul. In Proceedings of the 59th Annual IEEE Global Communications Conference (IEEE GLOBECOM), Washington, DC, USA, 4–8 December 2016. 142. Cho, J.H.; Kim, H.; Yoon, C.H.; Cho, S.; Lee, T.J. Ethernet transport system supporting delay-sensitive real-time traffics. Int. J. Commun. Syst. 2014, 27, 2366–2376. doi:10.1002/dac.2480. 143. Ademaj, A.; Kopetz, H. Time-triggered Ethernet and IEEE 1588 clock synchronization; IEEE: 3, 2007; pp. 41–43. In Proceedings of the IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication, Austrian Acad Sci, Vienna, Austria, 1–3 October 2007. doi:10.1109/ISPCS.2007.4383771. 144. Bai, J.; Wu, L.; Yun, N.; Liu, Y.; Zhang, X. A 10Gbps In-line Network Security Processor with a 32-bit Embedded CPU. In Proceedings of the 22nd Wireless and Optical Communications Conference (WOCC), Chongqing Univ Posts & Telecommunicat, Chongqing, China, 16–18 May 2013. 145. Niu, Y.; Wu, L.; Wang, L.; Zhang, X.; Xu, J. A configurable IPSec processor for high performance in-line security network processor. In Proceedings of the 2011 7th International Conference on Computational Intelligence and Security, CIS 2011, Sanya, China, 3–4 December 2011. doi:10.1109/CIS.2011.154. 146. Haene, S.; Perels, D.; Burg, A. A real-time 4-stream MIMO-OFDM transceiver: System design, FPGA implementation, and characterization. IEEE J. Sel. Areas Commun. 2008, 26, 877–889. doi:10.1109/JSAC.2008.080805. 147. Iacono, D.; Ronchi, M.; Torre, L.; Osnato, F. MIMO OFDM Physical layer real-time prototyping. In Proceedings of the IEEE Wireless Communications and Networking Conference, WCNC 2008, Las Vegas, NV, USA, 31 March–3 April 2008. 148. Park, J.S.; Ogunfunmi, T. Efficient FPGA-Based Implementations of MIMO-OFDM Physical Layer. Circuits Syst. Signal Process. 2012, 31, 1487–1511. doi:10.1007/s00034-012-9411-4. 149. Park, J.S.; Ogunfunmi, T. FPGA implementation of Channel Estimation for MIMO-OFDM. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, 15–18 May 2011. Computation 2019, xx, 5 33 of 115 150. Vincent, H.M.J.; Dahmane, A.; Moussa, S.; D’Amours, C. Rapid prototyping of channel estimation techniques in MIMO-OFDM systems. In Proceedings of the 2013 6th Joint IFIP Wireless and Mobile Networking Conference, WMNC 2013, Dubai, UAE, 23–25 April 2013. doi:10.1109/WMNC.2013.6549034. 151. Sudhakar, R.P.; Ramachandra, R.R. Design and FPGA implementation of channel estimation method and modulation technique for MIMO system. Eur. J. Sci. Res. 2009, 25, 257–265. 152. Zhang, H.; Zhao, J. The design of RF data acquisition system based on STM32 and FPGA. In Proceedings of the 2nd International Conference on Multimedia Technology, ICMT 2011, Hangzhou, 26–28 July 2011. doi:10.1109/ICMT.2011.6002030. 153. Cabrini, A.; Gobbi, L.; Baderna, D.; Torelli, G. A compact low-cost test equipment for thermal and electrical characterization of integrated circuits. Measurement 2009, 42, 281–289. doi:10.1016/j.measurement.2008.06.011. 154. Liu, J.; Niu, Y.; Dong, W.; Si, B.; Liu, J. Design and application of video signal generator based on FPGA. Yi Qi Yi Biao Xue Bao/Chin. J. Sci. Instrum. 2008, 29, 654–657. 155. Wen, F.; Xia, L.; Liang, F.; Dong, J.; Wang, Q.; Jin, G. Development of lidar data acquisition system for visibility measurement. Hongwai Yu Jiguang Gongcheng/Infrared Laser Eng. 2011, 40, 52–56. 156. Huixin, Z.; Qi, H.; Suhua, L.; Haiguang, Y. The design for LVDS high-speed data acquisition and transmission system based on FPGA. In Proceedings of the 2011 IEEE 3rd International Conference on Communication Software and Networks, ICCSN 2011, Xi’an, 27–29 May 2011. doi:10.1109/ICCSN.2011.6014590. 157. Wang, A.; Li, Z.; Yang, X.; Feng, B. A new security problem of USB: Monitoring cable attack and countermeasures. In Proceedings of the 2012 International Conference on Information Technology and Software Engineering, ITSE 2012, Beijing, 8–10 December 2012. doi:10.1007/978-3-642-34522-7_15. 158. Yang, X.; Li, Z.; Wang, A.; Zhang, Y. System design of cryptographic security USB device controller IP core. Huazhong Keji Daxue Xuebao (Ziran Kexue Ban)/J. Huazhong Univ. Sci. Technol. (Nat. Sci. Ed.) 2010, 38, 59–62. 159. Yang, Y.T.; Zhang, S.T.; Li, Z.C.; Zhang, M.D.; Cao, G.C. Design and Implementation for High Speed Data Transfer Interface of PCI Express Based on Zynq Platform. Dianzi Keji Daxue Xuebao/J. Univ. Electron. Sci. Technol. China 2017, 46, 522–528. doi:10.3969/j.issn.1001-0548.2017.03.008. 160. Byszuka, A.; Pozniak, K.; Zabolotny, W.M.; Kasprowicz, G.; Wojenski, A.; Cieszewski, R.; Juszczyk, B.; Kolasinski, P.; Zienkiewicz, P.; Chernyshova, M.; Czarski, T. Fast data transmission in dynamic data acquisition system for plasma diagnostics. In Proceedings of the Conference on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments, Wilga, Poland, 26 May–1 June 2014. doi:10.1117/12.2076089. 161. Bittner, R.; Ruf, E.; Forin, A. Direct GPU/FPGA communication Via PCI express. Clust.-Comput.- J. Networks Softw. Tools Appl. 2014, 17, 339–348. doi:10.1007/s10586-013-0280-9. 162. Thoma, Y.; Dassatti, A.; Molla, D.; Petraglio, E. FPGA-GPU communicating through PCIe. Microprocess. Microsyst. 2015, 39, 565–575. doi:10.1016/j.micpro.2015.02.005. 163. Wu, A.; Jin, X.; Guo, S.; Du, X. A Flexible FPGA-to-FPGA Interconnect Interface Design and Implementation. In Proceedings of the International Conference on Computers, Communications and Systems (ICCCS), Kanyakumari, India, 2–3 November 2015. 164. An, W.; Jin, X.; Du, X.; Guo, S. A Flexible FPGA-to-FPGA Communication System. In Proceedings of the 18th International Conference on Advanced Communication Technology (ICACT), Pyeongchang, Korea, 31 Janrary–3 February 2016. 165. Bono, S.; Green, M.; Stubblefield, A.; Juels, A.; Rubin, A.; Szydlo, M. Security analysis of a cryptographically-enabled RFID device. In Proceedings of the 14th USENIX Security Symposium, Baltimore, MD, USA, 31 July–5 August 2005. 166. Kavun, E.B.; Yalcin, T. A Lightweight Implementation of Keccak Hash Function for Radio-Frequency Identification Applications. In Proceedings of the 6th Workshop on Radio Frequency Identification Security, Istanbul, Turkey, 8–9 June 2010. 167. Fu, L.; Shen, X.; Zhu, L.; Wang, J. A low-cost UHF RFID tag chip with AES cryptography engine. Secur. Commun. Netw. 2014, 7, 365–375. doi:10.1002/sec.723. 168. Fang, Y.Y.; Chen, X.J. Design and simulation of UART serial communication module based on VHDL. In Proceedings of the 2011 3rd International Workshop on Intelligent Systems and Applications, ISA 2011, Wuhan, China, 28–29 May 2011. doi:10.1109/ISA.2011.5873448. Computation 2019, xx, 5 34 of 115 169. Ali, L.; Sidek, R.; Aris, I.; Ali, A.; Suparjo, B. Design of a micro-UART for SoC application. Comput. Electr. Eng. 2004, 30, 257–268. doi:10.1016/j.compeleceng.2003.01.002. 170. Wakhle, G.; Aggarwal, I.; Gaba, S. Synthesis and implementation of UART using VHDL codes. In Proceedings of the 2012 International Symposium on Computer, Consumer and Control, IS3C 2012, Taichung, Taiwan, 4–6 June 2012. doi:10.1109/IS3C.2012.10. 171. Kammerer, R.; Obermaisser, R.; Fromel, B. A router for the containment of timing and value failures in CAN. Eurasip J. Embed. Syst. 2012, 2012. doi:10.1186/1687-3963-2012-4. 172. Lee, T.Y.; Kuo, C.W.; Lin, I.A. High Performance CAN/FlexRay Gateway Design for In-Vehicle Network. In Proceedings of the IEEE Conference on Dependable and Secure Computing, Taipei, Taiwan, 7–10 August 2017. 173. Mellal, I.; Laghrouche, M.; Bui, H.T. Field Programmable Gate Array (FPGA) Respiratory Monitoring System Using a Flow Microsensor and an Accelerometer. Meas. Sci. Rev. 2017, 17, 61–67. doi:10.1515/msr-2017-0008. 174. Kumari, R.S.S.; Gayathri, C. Interfacing of mems motion sensor with fpga using 12c protocol. In Proceedings of the International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS), Karpagam Coll Engn, Coimbatore, India, 17–18 March 2017. 175. Feng, Z.; Qinzhang, W.; Guoqiang, R. A High-speed Method of CCD Image Data Storage System. In Proceedings of the 2nd IEEE International Conference on Advanced Computer Control, Shenyang, China, 27–29 March 2010. doi:10.1109/ICACC.2010.5487181. 176. Zhang, F.; Wu, Q.; Ren, G. A high-speed method of CCD image data storage system based on SATA. Bandaoti Guangdian/Semicond. Optoelectron. 2010, 31, 782–786. 177. Wu, Q.; Song, T.; Li, X. Research on the High-Speed Image Acquisition and Storage Technology based on TMS320C6748. In Proceedings of the 4th National Conference on Electrical, Electronics and Computer Engineering (NCEECE), Xi’an, China, 12–13 December 2015. 178. Dillinger, M.; Madani, K.; Alonistioti, N. Software Defined Radio: Architectures, Systems and Functions; Wiley Series in Software Radio, Wiley: Hoboken, NJ, USA, 2005; 179. Garcia, J.; Cumplido, R. On the design of an FPGA-based OFDM modulator for IEEE 802.11a. In Proceedings of the 2nd International Conference on Electrical and Electronics Engineering (ICEEE 2005), Mexico City, Mexico, 7–9 September 2005. doi:10.1109/ICEEE.2005.1529586. 180. Garcia, J.; Cumplido, R. On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs, Puebla, Mexico, 28–30 September 2005. 181. Bluemm, C.; Heller, C.; Weigel, R. SDR OFDM Waveform Design for a UGV/UAV Communication Scenario. J. Signal Process. Syst. Signal Image Video Technol. 2012, 69, 11–21. doi:10.1007/s11265-011-0640-8. 182. Zhang, B.; Guo, X. A Novel Reconfigurable Architecture for Generic OFDM Modulator Based on FPGA. In Proceedings of the 16th International Conference on Advanced Communication Technology (ICACT), Korea, 16–19 February 2014. 183. Ribeiro, C.; Gameiro, A. A software-defined radio FPGA implementation of OFDM-based PHY transceiver for 5G. Analog. Integr. Circuits Signal Process. 2017, 91, 343–351. doi:10.1007/s10470-017-0939-x. 184. Al Safi, A.; Bazuin, B. FPGA Based Implementation of BPSK and QPSK Modulators using Address Reverse Accumulators. In Proceedings of the 7th IEEE Annual Ubiquitous Computing, Electronics and Mobile Communication Conference (IEEE UEMCON), New York, NY, USA, 20–22 October 2016. 185. Nivin, R.; Rani, J.S.; Vidhya, P. Design and Hardware Implementation of Reconfigurable Nano Satellite Communication System Using FPGA Based SDR for FM/ FSK Demodulation and BPSK Modulation. In Proceedings of the International Conference on Communication Systems and Networks (ComNet), Trivandrum, India, 21–23 July 2016. 186. Kazaz, T.; Kulin, M.; Hadzialic, M. Design and Implementation of SDR Based QPSK Modulator on FPGA. In Proceedings of the 36th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), Opatija, Croatia, 20–24 May 2013. 187. Jakubov, O.; Kovar, P.; Kacmarik, P.; Vejrazka, F. The Witch Navigator - A Low Cost GNSS Software Receiver for Advanced Processing Techniques. Radioengineering 2010, 19, 536–543. 188. Kovar, P.; Vejrazka, F. Software radio and its applications in GNSS. In Proceedings of the 46th International Symposium Electronics in Marine (ELMAR -2004), Zadar, Croatia, 16–18 June 2004. Computation 2019, xx, 5 35 of 115 189. Puricer, P.; Kovar, P.; Seidl, L.; Vejrazka, F. GNSS software receiver - A versatile platform for navigation systems signals processing. In Proceedings of the 47th International Symposium ELMAR-2005 on Multimedia Systems and Applications, Zadar, Croatia, 8–10 June 2005. 190. Raju, K.; Pratap, Y.; Patel, V.; Kumar, G.; Naidu, S.; Patwardhan, A.; Henry, R.; Bhanu, P.P. Implementation of multichannel GPS receiver baseband modules. In Proceedings of the 2nd International Conference on Computer Science, Engineering and Applications, ICCSEA 2012, New Delhi, India, 25–27 May 2012. doi:10.1007/978-3-642-30157-5_81. 191. Mohamed, K.E.; Ali, B.M.; Jamuar, S.S.; Khatun, S.; Ismail, A. A software defined radio approach for digital CDMA transmitter. In Proceedings of the 4th International Conference on Cybernetics and Information Technologies, Systems and Applications/5th Int Conf on Computing, Communications and Control Technologies, Orlando, FL, USA, 12–15 July 2007. 192. Al Safi, A.; Bazuin, B. Toward Digital Transmitters with Amplitude Shift Keying and Quadrature Amplitude Modulators Implementation Examples. In Proceedings of the 7th IEEE Annual Computing and Communication Workshop and Conference (IEEE CCWC), Las Vegas, NV, USA, 9–11 January 2017. 193. Kumar, A.K.A. FPGA Implementation of QAM Modems Using PR for Reconfigurable Wireless Radios. In Proceedings of the Annual International Conference on Emerging Research Areas (AICERA) / International Conference on Microelectronics, Communication and Renewable Energy (ICMiCR), Amal Jyothi Coll Engn, Kanjirapally, India, 4–6 June 2013. 194. Khan, M.A.; Ansari, A.Q. Design of 8-Bit Programmable Crossbar Switch for Network-on-Chip Router. In Proceedings of the 4th International Conference on Network Security and Applications (CNSA 2011), Chennai, India, 15–17 July 2011. 195. Karadeniz, T.; Mhamdi, L.; Goossens, K.; Garcia-Luna-Aceves, J.J. Hardware Design and Implementation of a Network-on-Chip Based Load Balancing Switch Fabric. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 5–7 December 2012. 196. Sharma, R.; Joshi, V.; Rohokale, V. Performance of router design for Network-on-Chip implementation. In Proceedings of the 2012 International Conference on Communication, Information and Computing Technology, ICCICT 2012, Mumbai, India, 19–20 October 2012. doi:10.1109/ICCICT.2012.6398142. 197. Bayar, S.; Yurdakul, A. An Efficient Mapping Algorithm on 2-D Mesh Network-on-Chip with Reconfigurable Switches. In Proceedings of the 11th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Istanbul, Turkey, 12–14 April 2016. 198. Bansal, S.; Sharma, S.; Sharma, N. Design of Configurable Power Efficient 2-Dimensional Crossbar Switch For Network-on-Chip(NoC). In Proceedings of the IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT), Sri Venkateshwara Coll Engn, Dept Elect & Commun Engn, Bengaluru, India, 20–21 May 2016. 199. Bansal, S.; Sharma, S.; Sharma, N. Design of Configurable Power Efficient 3-Dimensional Crossbar Switch For Network-on-Chip(NoC). In Proceedings of the 2nd International Conference on Advances in Computing, Communication, and Automation (ICACCA) (Fall), Bareilly, India, 30 September–1 October 2016. 200. Khan, M.; Ansari, A. N-Bit multiple read and write FIFO memory model for network-on-chip. In Proceedings of the 2011 World Congress on Information and Communication Technologies, WICT 2011, Mumbai, India, 11–14 December 2011. doi:10.1109/WICT.2011.6141440. 201. Ortega-Cisneros, S.; Cabrera-Villasenor, H.J.; Raygoza-Panduro, J.J.; Sandoval, F.; Loo-Yau, R. Hardware and Software Co-design: An Architecture Proposal for a Network-on-Chip Switch based on Buffer less Data Flow. J. Appl. Res. Technol. 2014, 12, 153–163. doi:10.1016/S1665-6423(14)71615-3. 202. Elhajji, M.; Attia, B.; Zitouni, A.; Tourki, R.; Meftali, S.; Dekeyser, J.L. FeRoNoC: Flexible and extensible router implementation for diagonal mesh topology. In Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, DASIP 2011, Tampere, Finland, 2–4 November 2011. doi:10.1109/DASIP.2011.6136890. 203. Zakaria, F.F.; Latif, N.A.A.; Hashim, S.J.; Ehkan, P.; Rokhani, F.Z. Cooperative Virtual Channel Router for Adaptive Hardwired FPGA Network-on-Chip. In Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, Korea, 25–28 October 2016. 204. Kamal, R.; Moreno Arostegui, J.M. Design and Analysis of DMA based Network Interface for NoC’s Router. In Proceedings of the IEEE International Conference on Recent Trends in Electronics, Information Computation 2019, xx, 5 36 of 115 and Communication Technology (RTEICT), Sri Venkateshwara Coll Engn, Dept Elect & Commun Engn, Bengaluru, India, 20–21 May 2016. 205. Jayan, G.; Pavitha, P.P. FPGA Implementation of an Efficient Router Architecture Based on DMC. In Proceedings of the IEEE International Conference on Emerging Technological Trends in Computing, Communications and Electrical Engineering (ICETT), Sasthancotta, India, 21–22 October 2016. 206. Kashwan, K.R.; Selvaraj, G. Implementation and Performance Analyses of a Novel Optimized NoC Router. In Proceedings of the International Conference for Convergence of Technology (I2CT), Pune, India, 6–8 April 2014. 207. Shahane, P.; Pisharoty, N. Implementation of input block of minimally buffered deflection NoC Router. Int. J. Eng. Technol. 2016, 8, 1796–1800. doi:10.21817/ijet/2016/v8i4/160804415. 208. Kamali, H.M.; Hessabi, S. AdapNoC: A Fast and Flexible FPGA-based NoC Simulator. In Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL), Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland, 29 August–2 September 2016. doi:10.1109/FPL.2016.7577377. 209. Sanju, V.; Koushika, C.; Sharmili, R.; Chiplunkar, N.; Khalid, M. Design and implementation of a network on chip-based simulator: A performance study. Int. J. Comput. Sci. Eng. 2014, 9. 95–105. doi:10.1504/IJCSE.2014.058702. 210. Killian, C.; Tanougast, C.; Monteiro, M.; Diou, C.; Dandache, A.; Jovanovic, S. Behavioral modeling and C-VHDL co-simulation of network on chip on FPGA for education. In Proceedings of the 5th International Workshop on Reconfigurable Communication-Centric Systems on Chip 2010, ReCoSoC 2010, Karlsruhe, Germany, 17–19 May 2010. 211. VENKATESWARAN, R.; MAZUMDER, P. A survey of da techniques for pld and fpga based systems. Integr. VLSI J. 1994, 17, 191–240. doi:10.1016/0167-9260(94)90001-9. 212. Lockwood, J.; Naufel, N.; Turner, J.; Taylor, D. Reprogrammable network packet processing on the Field Programmabl Port Extender (FPX). In Proceedings of the 2001 ACM/SIGDA 9th International Sysmposium on Field Programmable Gate Arrays (FPGA 2001), Monterrey, CA, USA, 11–13 February 2001. 213. Braun, F.; Lockwood, J.; Waldvogel, M. Layered protocol wrappers for Internet packet processing in reconfigurable hardware. In Proceedings of the HOT 9 Interconnects. Symposium on High Performance Interconnects. Stanford, CA, USA, 22–24 August 2001. doi:10.1109/HIS.2001.946699. 214. Zhang, Y.; Lan, J.L.; Hu, Y.X.; Wang, P.; Duan, T. A polymorphic routing system providing flexible customization for service. Tien Tzu Hsueh Pao/Acta Electron. Sin. 2016, 44, 988–994. doi:10.3969/j.issn.0372-2112.2015.04.033. 215. Kwon, A.; Zhang, K.; Lim, P.; Pan, Y.; Smith, J.; Dehon, A. RotoRouter: Router support for endpoint-authorized decentralized traffic filtering to prevent DoS attacks. In Proceedings of the 2014 International Conference on Field-Programmable Technology (FPT), Shanghai, China, 10–12 December 2014. doi:10.1109/FPT.2014.7082774. 216. Gibb, G.; Lockwood, J.W.; Naous, J.; Hartke, P.; McKeown, N. NetFPGA - An open platform for teaching how to build gigabit-rate network switches and routers. IEEE Trans. Educ. 2008, 51, 364–369. doi:10.1109/TE.2008.919664. 217. Chan, P.; Schlag, M.; Ebeling, C.; McMurchie, L. Distributed-memory parallel routing for field-programmable gate arrays. IEEE Trans.-Comput.-Aided Des. Integr. Circuits Syst. 2000, 19, 850–862. doi:10.1109/43.856973. 218. Moctar, Y.O.M.; Brisk, P. Parallel FPGA Routing based on the Operator Formulation; IEEE: 6, 2014. In Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 1–5 June 2014. doi:10.1145/2593069.2593177. 219. Gort, M.; Anderson, J.H. Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010. IEEE Trans.-Comput.-Aided Des. Integr. Circuits Syst. 2012, 31, 61–74. doi:10.1109/TCAD.2011.2165715. 220. Muthukaruppan, A.; Suresh, S.; Kamakoti, V. A novel three phase parallel genetic approach to routing for field programmable gate arrays. In Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT), Hong Kong, China„ China, 16–18 December 2002. doi:10.1109/FPT.2002.1188705. 221. Fatima, K.; Rao, R. FPGA Implementation of a New Parallel Routing Algorithm. In Proceedings of the IEEE Region 10 Conference (TENCON 2008), Hyderabad, India, 19–21 November 2008. 222. D’Hollander, E.H.; Stroobandt, D.; Touhafi, A. ParaFPGA 2013: Harnessing Programs, Power and Performance in Parallel FPGA applications. In Proceedings of the International Conference on Parallel Computation 2019, xx, 5 37 of 115 Programming (ParCo), Tech Univ Munchen, Dept Informat, Garching, Germany, 10–13 September 2013. doi:10.3233/978-1-61499-381-0-493. 223. Mitola, J.; Maguire, G.Q. Cognitive radio: making software radios more personal. IEEE Pers. Commun. 1999, 6, 13–18. doi:10.1109/98.788210. 224. Kosunen, M.; Turunen, V.; Kokkinen, K.; Ryynanen, J. Survey and Analysis of Cyclostationary Signal Detector Implementations on FPGA. IEEE J. Emerg. Sel. Top. Circuits Syst. 2013, 3, 541–551. doi:10.1109/JETCAS.2013.2280810. 225. Srinu, S.; Sabat, S. FPGA implementation of spectrum sensing based on energy detection for cognitive radio. In Proceedings of the 2010 IEEE International Conference on Communication Control and Computing Technologies, ICCCCT 2010, Tamil Nadu, India, 7–9 October 2010. doi:10.1109/ICCCCT.2010.5670540. 226. Chaitanya, G.; Rajalakshmi, P.; Desai, U. Real time hardware implementable spectrum sensor for cognitive radio applications. In Proceedings of the 2012 9th International Conference on Signal Processing and Communications, SPCOM 2012, Bangalore, 22–25 July 2012. doi:10.1109/SPCOM.2012.6290024. 227. Nguyen, T.T.; Dang, K.L.; Nguyen, H.V.; Nguyen, P.H. A Real-Time FPGA Implementation of Spectrum Sensing Applying for DVB-T Primary Signal. In Proceedings of the International Conference on Advanced Technologies for Communications (ATC), Ho Chi Minh City, Vietnam, 16–18 October 2013. 228. Wen, Z.; Meng, Z.; Wang, Q.; Liu, L.; Zou, J.; Wang, L. An FPGA real-time spectrum sensing for cognitive radio in very high throughput WLAN. In Proceedings of the Joint International Conference on Pervasive Computing and the Networked World, ICPCA/SWS 2012, Istanbul, Turkey, 28 –30 November 2012. doi:10.1007/978-3-642-37015-1_53. 229. Hanninen, T.; Vartiainen, J.; Juntti, M.; Raustia, M. Implementation of spectrum sensing on wireless open-access research platform. In Proceedings of the 2010 3rd International Symposium on Applied Sciences in Biomedical and Communication Technologies, ISABEL 2010, Roma, Italy, 7–10 November 2010. doi:10.1109/ISABEL.2010.5702910. 230. Kyperountas, S.; Shi, Q.; Vallejo, A.; Correal, N. A MultiTaper Hardware Core for Spectrum Sensing. In Proceedings of the IEEE International Symposium on Dynamic Spectrum Access Networks, Bellevue, WA, USA, 16–19 October 2012. 231. Recio, A.; Athanas, P. Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA. In Proceedings of the 13th Euromicro Conference on Digital System Design on Architectures, Methods and Tools, Lille, France, 1–3 September 2010. doi:10.1109/DSD.2010.110. 232. Ishwerya, P.; Geethu, S.; Lakshminarayanan, G. An Efficient Hybrid Spectrum Sensing Architecture on FPGA. In Proceedings of the 2nd IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), Chennai, India, 22–24 March 2017. 233. Omara, M.O.S.; Suratman, F.Y.; Astuti, R.P. An FPGA Testbed for Spectrum Sensing in Cognitive Radio. In Proceedings of the IEEE Asia Pacific Conference on Wireless and Mobile (APWiMob), Bandung, Indonesia, 28–29 November 2017. 234. Shreejith, S.; Mathew, L.K.; Prasad, V.A.; Fahmy, S.A. Efficient Spectrum Sensing for Aeronautical LDACS Using Low-Power Correlators. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2018, 26, 1183–1191. doi:10.1109/TVLSI.2018.2806624. 235. Sramek, P.; Povalac, K.; Marsalek, R. Experimental evaluation of radio frequency spectrum sensing detectors in tv bands. In Proceedings of the International Conference on Signal Processing and Multimedia Application (SIGMAP 2010), Univ Piraeus, Athens, Greece, 26–28 July 2010. 236. Sunil, D.; Sabat, S. Spectrum sensing using envelope tracking and signal moment. In Proceedings of the 2016 International Conference on Signal Processing and Communication, ICSC 2016, Noida, India, 26–28 December 2016. doi:10.1109/ICSPCom.2016.7980632. 237. Murty, M.S.; Shrestha, R. Hardware-Efficient and Wide-Band Frequency-Domain Energy Detector for Cognitive-Radio Wireless Network; IEEE: 6, 2018; pp. 277–282. In Proceedings of the 31st International Conference on VLSI Design /17th International Conference on Embedded Systems (VLSID & ES)), Pune, India, 6–10 January 2018. doi:10.1109/VLSID.2018.76. 238. Costantine, J.; Tawk, Y.; Barbin, S.E.; Christodoulou, C.G. Reconfigurable Antennas: Design and Applications. Proc. IEEE 2015, 103, 424–437. doi:10.1109/JPROC.2015.2396000. Computation 2019, xx, 5 38 of 115 239. Manoj, S.; Kothari, A. Reconfigurable planar inverted F antenna for cognitive radio & mobile systems. In Proceedings of the 2015 5th International Workshop on Computer Science and Engineering: Information Processing and Control Engineering, Moscow, Russia, 15–17 April 2015. 240. Raut, R.; Kulat, K. Software defined adaptive codec for cognitive radio. WSEAS Trans. Commun. 2009, 8, 1243–1252. 241. Golbon-Haghighi, M.H. Beamforming in Wireless Networks. In Towards 5G Wireless Networks; Bizaki, H.K., Ed.; IntechOpen: Rijeka, Croatia, 2016; Chapter 8. doi:10.5772/66399. 242. Sengupta, A.; Madanayake, A.; Gomez-Garcia, R.; Engeberg, E.D. Wideband Aperture Array using RF Channelizers and Massively-Parallel Digital 2-D IIR Filterbank. In Proceedings of the Conference on Radar Sensor Technology XVIII, Baltimore, MD, USA, 5–7 May 2014. doi:10.1117/12.2053050. 243. Seneviratne, V.; Madanayake, A.; Bruton, L.T. A 480MHz ROACH-2 FPGA Realization of 2-Phase 2-D IIR Beam Filters for Digital RF Apertures. In Proceedings of the Moratuwa Engineering Research Conference (MERCon), Univ Moratuwa, Moratuwa, Sri Lanka, 5–6 April 2016. 244. Thiripurasundari, C.; Sumathy, V.; Thiruvengadam, C. An FPGA implementation of novel smart antenna algorithm in tracking systems for smart cities. Comput. Electr. Eng. 2018, 65, 59–66. doi:10.1016/j.compeleceng.2017.06.009. 245. Kee, H.; Bhattacharyya, S.S.; Wong, I.; Rao, Y. FPGA-based design and implementation of the 3gpp-lte physical layer using parameterized synchronous dataflow techniques. In Proceedings of the 2010 IEEE International Conference on Acoustics, Speech, and Signal Processing, Dallas, TX, USA, 10–19 March 2010. doi:10.1109/ICASSP.2010.5495504. 246. Sleiman, S.; Ismail, M. Multimode Reconfigurable digital sd modulator architecture for fractional-N PLLs. IEEE Trans. Circuits Syst. II Express Briefs 2010, 57, 592–596. doi:10.1109/TCSII.2010.2048480. 247. Abbas, S.; Sheeba, P.; Thiruvengadam, S. Design of downlink PDSCH architecture for LTE using FPGA. In Proceedings of the International Conference on Recent Trends in Information Technology, ICRTIT 2011, Chennai, India, 3–5 June 2011. doi:10.1109/ICRTIT.2011.5972424. 248. Abbas, S.S.A.; Thiruvengadam, S.J.; Punitha, M. Realization of PDSCH Transmitter and Receiver Architecture for 3GPP-LTE Advanced. In Proceedings of the IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), Dept Elect & Commun Engn, Chennai, India, 23–25 March 2016. 249. Syed, A.A.S.; Geethu, K.; Thiruvengadam, S. Implementation of Physical Downlink Control Channel (PDCCH) for LTE using FPGA. In Proceedings of the 2012 International Conference on Devices, Circuits and Systems, ICDCS 2012, Coimbatore, India, 15–16 March 2012. doi:10.1109/ICDCSyst.2012.6188732. 250. Chen, F.; Zheng, W.; Lv, N. FPGA implementation of PDCCH blind detection algorithm in TD-LTE. In Proceedings of the 2014 International Conference on Materials Science and Computational Engineering, ICMSCE 2014, Qingdao, China, 20 –21 May 2014. doi:10.4028/www.scientific.net/AMR.926-930.3616. 251. Adiono, T.; Mareta, R. Low Latency Parallel-Pipelined Configurable FFT-IFFT 128/256/512/1024/2048 for LTE. In Proceedings of the 4th International Conference on Intelligent and Advanced Systems (ICIAS) and A Conference of World Engineering, Science and Technology Congress (ESTCON), Kuala Lumpur, Malaysia, 12–14 June 2012. 252. Nash, J.G. Distributed-Memory-Based FFT Architecture and FPGA Implementations. Electronics 2018, 7. doi:10.3390/electronics7070116. 253. Ayhan, T.; Dehaene, W.; Verhelst, M. A 128 similar to 2048/1536 point fft hardware implementation with output pruning. In Proceedings of the 22nd European Signal Processing Conference (EUSIPCO), Lisbon, Portugal, 1–5 September 2014. 254. Tran, M.T.; Casseau, E.; Gautier, M. Demo abstract: FPGA-based implementation of a flexible FFT dedicated to LTE standard. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Rennes, France, 12–14 October 2016. 255. Jiang, W.; Prasanna, V.K. Scalable Packet Classification on FPGA. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2012, 20, 1668–1680. doi:10.1109/TVLSI.2011.2162112. 256. Fong, J.; Wang, X.; Qi, Y.; Li, J.; Jiang, W. ParaSplit: A scalable architecture on FPGA for Terabit packet classification. In Proceedings of the 2012 IEEE 20th Annual Symposium on High-Performance Interconnects, HOTI 2012, Santa Clara, CA, USA, 22–24 August 2012. doi:10.1109/HOTI.2012.17. Computation 2019, xx, 5 39 of 115 257. Qi, Y.; Fong, J.; Jiang, W.; Xu, B.; Li, J.; Prasanna, V. Multi-dimensional packet classification on FPGA: 100 Gbps and beyond. In Proceedings of the 2010 International Conference on Field-Programmable Technology, FPT’10, Beijing, China, 8–10 December 2010. doi:10.1109/FPT.2010.5681492. 258. Qu, Y.R.; Prasanna, V.K. High-Performance and Dynamically Updatable Packet Classification Engine on FPGA. IEEE Trans. Parallel Distrib. Syst. 2016, 27, 197–209. doi:10.1109/TPDS.2015.2389239. 259. Jiang, W.; Prasanna, V.K. A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification. In Proceedings of the 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Boston, MA, USA, 7–9 July 2009. doi:10.1109/ASAP.2009.17. 260. Fiesslert, A.; Hager, S.; Scheuermannt, B.; Moore, A.W. HyPaFilter - A Versatile Hybrid FPGA Packet Filter. In Proceedings of the 12th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), Santa Clara, CA, USA, 17–18 March 2016. doi:10.1145/2881025.2881033. 261. Fiessler, A.; Lorenz, C.; Hager, S.; Scheuermann, B.; Moore, A. HyPaFilter: Enhanced Hybrid Packet Filtering Using Hardware Assisted Classification and Header Space Analysis. IEEE/ACM Trans. Netw. 2017, 25, 3655–3669. doi:10.1109/TNET.2017.2749699. 262. Antichi, G.; Di Pietro, A.; Giordano, S.; Procissi, G.; Ficara, D. Design and Development of an OpenFlow Compliant Smart Gigabit Switch. In Proceedings of the 54th Annual IEEE Global Telecommunications Conference (GLOBECOM), Houston, TX, USA, 5–9 December 2011. 263. Farahani, S. ZigBee Wireless Networks and Transceivers; Elsevier Science, 2011. 264. Deep, V.; Elarabi, T. Efficient IEEE 802.15.4 ZigBee standard hardware design for IoT applications. In Proceedings of the 1st IEEE International Conference on Signals and Systems, ICSigSys 2017, Sanur, Indonesia, 16–18 May 2017. doi:10.1109/ICSIGSYS.2017.7967053. 265. Supare, V.P.; Sayankar, B.B.; Agrawal, P. Design & Implementation of MQAM based IEEE 802.15.4/ZigBee Tranceiver using HDL. In Proceedings of the International Conference on Smart Technologies and Management for Computing, Communication, Controls, Energy and Materials (ICSTM), Chennai, India, 6–8 May 2015. 266. Li, S.; Li, W.; Zhu, J. A novel zigbee based high speed ad hoc communication network. In Proceedings of the IEEE International Conference on Network Infrastructure and Digital Content, Beijing, China, 6–8 November 2009. 267. Ahmad, R.; Sidek, O.; Kunhi, M.S. Implementation of a Verilog-based digital receiver for 2.4 GHZ Zigbee applications on FPGA. J. Eng. Sci. Technol. 2014, 9, 135–152. 268. Mohana, P.; Radha, S. Realization of MAC Layer Functions of ZigBee Protocol Stack in FPGA. In Proceedings of the International Conference on Control, Automation, Communication and Energy Conservation, Kongu Engn Coll, Perundurai, India, 4–6 June 2009. 269. Ottoy, G.; Hamelinckx, T.; Preneel, B.; De, S.L.; Goemaere, J.P. AES data encryption in a ZigBee network: Software or hardware? In Proceedings of the 2nd International ICST Conference on Security and Privacy in Mobile Information and Communication Systems, MobiSec 2010, Catania, Italy, 27–28 May 2010. doi:10.1007/978-3-642-17502-2_14. 270. Ottoy, G.; Hamelinckx, T.; Preneel, B.; De Strycker, L.; Goemaere, J.P. On the choice of the appropriate AES data encryption method for ZigBee nodes. Secur. Commun. Netw. 2016, 9, 87–93. doi:10.1002/sec.267. 271. Ahmad, R.; Kho, D.; Abd Manaf, A.; Ismail, W. Parallel-Pipelined-Memory-Based Blowfish Design with Reduced FPGA Utilization for Secure ZigBee Real-Time Transmission. Wirel. Pers. Commun. 2019, 104, 471–489. doi:10.1007/s11277-018-6031-8. 272. Asif, S. 5G Mobile Communications: Concepts and Technologies; CRC Press, 2018. 273. Andrews, J.; Ghosh, A.; Muhamed, R. Fundamentals of WiMAX: Understanding Broadband Wireless Networking; Prentice Hall Press: Upper Saddle River, NJ, USA, 2011. 274. Abba, S.; Khan, W.A.; Khan, T.A.; Ahmed, S. Implementation of OFDM Baseband Transmitter Compliant IEEE Std 802.16d on FPGA. In Proceedings of the 2nd International Conference on Communication Software and Networks, Singapore, Singapore, 26–28 Feburary 2010. doi:10.1109/ICCSN.2010.83. 275. Hadiyoso, S.; Astuti, R.P.; Hidayat, I. Design of an FPGA-Based OFDM-STBC Transceiver for WiMAX 802.16e Standard. In Proceedings of the 2nd International Conference on Information and Communication Technology (ICoICT), Bandung, Indonesia, 28–30 May 2014. Computation 2019, xx, 5 40 of 115 276. Ahn, C.; Kim, J.; Ju, J.; Choi, J.; Choi, B.; Choi, S. Implementation of an SDR platform using GPU and its application to a 2 x 2 MIMO WiMAX system. Analog. Integr. Circuits Signal Process. 2011, 69, 107–117. doi:10.1007/s10470-011-9764-9. 277. Suarez-Casal, P.; Carro-Lagoa, A.; Garcia-Naya, J.A.; Castedo, L. A Multicore SDR Architecture for Reconfigurable WiMAX Downlink. In Proceedings of the 13th Euromicro Conference on Digital System Design on Architectures, Methods and Tools, Lille, France, 1–3 September 2010. doi:10.1109/DSD.2010.108. 278. Suarez-Casal, P.; Carro-Lagoa, A.; Garcia-Naya, J.A.; Fraga-Lamas, P.; Castedo, L.; Morales-Mendez, A. A Real-Time Implementation of the Mobile WiMAX ARQ and Physical Layer. J. Signal Process. Syst. Signal Image Video Technol. 2015, 78, 283–297. doi:10.1007/s11265-014-0890-3. 279. Shaker, S.; Elramly, S.; Shehata, K. FPGA implementation of a reconfigurable Viterbi decoder for WiMAX receiver. In Proceedings of the 21th International Conference on Microelectronics, ICM 2009, Marrakech, Morocco, 19–22 December 2009. doi:10.1109/ICM.2009.5418636. 280. Nandula, S.; Rao, Y.S.; Embanath, S.P. High speed area efficient configurable Viterbi decoder for WiFi and WiMAX systems. In Proceedings of the International Conference on Intelligent and Advanced Systems, Kuala Lumpur, Malaysia, 25–28 November 2007. 281. Junjie, L.; June, T.; Yingning, P.; Jianwen, C. High Performance Viterbi Decoder on Cell/BE. China Commun. 2009, 6, 150–156. 282. Benzekki, K.; El Fergougui, A.; Elbelrhiti Elalaoui, A. Software-defined networking (SDN): a survey. Secur. Commun. Netw. 2016, 9, 5803–5833. doi:10.1002/sec.1737. 283. Lockwood, J.W.; Monga, M. Implementing ultra-low-latency datacenter services with programmable logic. In Proceedings of the 2015 IEEE 23rd Annual Symposium on High-Performance Interconnects, Santa Clara, CA, USA, 26–28 August 2015. 284. Zhao, T.; Li, T.; Han, B.; Sun, Z.; Huang, J. Design and implementation of Software Defined Hardware Counters for SDN. Comput. Netw. 2016, 102, 129–144. doi:10.1016/j.comnet.2016.03.004. 285. Antichi, G.; Rotsos, C.; Moore, A. Enabling performance evaluation beyond 10 Gbps. In Proceedings of the ACM Conference on Special Interest Group on Data Communication, SIGCOMM 2015, New York, NY, USA, 17–21 August 2015. doi:10.1145/2785956.2790036. 286. Pacifico, R.; Goulart, P.; Vieira, A.; Vieira, M.; Nacif, J. Hardware Modules for Packet Interarrival Time Monitoring for Software Defined Measurements. In Proceedings of the 41st IEEE Conference on Local Computer Networks, LCN 2016, Dubai, United Arab Emirates, 7–10 November 2016. doi:10.1109/LCN.2016.39. 287. Van, T.N.; Bao, H.; Thinh, T. An anomaly-based intrusion detection architecture integrated on openflow switch. In Proceedings of the 6th International Conference on Communication and Network Security, ICCNS 2016, New York, NY, USA, 12–14 November 2016. doi:10.1145/3017971.3017982. 288. Arap, O.; Brown, G.; Himebaugh, B.; Swany, M. Software Defined Multicasting for MPI Collective Operation Offloading with the NetFPGA. In Proceedings of the 20th International Euro-Par Conference on Parallel Processing (Euro-Par), Porto, Portugal, 25–29 August 2014. 289. Rotsos, C.; Antichi, G.; Bruyere, M.; Owezarski, P.; Moore, A. An open testing framework for next-generation openflow switches. In Proceedings of the 3rd European Workshop on Software-Defined Networks, EWSDN 2014, Washington, DC, USA, 1–3 September 2014. doi:10.1109/EWSDN.2014.12. 290. Park, T.; Xu, Z.; Shin, S. HEX switch: Hardware-assisted security extensions of OpenFlow. In Proceedings of the 1st Workshop on Security in Softwarized Networks: Prospects and Challenges, Budapest, Hungary, 20–24 August 2018. doi:10.1145/3229616.3229622. 291. Paolucci, F.; Civerchia, F.; Sgambelluri, A.; Giorgetti, A.; Cugini, F.; Castoldi, P. P4 Edge Node Enabling Stateful Traffic Engineering and Cyber Security. J. Opt. Commun. Netw. 2019, 11, A84–A95. doi:10.1364/JOCN.11.000A84. 292. Yu, Y.; Liang, M.; Wang, Z. Research on data center network data plane model based on vector address. Sichuan Daxue Xuebao (Gongcheng Kexue Ban)/J. Sichuan Univ. (Engineering Sci. Ed. 2016, 48, 129–135. doi:10.15961/j.jsuese.2016.04.018. 293. Duan, T.; Lan, J.; Hu, Y.; Sun, P. Separating VNF and network control for hardware-acceleration of SDN/NFV architecture. ETRI J. 2017, 39, 525–534. doi:10.4218/etrij.17.0117.0174. Computation 2019, xx, 5 41 of 115 294. Vieira, J.; Malkowsky, S.; Nieman, K.; Miers, Z.; Kundargi, N.; Liu, L.; Wong, I.; Owall, V.; Edfors, O.; Tufvesson, F. A flexible 100-antenna testbed for Massive MIMO; IEEE: 7, 2014; pp. 287–293. In Proceedings of the IEEE Global Communications Conference (GLOBECOM), Austin, TX, USA, 8–12 December 2014. 295. Malkowsky, S.; Vieira, J.; Liu, L.; Harris, P.; Nieman, K.; Kundargi, N.; Wong, I.C.; Tufvesson, F.; Owall, V.; Edfors, O. The World’s First Real-Time Testbed for Massive MIMO: Design, Implementation, and Validation. IEEE Access 2017, 5, 9073–9088. doi:10.1109/ACCESS.2017.2705561. 296. Nadal, J.; Nour, C.A.; Baghdadi, A. Low-Complexity Pipelined Architecture for FBMC/OQAM Transmitter. IEEE Trans. Circuits Syst. -Express Briefs 2016, 63, 19–23. doi:10.1109/TCSII.2015.2468926. 297. Danneberg, M.; Michailow, N.; Gaspar, I.; Matthe, M.; Zhang, D.; Mendes, L.L.; Fettweis, G. Implementation of a 2 by 2 MIMO-GFDM Transceiver for Robust 5G Networks. In Proceedings of the 12th International Symposium on Wireless Communication Systems (ISWCS), Brussels, Belgium, 25–28 August 2015. 298. Ferreira, M.; Ferreira, J.; Huebner, M. A parallel-pipelined OFDM baseband modulator with dynamic frequency scaling for 5G systems. In Proceedings of the 14th International Symposium on Applied Reconfigurable Computing, ARC 2018, Santorini, Greece, 2–4 May 2018. doi:10.1007/978-3-319-78890-6_41. 299. Medjkouh, S.; Nadal, J.; Nour, C.A.; Baghdadi, A. Reduced Complexity FPGA Implementation for UF-OFDM Frequency Domain Transmitter. In Proceedings of the IEEE International Workshop on Signal Processing Systems (SiPS), Lorient, France, 3–5 October 2017. 300. Haggui, H.; Bellili, F.; Affes, S. FPGA Prototyping of a STAR-Based Time-Delay Estimator for 5G Radio Access. In Proceedings of the IEEE 28th Annual International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC), Montreal, QC, Canada, 8–13 October 2017. 301. Chitimalla, D.; Kondepu, K.; Valcarenghi, L.; Tornatore, M.; Mukherjee, B. 5G Fronthaul-Latency and Jitter Studies of CPRI Over Ethernet. J. Opt. Commun. Netw. 2017, 9, 172–182. doi:10.1364/JOCN.9.000172. 302. Haroun, M.H.; Cabedo-Fabres, M.; Ayad, H.; Jomaah, J.; Ferrando-Bataller, M. Direction of Arrival Estimation for LTE-Advanced and 5G in the Uplink. In Proceedings of the IEEE Middle East and North Africa Communications Conference (MENACOMM), Jounieh, Lebanon, 18–20 April 2018. 303. Schatz, D.; Bashroush, R.; Wall, J. Towards a more representative definition of cyber security. J. Digit. Forensics, Secur. Law 2017, 12, 8. doi:10.15394/jdfsl.2017.1476. 304. Lee, P.; Anderson, T. Fault Tolerance: Principles and Practice; Dependable Computing and Fault-Tolerant Systems; Springer: Vienna, Austria, 2012. 305. Perez, A.; Suriano, L.; Otero, A.; de la Torre, E. Dynamic Reconfiguration under RTEMS for Fault Mitigation and Functional Adaptation in SRAM-based SoPCs for Space Systems. In Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS), California Inst Technol, Pasadena, CA, USA, 24–27 July 2017. 306. Perez Celis, J.A.; de la Rosa Nieves, S.; Romo Fuentes, C.; Santillan Gutierrez, S.D.; Saenz-Otero, A. Methodology for designing highly reliable Fault Tolerance Space Systems based on COTS devices; IEEE: 4, 2013; pp. 591–594. In Proceedings of the 7th Annual IEEE International Systems Conference (SysCon), Orlando, FL, USA, 15–18 April 2013. 307. Andres Perez-Celis, J.; Ferrer-Perez, J.A.; Santillan-Gutierrez, S.D.; de la Rosa Nieves, S. Simulation of Fault-Tolerant Space Systems Based on COTS Devices With GPSS. IEEE Syst. J. 2016, 10, 53–58. doi:10.1109/JSYST.2014.2338212. 308. van Harten, L.; Jordans, R.; Pourshaghaghi, H. Necessity of Fault Tolerance Techniques in Xilinx Kintex 7 FPGA Devices for Space Missions: A Case Study. In Proceedings of the 20th Euromicro Conference on Digital System Design (DSD), Vienna, Austria, 30 August–1 September 2017. doi:10.1109/DSD.2017.45. 309. van Harten, L.D.; Mousavi, M.; Jordans, R.; Pourshaghaghi, H.R. Determining the necessity of fault tolerance techniques in FPGA devices for space missions. Microprocess. Microsystems 2018, 63, 1–10. doi:10.1016/j.micpro.2018.08.001. 310. Frenkel, C.; Legat, J.D.; Bol, D. A Partial Reconfiguration-Based Scheme to Mitigate Multiple-Bit Upsets for FPGAs in Low-Cost Space Applications. In Proceedings of the 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Bremen, Germany, 29 June–1 July 2015. 311. Paulsson, K.; Huebner, M.; Jung, M.; Becker, J. Methods for run-time failure recognition and recovery in dynamic and partial reconfigurable systems based on xilinx Virtex-II pro FPGAs. In Proceedings of the IEEE-Computer-Society Annual Symposium on VLSI, Karlsruhe, Germany, 2–3 March 2006. Computation 2019, xx, 5 42 of 115 312. Paulsson, K.; Huebner, M.; Becker, J. Strategies to on-line failure recovery in self-adaptive systems based on dynamic and partial reconfiguration. In Proceedings of the 1st NASA/ESA Conference on Adaptive Hardware and Systems, Bahcesehir Univ, Istanbul, Turkey, 15–18 June 2006. 313. Podivinsky, J.; Lojda, J.; Cekan, O.; Kotasek, Z. Evaluation platform for testing fault tolerance properties: Soft-core processor-based experimental robot controller. In Proceedings of the 21st Euromicro Conference on Digital System Design, Prague, Czech Republic, 29–31 August 2018. doi:10.1109/DSD.2018.00051. 314. Podivinsky, J.; Lojda, J.; Cekan, O.; Panek, R.; Kotasek, Z. Reliability Analysis and Improvement of FPGA-based Robot Controller. In Proceedings of the 20th Euromicro Conference on Digital System Design (DSD), Vienna, Austria, 30 August–1 September 2017. doi:10.1109/DSD.2017.15. 315. Perez, R. Handbook of Aerospace Electromagnetic Compatibility; Wiley, 2018. 316. Sterpone, L.; Violante, M. Hardening FPGA-based systems against SEUs: A new design methodology. J. Comput. 2006, 1, 22–30. doi:10.4304/jcp.1.1.22-30. 317. Reddy, E.; Chandrasekhar, V.; Sashikanth, M.; Kamakoti, V.; Vijaykrishnan, N. Detecting SEU-caused routing errors in SRAM-based FPGAs. In Proceedings of the 18th International Conference on VLSI Design/4th International Conference on Embedded Systems Design, Calcutta, India, 3–7 January 2005. doi:10.1109/ICVD.2005.79. 318. Ferlini, F.; Da, S.F.; Bezerra, E.; Lettnin, D. Non-intrusive fault tolerance in soft processors through circuit duplication. In Proceedings of the 13th IEEE Latin American Test Workshop, LATW 2012, Quito, Ecuador, 10–13 April 2012. doi:10.1109/LATW.2012.6261264. 319. Sterpone, L. Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs. In Proceedings of the 5th International Workshop on Applied Reconfigurable Computing, Karlsruhe, Germany, 16–18 March 2009. 320. Lima, F.; Carmichael, C.; Fabula, J.; Padovani, R.; Reis, R. A fault injection analysis of Virtex FPGA TMR design methodology. In Proceedings of the 6th European Conference on Radiation and Its Effects on Components and Systems, Grenoble, France, 10–14 September 2001. doi:10.1109/RADECS.2001.1159293. 321. Sterpone, L.; Violante, M. A new partial reconfiguration-based fault-injection system to evaluate SEU effects in SRAM-Based FPGAs. IEEE Trans. Nucl. Sci. 2007, 54, 965–970. doi:10.1109/TNS.2007.904080. 322. Civera, P.; Macchiarulo, L.; Rebaudengo, M.; Reorda, M.; Violante, M. An FPGA-based approach for speeding-up fault injection campaigns on safety-critical circuits. J. Electron.-Test.-Theory Appl. 2002, 18, 261–271. doi:10.1023/A:1015079004512. 323. Villalta, I.; Bidarte, U.; Gomez-Cornejo, J.; Jimenez, J.; Lazaro, J. SEU emulation in industrial SoCs combining microprocessor and FPGA. Reliab. Eng. Syst. Saf. 2018, 170, 53–63. doi:10.1016/j.ress.2017.09.028. 324. Yang, X.; Yang, C.; Peng, T.; Chen, Z.; Liu, B.; Gui, W. Hardware-in-the-Loop Fault Injection for Traction Control System. IEEE J. Emerg. Sel. Top. Power Electron. 2018, 6, 696–706. doi:10.1109/JESTPE.2018.2794339. 325. Homma, N.; Nagashima, S.; Imai, Y.; Aoki, T.; Satoh, A. High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching. In Cryptographic Hardware and Embedded Systems—CHES 2006; Goubin, L., Matsui, M., Eds.; Springer Berlin Heidelberg: Berlin/Heidelberg, Germany, 2006; pp.187–200. 326. Moradi, A.; Barenghi, A.; Kasper, T.; Paar, C. On the vulnerability of FPGA bitstream encryption against power analysis attacks: Extracting keys from Xilinx Virtex-II FPGAs. In Proceedings of the 18th ACM Conference on Computer and Communications Security, CCS’11, Chicago, IL, USA, 17–21 October 2011, doi:10.1145/2046707.2046722. 327. Standaert, F.; Peeters, E.; Rouvroy, G.; Quisquater, J. An overview of power analysis attacks against field programmable gate arrays. Proc. IEEE 2006, 94, 383–394. doi:10.1109/JPROC.2005.862437. 328. Masoumi, M. Differential power analysis: A serious threat for FPGA security. Int. J. Internet Technol. Secur. Trans. 2012, 4, 12–25. doi:10.1504/IJITST.2012.045161. 329. Ghosh, S.; Mukhopadhyay, D.; Roychowdhury, D. Petrel: Power and Timing Attack Resistant Elliptic Curve Scalar Multiplier Based on Programmable GF(p) Arithmetic Unit. IEEE Trans. Circuits Syst. -Regul. Pap. 2011, 58, 1798–1812. doi:10.1109/TCSI.2010.2103190. 330. Bayrak, A.G.; Velickovic, N.; Ienne, P.; Burleson, W. An Architecture-Independent Instruction Shuffler to Protect against Side-Channel Attacks. ACM Trans. Archit. Code Optim. 2012, 8. doi:10.1145/2086696.2086699. 331. Sasdrich, P.; Gueneysu, T. Implementing Curve25519 for Side-Channel-Protected Elliptic Curve Cryptography. ACM Trans. Archit. Code Optim. 2015, 9. doi:10.1145/2700834. Computation 2019, xx, 5 43 of 115 332. Chen, Z.; Sinha, A.; Schaumont, P. Using Virtual Secure Circuit to Protect Embedded Software from Side-Channel Attacks. IEEE Trans. Comput. 2013, 62, 124–136. doi:10.1109/TC.2011.225. 333. Bruguier, F.; Benoit, P.; Torres, L.; Barthe, L.; Bourree, M.; Lomne, V. Cost-Effective Design Strategies for Securing Embedded Processors. IEEE Trans. Emerg. Top. Comput. 2016, 4, 60–72. doi:10.1109/TETC.2015.2407832. 334. Bogdanov, A.; Moradi, A.; Yalcin, T. Efficient and Side-Channel Resistant Authenticated Encryption of FPGA Bitstreams. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 5–7 December 2012. 335. Hoque, T.; Narasimhan, S.; Wang, X.; Mal-Sarkar, S.; Bhunia, S. Golden-Free Hardware Trojan Detection with High Sensitivity Under Process Noise. J. Electron.-Test.-Theory Appl. 2017, 33, 107–124. doi:10.1007/s10836-016-5632-y. 336. Wang, S.; Dong, X.; Sun, K.; Cui, Q.; Li, D.; He, C. Hardware Trojan Detection Based on ELM Neural Network. In Proceedings of the 1st IEEE International Conference on Computer Communication and the Internet (ICCCI), Wuhan, China, 13–15 October 2016. 337. Zhao, Y.; Liu, A.; He, J.; Liu, Y. Hardware Trojan detection technology based on factor analysis under process variation. Huazhong Keji Daxue Xuebao (Ziran Kexue Ban)/J. Huazhong Univ. Sci. Technol. (Nat. Sci. Ed.) 2018, 46, 7–11. doi:10.13245/j.hust.180302. 338. Wachsmann, C.; Sadeghi, A. Physically Unclonable Functions (PUFs): Applications, Models, and Future Directions; Synthesis Lectures on Information Security, Privacy, and Trust, Morgan & Claypool Publishers, 2014. 339. Maiti, A.; Schaumont, P. Improved Ring Oscillator PUF: An FPGA-friendly Secure Primitive. J. Cryptol. 2011, 24, 375–397. doi:10.1007/s00145-010-9088-4. 340. Eiroa, S.; Baturone, I. An analysis of ring oscillator PUF behavior on FPGAs. In Proceedings of the 2011 International Conference on Field-Programmable Technology, FPT 2011, New Delhi, India, 12–14 December 2011. doi:10.1109/FPT.2011.6132673. 341. Kodytek, F.; Lorencz, R. A Design of Ring Oscillator Based PUF on FPGA. In Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Belgrade, Serbia, 22–24 April 2015. doi:10.1109/DDECS.2015.21. 342. Kodytek, F.; Lorencz, R.; Bucek, J. Improved ring oscillator PUF on FPGA and its properties. Microprocess. Microsyst. 2016, 47, 55–63. doi:10.1016/j.micpro.2016.02.005. 343. Lee, S.; Oh, M.K.; Kang, Y.; Choi, D. Implementing a phase detection ring oscillator PUF on FPGA. In Proceedings of the 9th International Conference on Information and Communication Technology Convergence, ICTC 2018, 17–19 October 2018. doi:10.1109/ICTC.2018.8539624. 344. Hussain, S.U.; Yellapantula, S.; Majzoobi, M.; Koushanfar, F. BIST-PUF: Online, Hardware-based Evaluation of Physically Unclonable Circuit Identifiers. In Proceedings of the 33rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, 2–6 November 2014. 345. Komurcu, G.; Dundar, G. Determining the Quality Metrics for PUFs and Performance Evaluation of Two RO-PUFs. In Proceedings of the 10th IEEE International New Circuits and Systems Conference (NEWCAS), Montreal, QC, Canada, 17–20 November 2012. 346. Hussain, S.U.; Majzoobi, M.; Koushanfar, F. A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators. IEEE Trans.-Multi-Scale Comput. Syst. 2016, 2, 2–16. doi:10.1109/TMSCS.2016.2519902. 347. Cherif, Z.; Danger, J.L.; Lozac’h, F.; Mathieu, Y.; Bossuet, L. Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA. In Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy, HASP 2013, Tel-Aviv, Israel, 23 –24 June 2013. 348. Lyons, R.E.; Vanderkulk, W. The Use of Triple-Modular Redundancy to Improve Computer Reliability. IBM J. Res. Dev. 1962, 6, 200–209. doi:10.1147/rd.62.0200. 349. Morgan, K.S.; McMurtrey, D.L.; Pratt, B.H.; Wirthlin, M.J. A comparison of TMR with alternative fault-tolerant design techniques for FPGAs. IEEE Trans. Nucl. Sci. 2007, 54, 2065–2072. doi:10.1109/TNS.2007.910871. 350. Manuzzato, A.; Gerardin, S.; Paccagnella, A.; Sterpone, L.; Violante, M. Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs. In Proceedings of the 9th European Conference on Radiation and Its Effects on Components and Systems, Deauville, France, 10–14 September 2007. Computation 2019, xx, 5 44 of 115 351. Alkady, G.I.; AbdelKader, A.; Daoud, R.M.; Amer, H.H.; El-Araby, N.A.; Abdelhalim, M.B. Integration of Multiple Fault-Tolerant Techniques for FPGA-Based NCS Nodes. In Proceedings of the 11th International Conference on Computer Engineering and Systems (ICCES), Cairo, Egypt, 21–22 December 2016. 352. Anjankar, S.C.; Kolte, M.T.; Pund, A.; Kolte, P.; Kumar, A.; Mankar, P.; Ambhore, K. FPGA Based Multiple Fault Tolerant and Recoverable Technique Using Triple Modular Redundancy (FRTMR). In Proceedings of the 7th International Conference on Communication, Computing and Virtualization (ICCCV), Mumbai, India, 26–27 Feburary 2016. doi:10.1016/j.procs.2016.03.109. 353. Foucard, G.; Peronnard, P.; Velazco, R. Reliability Limits of TMR Implemented in a SRAM-based FPGA: Heavy Ion Measures vs. Fault Injection Predictions. J. Electron.-Test.-Theory Appl. 2011, 27, 627–633. doi:10.1007/s10836-011-5245-4. 354. Anjankar, S.; Pund, A.; Junghare, R.; Zalke, J. Real-time FPGA-based fault tolerant and recoverable technique for arithmetic design using functional triple modular redundancy (FRTMR). In Proceedings of the 2nd International Conference on Computational Intelligence and Informatics, ICCII 2017, Telangana, India, 25–27 September 2017. doi:10.1007/978-981-10-8228-3_45. 355. Sterpone, L.; Boragno, L. Analysis of Radiation-induced Cross Domain Errors in TMR Architectures on SRAM-based FPGAs. In Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), Thessaloniki, Greece, 3–5 July 2017. 356. Abramowicz, H.; Abusleme, A.; Afanaciev, K.; Aguilar, J.; Alvarez, E.; Avila, D.; Benhammou, Y.; Bortko, L.; Borysov, O.; Bergholz, M.; et al. Performance of fully instrumented detector planes of the forward calorimeter of a Linear Collider detector. J. Instrum. 2015, 10. doi:10.1088/1748-0221/10/05/P05009. 357. Pastika, N.J. Performance of the prototype readout system for the CMS endcap hadron calorimeter upgrade. J. Instrum. 2016, 11. doi:10.1088/1748-0221/11/03/C03020. 358. Rost, A.; Galatyuk, T.; Koenig, W.; Michel, J.; Pietraszko, J.; Skott, P.; Traxler, M. A flexible FPGA based QDC and TDC for the HADES and the CBM calorimeters. J. Instrum. 2017, 12. doi:10.1088/1748-0221/12/02/C02047. 359. Arnold, L.; Beaumont, W.; Cussans, D.; Newbold, D.; Ryder, N.; Weber, A. The SoLid anti- neutrino detector’s readout system. J. Instrum. 2017, 12. doi:10.1088/1748-0221/12/02/C02012. 360. Calvo, D.; Real, D. High resolution time to digital converter for the KM3NeT neutrino telescope. J. Instrum. 2015, 10. doi:10.1088/1748-0221/10/01/C01015. 361. Visser, J.; van Beuzekom, M.; Boterenbrood, H.; van der Heijden, B.; Munoz, J.I.; Kulis, S.; Munneke, B.; Schreuder, F. SPIDR: a read-out system for Medipix3 & Timepix3. J. Instrum. 2015, 10. doi:10.1088/1748-0221/10/12/C12028. 362. Cachemiche, J.P.; Duval, P.Y.; Hachon, F.; Le Gac, R.; Marin, F. Study for the LHCb upgrade read-out board. J. Instrum. 2010, 5. doi:10.1088/1748-0221/5/12/C12036. 363. Kolotouros, D.M.; Baron, S.; Soos, C.; Vasey, F. A TTC upgrade proposal using bidirectional 10G-PON FTTH technology. J. Instrum. 2015, 10. doi:10.1088/1748-0221/10/04/C04001. 364. Deng, B.; He, M.; Chen, J.; Guo, D.; Hou, S.; Li, X.; Liu, C.; Teng, P.K.; Xiang, A.C.; You, Y.; Ye, J.; Gong, D.; Liu, T. A line code with quick-resynchronization capability and low latency for the optical data links of LHC experiments. J. Instrum. 2014, 9. doi:10.1088/1748-0221/9/07/P07020. 365. Muschter, S.; Aakerstedt, H.; Anderson, K.; Bohm, C.; Oreglia, M.; Tang, F. Development of a digital readout board for the ATLAS Tile Calorimeter upgrade demonstrator. J. Instrum. 2014, 9. doi:10.1088/1748-0221/9/01/C01001. 366. Mozaffari-Kermani, M.; Reyhani-Masoleh, A. A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2011, 19, 85–91. doi:10.1109/TVLSI.2009.2031651. 367. Jiang, J.A.; Chuang, C.L.; Wang, Y.C.; Hung, C.H.; Wang, J.Y.; Lee, C.H.; Hsiao, Y.T. A Hybrid Framework for Fault Detection, Classification, and Location-Part I: Concept, Structure, and Methodology. IEEE Trans. Power Deliv. 2011, 26, 1988–1998. doi:10.1109/TPWRD.2011.2141157. 368. Shahbazi, M.; Poure, P.; Saadate, S.; Zolghadri, M.R. FPGA-Based Fast Detection With Reduced Sensor Count for a Fault-Tolerant Three-Phase Converter. IEEE Trans. Ind. Informatics 2013, 9, 1343–1350. doi:10.1109/TII.2012.2209665. Computation 2019, xx, 5 45 of 115 369. Druant, J.; Vyncke, T.; De Belie, F.; Sergeant, P.; Melkebeek, J. Adding Inverter Fault Detection to Model-Based Predictive Control for Flying-Capacitor Inverters. IEEE Trans. Ind. Electron. 2015, 62, 2054–2063. doi:10.1109/TIE.2014.2354591. 370. Bajard, J.C.; Eynard, J.; Gandino, F. Fault Detection in RNS Montgomery Modular Multiplication; IEEE: 8, 2013; pp. 119–126. In Proceedings of the 21st IEEE Symposium on Computer Arithmetic (ARITH), Austin, TX, USA, 7–10 April 2013. doi:10.1109/ARITH.2013.31. 371. Shahbazi, M.; Zolghadri, M.; Poure, P.; Saadate, S. Fast detection of open-switch faults with reduced sensor count for a fault-tolerant three-phase converter. In Proceedings of the 2011 2nd Power Electronics, Drive Systems and Technologies Conference, PEDSTC 2011, Tehran, Iran, 16–17 February 2011, doi:10.1109/PEDSTC.2011.5742479. 372. Chine, W.; Mellit, A.; Lughi, V.; Malek, A.; Sulligoi, G.; Pavan, A.M. A novel fault diagnosis technique for photovoltaic systems based on artificial Neural Netw.. Renew. Energy 2016, 90, 501–512. doi:10.1016/j.renene.2016.01.036. 373. Shahbazi, M.; Jamshidpour, E.; Poure, P.; Saadate, S.; Zolghadri, M.R. Open- and Short-Circuit Switch Fault Diagnosis for Nonisolated DC-DC Converters Using Field Programmable Gate Array. IEEE Trans. Ind. Electron. 2013, 60, 4136–4146. doi:10.1109/TIE.2012.2224078. 374. Abramovici, M.; Stroud, C.; Emmert, J. Online BIST and BIST-based diagnosis of FPGA logic blocks. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2004, 12, 1284–1294. doi:10.1109/TVLSI.2004.837989. 375. Tahoori, M.B. High Resolution Application Specific Fault Diagnosis of FPGAs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2011, 19, 1775–1786. doi:10.1109/TVLSI.2010.2056941. 376. Aghaie, A.; Kermani, M.M.; Azarderakhsh, R. Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2017, 25, 1528–1536. doi:10.1109/TVLSI.2016.2633412. 377. Chine, W.; Mellit, A.; Bouhedir, R. FPGA-Based Implementation of an Intelligent Fault Diagnosis Method for Photovoltaic Arrays. Artif. Intell. Renew. Energetic Syst. Smart Sustain. Energy Syst. 2018, 35, 245–252. doi:10.1007/978-3-319-73192-6_25. 378. Jiang, N.; Peng, K.; Song, J.; Pan, C.; Yang, Z. High-Throughput QC-LDPC Decoders. IEEE Trans. Broadcast. 2009, 55, 251–259. doi:10.1109/TBC.2008.2012359. 379. Park, J.W.; Sunwoo, M.H.; Kim, P.S.; Chang, D.I. Low Complexity Soft-Decision Demapper for High Order Modulation of DVB-S2 system. In Proceedings of the International SoC Design Conference 2008, Busan, Korea, 24–25 November 2008. 380. Gao, B.; Xiao, Z.; Zhang, C.; Su, L.; Jin, D.; Zeng, L. Performance comparison of channel coding for 60GHz SC-PHY and a multigigabit Viterbi decoder. In Proceedings of the 2011 International Conference on Computational Problem-Solving, ICCP 2011, Chengdu, China, 21–23 October 2011. doi:10.1109/ICCPS.2011.6092169. 381. Zhao, H.; Zhang, H. Design and FPGA Implementation of a Quasi-Cyclic LDPC Decoder. In Proceedings of the 6th International Conference on Communications, Signal Processing, and Systems (ICCSPS), Tianjin Normal Univ, Harbin, China, 14–16 July 2017. doi:10.1007/978-981-10-6571-2_222. 382. Zhong, H.; Zhong, T.; Haratsch, E.F. Quasi-cyclic LDPC codes for the magnetic recording channel: Code design and VLSI implementation. IEEE Trans. Magn. 2007, 43, 1118–1123. doi:10.1109/TMAG.2006.888607. 383. Sun, L.; Song, H.; Keirn, Z.; Kumar, B. Field programmable gate array (FPGA) for iterative code evaluation. IEEE Trans. Magn. 2006, 42, 226–231. doi:10.1109/TMAG.2005.861744. 384. Bala, G.P.; Hari, K.K.; Kalyana, V.R.; Harinath, M.P. An FPGA implementation of onchip UART testing with BIST techniques. Int. J. Appl. Eng. Res. 2015, 10, 34047–34051. 385. Charan, N.; Kishore, K. Recognization of delay faults in cluster based FPGA using BIST. Indian J. Sci. Technol. 2016, 9. doi:10.17485/ijst/2016/v9i28/92389. 386. Girard, P.; Heron, O.; Pravossoudovitch, S.; Renovell, M. An efficient BIST architecture for delay faults in the logic cells of symmetrical SRAM-based FPGAs. J. Electron.-Test.-Theory Appl. 2006, 22, 161–172. doi:10.1007/s10836-005-4631-1. 387. Pundir, A.; Sharma, O. Fault tolerant reconfigurable hardware design using BIST on SRAM: A review. In Proceedings of the 2017 International Conference on Intelligent Computing and Control, I2C2 2017, Coimbatore, India, 23–24 June 2017. doi:10.1109/I2C2.2017.8321907. Computation 2019, xx, 5 46 of 115 388. Panwar, A.; Kumar, S.; Singh, J. FPGA based design of hierarchical self-Test for surveillance system. In Proceedings of the 2nd IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2017, Bangalore, India, 19–20 May 2017. doi:10.1109/RTEICT.2017.8256627. 389. Glabb, R.; Imbert, L.; Jullien, G.; Tisserand, A.; Veyrat-Charvillon, N. Multi-mode operator for SHA-2 hash functions. J. Syst. Archit. 2007, 53, 127–138. doi:10.1016/j.sysarc.2006.09.006. 390. Knezevic, M.; Kobayashi, K.; Ikegami, J.; Matsuo, S.; Satoh, A.; Kocabas, U.; Fan, J.; Katashita, T.; Sugawara, T.; Sakiyama, K.; Verbauwhede, I.; Ohta, K.; Homma, N.; Aoki, T. Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2012, 20, 827–840. doi:10.1109/TVLSI.2011.2128353. 391. Kakarountas, A.P.; Michail, H.; Milidonis, A.; Goutis, C.E.; Theodoridis, G. High-speed FPGA implementation of secure hash algorithm for IPSec and VPN applications. J. Supercomput. 2006, 37, 179–195. doi:10.1007/s11227-006-5682-5. 392. Algredo-Badillo, I.; Feregrino-Uribe, C.; Cumplido, R.; Morales-Sandoval, M. FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256. Microprocess. Microsyst. 2013, 37, 750–757. doi:10.1016/j.micpro.2012.06.007. 393. Kim, J.W.; Lee, H.U.; Won, Y. Design for high throughput SHA-1 hash function on FPGA. In Proceedings of the 4th International Conference on Ubiquitous and Future Networks, ICUFN 2012, Phuket, Thailand, 4 –6 July 2012. doi:10.1109/ICUFN.2012.6261737. 394. El, M.S.; Fettach, M.; Tragha, A. High frequency implementation of cryptographic hash function Keccak-512 on FPGA devices. Int. J. Inf. Comput. Secur. 2018, 10, 361–373. doi:10.1504/IJICS.2018.095299. 395. Anand, P.A.; Bajarangbali, D. Design of High Speed CRC Algorithm for Ethernet on FPGA Using Reduced Lookup Table Algorithm. In Proceedings of the IEEE Annual India Conference (INDICON), Bangalore, India, 16–18 December 2016. 396. Bi, Z.; Zhang, Y.; Huang, Z.; Wang, Y. Study on CRC parallel algorithm and its implementation in FPGA. Yi Qi Yi Biao Xue Bao/Chin. J. Sci. Instrum. 2007, 28, 2244–2249. 397. Zhang, B. A Parallel CRC Algorithm Based on Symbolic Polynomial; SPRINGER-VERLAG BERLIN: 7, 2012; Vol. 149, pp. 559–565. In Proceedings of the Conference on Electronic Commerce, Web Application and Communication, Wuhan, China, 17–18 March 2012. 398. Buzdar, A.R.; Sun, L.; Kashif, R.; Azhar, M.W.; Khan, M.I. Cyclic Redundancy Checking (CRC) Accelerator for Embedded Processor Datapaths. Int. J. Adv. Comput. Sci. Appl. 2017, 8, 321–325. 399. Weaver, N.; Paxson, V.; Gonzalez, J.M. The Shunt: An FPGA-Based Accelerator for Network Intrusion Prevention. In Proceedings of the 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, 18–20 February 2007. 400. Gonzalez, J.; Paxson, V.; Weaver, N. Shunting: A hardware/software architecture for flexible, high-performance network intrusion prevention. In Proceedings of the 14th ACM Conference on Computer and Communications Security, CCS’07, Alexandria, VA, USA, 29 October–2 November 2007. doi:10.1145/1315245.1315264. 401. Rahmatian, M.; Kooti, H.; Harris, I.; Bozorgzadeh, E. Hardware-assisted detection of malicious software in embedded systems. IEEE Embed. Syst. Lett. 2012, 4, 94–97. doi:10.1109/LES.2012.2218630. 402. Baker, Z.K.; Prasanna, V.K. Automatic synthesis of efficient intrusion detection systems on FPGAs. IEEE Trans. Dependable Secur. Comput. 2006, 3, 289–300. doi:10.1109/TDSC.2006.44. 403. Clark, C.R.; Ulmer, C.D.; Schimmel, D.E. An FPGA-based network intrusion detection system with on-chip network interfaces. Int. J. Electron. 2006, 93, 403–420. doi:10.1080/00207210600566083. 404. Rehak, M.; Pechoucek, M.; Bartos, K.; Grill, M.; Celeda, P.; Krmicek, V. CAMNEP: An intrusion detection system for high-speed networks. Prog. Informatics 2008, pp. 65–74. doi:10.2201/NiiPi.2008.5.7. 405. Katz, J.; Lindell, Y. Introduction to Modern Cryptography, Second Edition; Chapman & Hall/CRC Cryptography and Network Security Series, Taylor & Francis: Abingdon, UK, 2014. 406. Jarvinen, K.; Tommiska, M.; Skytta, J. A fully pipelined memoryless 17.8 Gbps AES-128 encryptor. In Proceedings of the ACM/SIGDA 11th ACM International Symposium on Field Programmable Gate Arrays, Monterey, CA, USA, 23–25 February 2003. Computation 2019, xx, 5 47 of 115 407. Qu, S.; Shou, G.; Hu, Y.; Guo, Z.; Qian, Z. High Throughput, Pipelined Implementation of AES on FPGA. In Proceedings of the 1st International Symposium on Information Engineering and Electronic Commerce, Ternopil, Ukraine, 16–17 May 2009. doi:10.1109/IEEC.2009.120. 408. Gielata, A.; Russek, P.; Wiatr, K. AES hardware implementation in FPGA for algorithm acceleration purpose. In Proceedings of the International Conference on Signals and Electronic Systems (ICSES 2008), Cracow, Poland, 14–17 September 2008. doi:10.1109/ICSES.2008.4673377. 409. Guneysu, T. Utilizing hard cores of modern FPGA devices for high-performance cryptography. J. Cryptogr. Eng. 2011, 1, 37–55. doi:10.1007/s13389-011-0002-2. 410. Farashahi, R.R.; Rashidi, B.; Sayedi, S.M. FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm. Microelectron. J. 2014, 45, 1014–1025. doi:10.1016/j.mejo.2014.05.004. 411. Chen, H.; Jing, W. Design of low hardware-cost AES. Jisuanji Gongcheng/Comput. Eng. 2005, 31, 165–167. 412. Good, T.; Benaissa, M. Very small FPGA application-specific instruction processor for AES. IEEE Trans. Circuits Syst. I-Regul. Pap. 2006, 53, 1477–1486. doi:10.1109/TCSI.2006.875179. 413. Dehbaoui, A.; Dutertre, J.M.; Robisson, B.; Tria, A. Electromagnetic Transient Faults Injection on a hardware and a software implementations of AES. In Proceedings of the 9th International Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), Leuven, Belgum, 9 September 2012. doi:10.1109/FDTC.2012.15. 414. Canivet, G.; Maistri, P.; Leveugle, R.; Clediere, J.; Valette, F.; Renaudin, M. Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. J. Cryptol. 2011, 24, 247–268. doi:10.1007/s00145-010-9083-9. 415. Pahlevanzadeh, H.; Dofe, J.; Yu, Q. Assessing CPA Resistance of AES with Different Fault Tolerance Mechanisms. In Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, China, 25–28 January 2016. 416. Dofe, J.; Pahlevanzadeh, H.; Yu, Q. A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack. J. Electron.-Test.-Theory Appl. 2016, 32, 611–624. doi:10.1007/s10836-016-5598-9. 417. Bos, J.W.; Halderman, J.A.; Heninger, N.; Moore, J.; Naehrig, M.; Wustrow, E. Elliptic curve cryptography in practice. In Proceedings of the International Conference on Financial Cryptography and Data Security, Christ Church, Barbados, 3–7 March 2014. 418. Mahdizadeh, H.; Masoumi, M. Novel Architecture for Efficient FPGA Implementation of Elliptic Curve Cryptographic Processor Over GF(2(163)). IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2013, 21, 2330–2333. doi:10.1109/TVLSI.2012.2230410. 419. Liu, Z.; Grossschadl, J.; Hu, Z.; Jarvinen, K.; Wang, H.; Verbauwhede, I. Elliptic Curve Cryptography with Efficiently Computable Endomorphisms and Its Hardware Implementations for the Internet of Things. IEEE Trans. Comput. 2017, 66, 773–785. doi:10.1109/TC.2016.2623609. 420. Tawalbeh, L.A.; Mohammad, A.; Gutub, A.A.A. Efficient FPGA Implementation of a Programmable Architecture for GF(p) Elliptic Curve Crypto Computations. J. Signal Process. Syst. Signal Image Video Technol. 2010, 59, 233–244. doi:10.1007/s11265-009-0376-x. 421. Khan, Z.U.A.; Benaissa, M. High Speed ECC Implementation on FPGA over GF(2(m)). In Proceedings of the 25th International Conference on Field Programmable Logic and Applications, Imperial Coll London, London, UK, 2–4 September 2015. 422. Asif, S.; Kong, Y. Highly Parallel Modular Multiplier for Elliptic Curve Cryptography in Residue Number System. Circuits Syst. Signal Process. 2017, 36, 1027–1051. doi:10.1007/s00034-016-0336-1. 423. Okamoto, T.; Uchiyama, S. A new public-key cryptosystem as secure as factoring. In Advances in Cryptology—EUROCRYPT’98; Nyberg, K., Ed.; Springer Berlin Heidelberg: Berlin/Heidelberg, Germany, 1998; pp. 308–318. 424. Daly, A.; Marnane, W. Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic. In Proceedings of the FPGA 2002: Tenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, 24–26 February 2002. 425. Issad, M.; Boudraa, B.; Anane, M.; Anane, N. Software/hardware co-design of modular exponentiation for efficient rsa cryptosystem. J. Circuits Syst. Comput. 2014, 23. doi:10.1142/S0218126614500327. 426. Bai, X.; Jiang, L.; Dai, Q.; Yang, J.; Tan, J. Acceleration of RSA Processes based on Hybrid ARM-FPGA Cluster. In Proceedings of the IEEE Symposium on Computers and Communications (ISCC), Heraklion, Greece, 3–7 July 2017. Computation 2019, xx, 5 48 of 115 427. Bayam, K.A.; Ors, B. Differential power analysis resistant hardware implementation of the RSA cryptosystem. Turk. J. Electr. Eng. Comput. Sci. 2010, 18. doi:10.3906/elk-0904-4. 428. Ren, Y.; Wu, L.; Li, X.; Wang, A.; Zhang, X. Design and implementation of a side-channel resistant and low power RSA processor. Qinghua Daxue Xuebao/J. Tsinghua Univ. 2016, 56, 1–6. doi:10.16511/j.cnki.qhdxxb.2016.23.012. 429. Liu, Z.; Xia, L.; Jing, J.; Liu, P. A tiny RSA coprocessor based on optimized systolic montgomery architecture. In Proceedings of the International Conference on Security and Cryptography (SECRYPT), ETSII Univ Seville, Seville, Spain, 18–21 July 2011. 430. George, D.; Bonifus, P.L. RSA Encryption System Using Encoded Multiplier and Vedic Mathematics. In Proceedings of the International Conference on Advanced Computing and Communication Systems (ICACCS), Sri Eshwar Coll Engn, Coimbatore, India, 19–21 December 2013. 431. Chakraborty, D.; Raha, P.; Bhattacharya, A.; Dutta, R. Speed optimization of a FPGA based modified Viterbi Decoder. In Proceedings of the 3rd International Conference on Computer Communication and Informatics (ICCCI), Coimbatore, India, 4–6 January 2013. 432. Vestias, M.; Neto, H.; Sarmento, H. Design of high-speed viterbi decoders on virtex-6 FPGAs. In Proceedings of the 15th Euromicro Conference on Digital System Design, DSD 2012, Cesme, Izmir, 5–8 September 2012. doi:10.1109/DSD.2012.42. 433. Garcia-Bosque, M.; Perez, A.; Sanchez-Azqueta, C.; Celma, S. Application of a MEMS-Based TRNG in a Chaotic Stream Cipher. Sensors 2017, 17. doi:10.3390/s17030646. 434. Pudi, V.; Chattopadhyay, A.; Lam, K.Y. Secure and Lightweight Compressive Sensing Using Stream Cipher. IEEE Trans. Circuits Syst. -Express Briefs 2018, 65, 371–375. doi:10.1109/TCSII.2017.2715659. 435. Perez-Resa, A.; Garcia-Bosque, M.; Sanchez-Azqueta, C.; Celma, S. Chaos-Based Stream Cipher for Gigabit Ethernet. In Proceedings of the 9th IEEE Latin American Symposium on Circuits and Systems (LASCAS), Puerto Vallarta, Mexico, 25–28 February 2018. 436. Perez-Resa, A.; Garcia-Bosque, M.; Sanchez-Azqueta, C.; Celma, S. Using a Chaotic Cipher to Encrypt Ethernet Traffic. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 27–30 May 2018. 437. Mohd, B.J.; Hayajneh, T.; Abu Khalaf, Z.; Yousef, K.M.A. Modeling and optimization of the lightweight HIGHT block cipher design with FPGA implementation. Secur. Commun. Netw. 2016, 9, 2200–2216. doi:10.1002/sec.1479. 438. Kolay, S.; Mukhopadhyay, D. Khudra: A New Lightweight Block Cipher for FPGAs. In Proceedings of the 4th International Conference on Security, Privacy, and Applied Cryptography Engineering (SPACE), Def Inst Adv Technol, Pune, India, 18–22 October 2014. 439. Mohd, B.J.; Hayajneh, T.; Youseff, K.M.A.; Abu Khalaf, Z.; Bhuiyan, M.Z.A. Hardware design and modeling of lightweight block ciphers for secure communications. Future Gener. Comput.-Syst.- Int. J. Escience 2018, 83, 510–521. doi:10.1016/j.future.2017.03.025. 440. Gueneysu, T.; Kasper, T.; Novotny, M.; Paar, C.; Rupp, A. Cryptanalysis with COPACOBANA. IEEE Trans. Comput. 2008, 57, 1498–1513. doi:10.1109/TC.2008.80. 441. Rouvroy, G.; Standaert, F.; Quisquater, J.; Legat, J. Efficient uses of FPGAs for implementations of DES and its experimental linear cryptanalysis. IEEE Trans. Comput. 2003, 52, 473–482. doi:10.1109/TC.2003.1190588. 442. Zodpe, H.D.; Wani, P.W.; Mehta, R.R. Design and Implementation of Algorithm for DES Cryptanalysis. In Proceedings of the 12th International Conference on Hybrid Intelligent Systems (HIS), Pune, India, 4–7 December 2012. 443. Taherkhani, S.; Ever, E.; Gemikonakli, O. Implementation of non-pipelined and pipelined Data Encryption Standard (DES) using Xilinx Virtex-6 FPGA technology. In Proceedings of the 2010 10th IEEE International Conference on Computer and Information Technology, Bradford, UK, 29 June–1 July 2010. doi:10.1109/CIT.2010.227. 444. Pandey, B.; Thind, V.; Sandhu, S.K.; Walia, T.; Sharma, S. SSTL Based Power Efficient Implementation of DES Security Algorithm on 28nm FPGA. Int. J. Secur. Its Appl. 2015, 9, 267–273. doi:10.14257/ijsia.2015.9.7.23. 445. Abdelwahab, M.M. High performance FPGA implementation of Data Encryption Standard. In Proceedings of the International Conference on Computing, Control, Networking, Electronics and Embedded Systems Engineering (ICCNEEE), Khartoum, Sudan, 7–9 September 2015. Computation 2019, xx, 5 49 of 115 446. Oukili, S.; Bri, S. High throughput FPGA implementation of data encryption standard with time variable sub-keys. Int. J. Electr. Comput. Eng. 2016, 6, 298–306. doi:10.11591/ijece.v6i1.8388. 447. Pieprzyk, J. Topics in Cryptology - CT-RSA 2010: The 10th Cryptographers’ Track at the RSA Conference 2010, San Francisco, CA, USA, March 1-5, 2010. Proceedings; LNCS sublibrary: Security and cryptology, Springer: Berlin/Heidelberg, Germany, 2010. 448. Gaj, K.; Homsirikamol, E.; Rogawski, M. Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs. In Proceedings of the 12th International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2010), Santa Barbara, CA, USA, 17–20 August 2010. 449. Jungk, B.; Apfelbeck, J. Area-efficient FPGA implementations of the SHA-3 finalists. In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, 30 November–2 December 2011. doi:10.1109/ReConFig.2011.16. 450. Homsirikamol, E.; Rogawski, M.; Gaj, K. Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs. In Proceedings of the 13th International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2011), Nara, Japan, 28 September–1 October 2011. 451. Kobayashi, K.; Ikegami, J.; Knezevic, M.; Guo, E.; Matsuo, S.; Huang, S.; Nazhandali, L.; Kocabas, U.; Fan, J.; Satoh, A.; Verbauwhede, I.; Sakiyama, K.; Ohta, K. Prototyping platform for performance evaluation of SHA-3 candidates. In Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010, Anaheim, CA, USA, 13–14 June 2010. doi:10.1109/HST.2010.5513111. 452. Akin, A.; Aysu, A.; Ulusel, O.; Savas, E. Efficient hardware implementations of high throughput SHA-3 candidates Keccak, Luffa and Blue Midnight Wish for single-and multi-message hashing. In Proceedings of the 3rd International Conference on Security of Information and Networks, SIN 2010, Taganrog, Russia, 7–11 September 2010. doi:10.1145/1854099.1854135. 453. Kaps, J.P.; Yalla, P.; Surapathi, K.K.; Habib, B.; Vadlamudi, S.; Gurung, S.; Pham, J. Lightweight Implementations of SHA-3 Candidates on FPGAs. In Proceedings of the 12th International Conference on Cryptology in India, Inst Math Sci, Chennai, India, 11–14 December 2011. 454. Johansson, T.; Nguyen, P. Advances in Cryptology EUROCRYPT 2013: 32nd Annual International Conference on the Theory and Applications of Cryptographic Techniques, Athens, Greece, 26–30 May 2013, Proceedings; Lecture Notes in Computer Science; Springer: Berlin/Heidelberg, Germany, 2013. 455. Honda, T.; Guntur, H.; Satoh, A. FPGA Implementation of New Standard Hash Function Keccak. In Proceedings of the 3rd IEEE Global Conference on Consumer Electronics (GCCE), Tokyo, Japan, 7–10 October 2014. 456. Athanasiou, G.S.; Makkas, G.P.; Theodoridis, G. High throughput pipelined fpga implementation of the new sha-3 cryptographic hash algorithm. In Proceedings of the 6th International Symposium on Communications, Control and Signal Processing (ISCCSP), Athens, Greece, 21–23 May 2014. 457. Rao, M.; Newe, T.; Grout, I. Secure hash algorithm-3(SHA-3) implementation on Xilinx FPGAS, suitable for IoT applications. In Proceedings of the 8th International Conference on Sensing Technology, ICST 2014, Liverpool, UK, 2–4 September 2014. 458. Ioannou, L.; Michail, H.E.; Voyiatzis, A.G. High Performance Pipelined FPGA Implementation of the SHA-3 Hash Algorithm. In Proceedings of the 4th Mediterranean Conference on Embedded Computing (MECO, Budva, Montenegro, 14–18 June 2015. 459. Kahri, F.; Mestiri, H.; Bouallegue, B.; Machhout, M. High Speed FPGA Implementation of Cryptographic KECCAK Hash Function Crypto-Processor. J. Circuits Syst. Comput. 2016, 25. doi:10.1142/S0218126616500262. 460. Yang, Y.; He, D.; Kumar, N.; Zeadally, S. Compact Hardware Implementation of a SHA-3 Core for Wireless Body Sensor Networks. IEEE Access 2018, 6, 40128–40136. doi:10.1109/ACCESS.2018.2855408. 461. Nyberg, K. Perfect nonlinear S-boxes. Advances in Cryptology — EUROCRYPT ’91; Davies, D.W., Ed.; Springer Berlin Heidelberg: Berlin/Heidelberg, Germany, 1991; pp. 378–386. 462. Wong, M.M.; Wong, M.L.D.; Nandi, A.K.; Hijazin, I. Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2012, 20, 1151–1155. doi:10.1109/TVLSI.2011.2141693. Computation 2019, xx, 5 50 of 115 463. Iyer, N.C.; Anandmohan, P.V.; Poornaiah, D.V.; Kulkarni, V.D. High throughput, low cost, fully pipelined architecture for AES crypto chip. In Proceedings of the Annual IEEE India Conference, New Delhi, India, 15 September–17 September 2006. 464. Oukili, S.; Bri, S. High throughput FPGA implementation of Advanced Encryption Standard algorithm. Telkomnika Telecommun. Comput. Electron. Control. 2017, 15, 494–503. doi:10.12928/TELKOMNIKA.v15i1.4713. 465. Aziz, A.; Ikram, N. Memory efficient implementation of AES S-BOXES on FPGA. J. Circuits Syst. Comput. 2007, 16, 603–611. doi:10.1142/S0218126607003873. 466. Rais, M.H.; Qasim, S.M. Resource Efficient Implementation of S-Box Based on Reduced Residue of Prime Numbers using Virtex-5 FPGA. In Proceedings of the World Congress on Engineering (WCE 2010), Imperial Coll London, London, UK, 30 June–2 July 2010. 467. Nadjia, A.; Mohamed, A. Efficient Implementation of AES S-box in LUT-6 FPGAs. In Proceedings of the 2015 4th International Conference on Electrical Engineering (ICEE), Boumerdes, Algeria, 13–15 December 2015. 468. Prathiba, A.; Bhaaskaran, V.S.K. Lightweight S-Box Architecture for Secure Internet of Things. Information 2018, 9. doi:10.3390/info9010013. 469. Kumar, S.; Sharma, V.K.; Mahapatra, K.K. Low Latency VLSI Architecture of S-box for AES Encryption. In Proceedings of the IEEE International Conference on Circuits, Power and Computing Technologies (ICCPCT), Noorul lslam Univ, Noorul Islam Ctr Higher Educ, Kumaracoil, India, 20–22 March 2013. 470. Tay, J.J.; Wong, M.M.; Hijazin, I. Compact and Low Power AES Block Cipher Using Lightweight Key Expansion Mechanism and Optimal Number of S-Boxes. In Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), Sawarak, Malaysia, 1–4 December 2014. 471. Prasad, H.; JyotiKandpal.; Sharma, D.; Verma, G. Design of Low Power and Secure Implementation of SBOX for AES. In Proceedings of the 3rd International Conference on Computing for Sustainable Global Development (INDIACom), New Delhi, India, 16–18 March 2016. 472. Rajasekar, P.; Mangalam, H. Design and implementation of low power multistage AES S box. Int. J. Appl. Eng. Res. 2015, 10, 40535–40540. 473. Chu, M.; Kim, B.; Park, S.; Hwang, H.; Jeon, M.; Lee, B.H.; Lee, B.G. Neuromorphic Hardware System for Visual Pattern Recognition With Memristor Array and CMOS Neuron. IEEE Trans. Ind. Electron. 2015, 62, 2410–2419. doi:10.1109/TIE.2014.2356439. 474. Salvador, R.; Terleira, C.; Moreno, F.; Riesgo, T. Approach to an FPGA embedded, autonomous object recognition system: run-time learning and adaptation. In Proceedings of the Conference on VLSI Circuits and Systems IV, Dresden, Germany, 4–6 May 2009. doi:10.1117/12.821687. 475. Xie, S.; Liu, C.; Wu, Y.; Zhang, J.; Duan, X. A hybrid BCI (brain-computer interface) based on multi-mode EEG for words typing and mouse control. Xibei Gongye Daxue Xuebao/J. Northwestern Polytech. Univ. 2016, 34, 245–249. 476. He, Y.; Wu, A.; Xin, Y. Rapid pattern recognition of fault current for HTS three-phase saturated iron core fault current limiter. Diangong Jishu Xuebao/Trans. China Electrotech. Soc. 2009, 24, 81–87. 477. Mekki, H.; Mellit, A.; Kalogirou, S.A.; Messai, A.; Furlan, G. FPGA-based implementation of a real time photovoltaic module simulator. Prog. Photovoltaics 2010, 18, 115–127. doi:10.1002/pip.950. 478. Mellit, A.; Mekki, H.; Shaari, S. FPGA-Based Neural network for simulation of photovoltaic array: application for estimating the output power generation. In Proceedings of the 33rd IEEE Photovoltaic Specialists Conference, San Diego, CA, USA, 11–16 May 2008. 479. Khaldi, N.; Mahmoudi, H.; Zazi, M.; Barradi, Y. Implementation of a MPPT neural controller for photovoltaic systems on FPGA circuit. WSEAS Trans. Power Syst. 2014, 9, 471–478. 480. [No, a.n.a. FPGA realization of power quality disturbance detection: An approach with wavelet, ANN and fuzzy logic. In Proceedings of the International Joint Conference on Neural Networks, IJCNN 2005, Montreal, QC, Canada, 31 July–4 August 2005. doi:10.1109/IJCNN.2005.1556315. 481. Reaz, M.B.I.; Choong, F.; Sulaiman, M.S.; Mohd-Yasin, F. Prototyping of wavelet transform, artificial neural network and fuzzy logic for power quality disturbance classifier. Electr. Power Components Syst. 2007, 35, 1–17. doi:10.1080/15325000600815431. Computation 2019, xx, 5 51 of 115 482. Quintal, G.; Sanchez, E.N.; Alanis, A.Y.; Arana-Daniel, N.G. Real-time FPGA Decentralized Inverse Optimal Neural Control for a Shrimp Robot. In Proceedings of the 10th System of Systems Engineering Conference (SoSE), San Antonio, TX, USA, 17–20 May 2015. 483. De, L.F.M.; Echanobe, J.; Del, C.I.; Susperregui, L.; Maurtua, I. Hardware implementation of a neural-network recognition module for visual servoing in a mobile robot. In Proceedings of the 21st International Workshop on Database and Expert Systems Applications, DEXA 2010, Bilbao, Spain, 30 August–3 September 2010. doi:10.1109/DEXA.2010.58. 484. Hwang, K.S.; Lo, C.Y.; Liu, W.L. A Modular Agent Architecture for an Autonomous Robot. IEEE Trans. Instrum. Meas. 2009, 58, 2797–2806. doi:10.1109/TIM.2009.2016301. 485. Khalil-Hani, M.; Nambiar, V.; Marsono, M. GA-based parameter tuning in finger-vein biometric embedded systems for information security. In Proceedings of the 2012 1st IEEE International Conference on Communications in China, ICCC 2012, Beijing, China, 15–17 August 2012. doi:10.1109/ICCChina.2012.6356884. 486. Asami, K.; Hagiwara, H.; Komori, M. Visual navigation system based on evolutionary computation on FPGA for patrol service robot. In Proceedings of the 1st IEEE Global Conference on Consumer Electronics, GCCE 2012, Tokyo, Japan, 2–5 October 2012. doi:10.1109/GCCE.2012.6379607. 487. Imran, N.; Ashraf, R.; DeMara, R. Power and quality-aware image processing soft-resilience using online multi-objective GAs. Int. J. Comput. Vis. Robot. 2015, 5, 72–98. doi:10.1504/IJCVR.2015.067154. 488. PrasadaKumari, K.S.; Kumar, S.V. Design and Simulation of Evolvable Hardware for Image Processing. In Proceedings of the International Conference on Micro-Electronics and Telecommunication Engineering (ICMETE), SRM Univ, Delhi NCR Campus, Ghaziabad, India, 22–23 September 2016. doi:10.1109/ICMETE.2016.53. 489. Qu, Y.; Soininen, J.P.; Nurmi, J. Static scheduling techniques for dependent tasks on dynamically reconfigurable devices. J. Syst. Archit. 2007, 53, 861–876. doi:10.1016/j.sysarc.2007.02.004. 490. Bogdanski, M.; Lewis, P.; Becker, T.; Yao, X. Improving scheduling techniques in heterogeneous systems with dynamic, on-line optimisations. In Proceedings of the 5th International Conference on Complex, Intelligent and Software Intensive Systems, CISIS 2011, Seoul, Korea, 30 June–2 July 2011. doi:10.1109/CISIS.2011.81. 491. Abdallah, F.; Tanougast, C.; Kacem, I.; Diou, C.; Singer, D. Temporal partitioning optimization for dynamically reconfigurable architecture. In Proceedings of the 46th International Conferences on Computers and Industrial Engineering, CIE 2016, Tianjin, China, 29–31 October 2016. 492. Coury, D.V.; Oleskovicz, M.; Delbem, A.C.B.; Simoes, E.V.; Silva, T.V.; de Carvalho, J.R.; Barbosa, D. A Genetic Based Algorithm for Frequency Relaying using FPGAs. In Proceedings of the General Meeting of the IEEE-Power-and-Energy-Society, Calgary, AB Canada, 26–30 July 2009. 493. Coury, D.; Oleskovicz, M.; Barbosa, D.; Delbem, A.; Simoes, E.; De, C.J. Evolutionary algorithm for frequency estimation in electrical systems using FPGAS [Algoritmo evolutivo para a estimacao da frequencia em sistemas eletricos utilizando fpgas]. Controle Y Autom. 2011, 22, 495–505. 494. Coury, D.; Oleskovicz, M.; Delbem, A.; Simoes, E.; Silva, T.; De, C.J.; Barbosa, D. Frequency relaying based on genetic algorithm using FPGAs. In Proceedings of the 2009 15th International Conference on Intelligent System Applications to Power Systems, ISAP ’09, Curitiba, Brazil, 8–12 November 2009. doi:10.1109/ISAP.2009.5352830. 495. Coury, D.V.; Delbem, A.C.B.; Oleskovicz, M.; Simoes, E.V.; Barbosa, D.; de Carvalho, J.R. FPGA Design of a New Frequency Relay Based on Evolutionary Algorithms. In Proceedings of the IEEE PES 2nd Latin American Conference on Innovative Smart Grid Technologies (ISGT Latin America), IEEE S Brazil Sect, Sao Paulo, Brazil, 15–17 April 2013. 496. Allaire, F.C.J.; Tarbouchi, M.; Labonte, G.; Fusina, G. FPGA Implementation of Genetic Algorithm for UAV Real-Time Path Planning. J. Intell. Robot. Syst. 2009, 54, 495–510. doi:10.1007/s10846-008-9276-8. 497. Tuncer, A.; Yildirim, M.; Erkan, K. A hybrid implementation of genetic algorithm for path planning of mobile robots on FPGA. In Proceedings of the 27h International Symposium on Computer and Information Sciences, ISCIS 2012, Paris, France, 3–4 October 2012. doi:10.1007/978-1-4471-4594-3-47. 498. Tuncer, A.; Yildirim, M. Design and implementation of a genetic algorithm IP core on an FPGA for path planning of mobile robots. Turk. J. Electr. Eng. Comput. Sci. 2016, 24, 5055–5067. doi:10.3906/elk-1502-122. Computation 2019, xx, 5 52 of 115 499. Roberge, V.; Tarbouchi, M. Fast Path Planning for Unmanned Aerial Vehicle using Embedded GPU System. In Proceedings of the 14th International Multi-Conference on Systems, Signals & Devices (SSD), Marrakech, Morocco, 28–31 March 2017. 500. Shah, R. Support Vector Machines for Classification and Regression; McGill theses, McGill University Libraries, 2007. 501. Hsiao, P.Y.; Lin, S.Y.; Huang, S.S. An FPGA based human detection system with embedded platform. Microelectron. Eng. 2015, 138, 42–46. doi:10.1016/j.mee.2015.01.018. 502. Zhou, Y.; Chen, Z.; Huang, X. A Pipeline Architecture for Traffic Sign Classification on an FPGA. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24–27 May 2015. 503. Yuan, X.; Li, C.N.; Xu, X.L.; Mei, J.; Zhang, J.G. A two-stage HOG feature extraction processor embedded with SVM for pedestrian detection. In Proceedings of the IEEE International Conference on Image Processing, ICIP 2015, Quebec City, QC, Canada,27–30 September 2015. doi:10.1109/ICIP.2015.7351445. 504. Ilas, M.E.; Ilas, C. A New Method of Histogram Computation for Efficient Implementation of the HOG Algorithm. Computers 2018, 7. doi:10.3390/computers7010018. 505. Wang, M.S.; Zhang, Z.R. FPGA Implementation of HOG based Multi-Scale Pedestrian Detection. In Proceedings of the 4th IEEE International Conference on Applied System Invention (IEEE ICASI), Tokyo, Japan, 13–17 April 2018. 506. Patil, R.; Gupta, G.; Sahula, V.; Mandal, A. Power aware hardware prototyping of multiclass SVM classifier through reconfiguration. In Proceedings of the 25th International Conference on VLSI Design, VLSID 2012 and the 11th International Conference on Embedded Systems, Hyderabad, India, 7–11 January 2012. doi:10.1109/VLSID.2012.47. 507. Saini, R.; Saurav, S.; Gupta, D.C.; Sheoran, N. Hardware Implementation of SVM using System Generator. In Proceedings of the 2nd IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT), Sri Venkateshwara Coll Engn, Bangalore, India, 19–20 May 2017. 508. Saurav, S.; Saini, A.K.; Singh, S.; Saini, R.; Gupta, S. VLSI Architecture of Pairwise Linear SVM for Facial Expression Recognition. In Proceedings of the International Conference on Advances in Computing, Communications and Informatics ICACCI, SCMS Grp of Inst, Aluva, India, 10–13 August 2015. 509. Groleat, T.; Arzel, M.; Vaton, S. Hardware Acceleration of SVM-Based Traffic Classification on FPGA. In Proceedings of the 8th IEEE International Wireless Communications and Mobile Computing Conference (IWCMC), Limassol, Cyprus, 27–31 August 2012. 510. Afifi, S.; GholamHosseini, H.; Sinha, R. Hardware Acceleration of SVM-Based Classifier for Melanoma Images. In Proceedings of the 7th Pacific-Rim Symposium on Image and Video Technology (PSIVT), Auckland, New Zealand, 23–27 November 2015. doi:10.1007/978-3-319-30285-0_19. 511. Afifi, S.; GholamHosseini, H.; Sinha, R. A Low-Cost FPGA-based SVM Classifier for Melanoma Detection. In Proceedings of the IEEE EMBS Conference on Biomedical Engineering and Sciences (IECBES), Kuala Lumpur, Malaysia, 4–8 December 2016. 512. Gholamhosseini, H. Melanoma image processing and analysis for decision support systems. In Proceedings of the 7th Pacific-Rim Symposium on Image and Video Technology, PSIVT 2015, Auckland, New Zealand, 23–27 November 2015. doi:10.1007/978-3-319-30285-0. 513. Orozco-Duque, A.; Rua, S.; Zuluaga, S.; Redondo, A.; Restrepo, J.; Bustamante, J. Support vector machine and artificial neural network implementation in embedded systems for real time arrhythmias detection. In Proceedings of the International Conference on Bio-Inspired Systems and Signal Processing, BIOSIGNALS 2013, Barcelona, Spain, 11–14 February 2013. 514. Tsoutsouras, V.; Koliogeorgi, K.; Xydis, S.; Soudris, D. An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC. J. Signal Process. Syst. Signal Image Video Technol. 2017, 88, 127–147. doi:10.1007/s11265-017-1230-1. 515. Wang, Y.; Li, Z.; Feng, L.; Bai, H.; Wang, C. Hardware design of multiclass SVM classification for epilepsy and epileptic seizure detection. IET Circuits Devices Syst. 2018, 12, 108–115. doi:10.1049/iet-cds.2017.0216. 516. Attaran, N.; Puranik, A.; Brooks, J.; Mohsenin, T. Embedded Low-Power Processor for Personalized Stress Detection. IEEE Trans. Circuits Syst. -Express Briefs 2018, 65, 2032–2036. doi:10.1109/TCSII.2018.2799821. Computation 2019, xx, 5 53 of 115 517. Ghosh-Dastidar, S.; Adeli, H. Third Generation Neural Netw.: Spiking Neural Netw.. Advances in Computational Intelligence; Yu, W.; Sanchez, E.N., Eds.; Springer Berlin Heidelberg: Berlin/Heidelberg, Germany, 2009; pp. 167–178. 518. Rice, K.L.; Bhuiyan, M.A.; Taha, T.M.; Vutsinas, C.N.; Smith, M.C. FPGA Implementation of Izhikevich Spiking Neural Netw. for Character Recognition. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, 9–11 December 2009. doi:10.1109/ReConFig.2009.77. 519. Soleimani, H.; Ahmadi, A.; Bavandpour, M. Biologically Inspired Spiking Neurons: Piecewise Linear Models and Digital Implementation. IEEE Trans. Circuits Syst. -Regul. Pap. 2012, 59, 2991–3004. doi:10.1109/TCSI.2012.2206463. 520. Dominguez-Morales, J.P.; Jimenez-Fernandez, A.; Dominguez-Morales, M.; Jimenez-Moreno, G. NAVIS: Neuromorphic Auditory VISualizer Tool. Neurocomputing 2017, 237, 418–422. doi:10.1016/j.neucom.2016.12.046. 521. Cerezuela-Escudero, E.; Jimenez-Fernandez, A.; Paz-Vicente, R.; Dominguez-Morales, J.P.; Dominguez-Morales, M.J.; Linares-Barranco, A. Sound Recognition System Using Spiking and MLP Neural Netw.. In Proceedings of the 25th International Conference on Artificial Neural Netw. (ICANN), Barcelona, Spain, 6–9 September 2016. doi:10.1007/978-3-319-44781-0_43. 522. Paz, I.; Gress, N.; Mendoza, M. Pattern recognition with spiking Neural Netw.. In Proceedings of the 12th Mexican International Conference on Artificial Intelligence, MICAI 2013, Mexico City, Mexico, 24–30 November 2013. doi:10.1007/978-3-642-45111-9_25. 523. Cao, Y.; Chen, Y.; Khosla, D. Spiking Deep Convolutional Neural Netw. for Energy-Efficient Object Recognition. Int. J. Comput. Vis. 2015, 113, 54–66. doi:10.1007/s11263-014-0788-3. 524. Yang, M.; Crenshaw, J.; Augustine, B.; Mareachen, R.; Wu, Y. AdaBoost-based face detection for embedded systems. Comput. Vis. Image Underst. 2010, 114, 1116–1125. doi:10.1016/j.cviu.2010.03.010. 525. Das, S.; Jariwala, A.; Pinalkumar. Modified Architecture for Real-Time Face Detection using FPGA. In Proceedings of the 3rd Nirma-University International Conference on Engineering (NUiCONE), Ahmedabad, India, 6–8 December 2012. 526. Lee, S.S.; Jang, S.J.; Kim, J.; Choi, B. A Hardware Architecture of Face Detection for Human-robot Interaction and its Implementation. In Proceedings of the IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia), Seoul, Korea, 26–28 October 2016. 527. Senthilsingh, C.; Manikandan, M. Design and implementation of face detection using Adaboost Algorithm. J. Theor. Appl. Inf. Technol. 2014, 65, 707–714. 528. Chakrasali, S.; Kuthale, S. Optimized face detection on FPGA. In Proceedings of the 2016 International Conference on Circuits, Controls, Communications and Computing, I4C 2016, Bangalore, India, 4–6 October 2016. doi:10.1109/CIMCA.2016.8053269. 529. Dohi, K.; Negi, K.; Shibata, Y.; Oguri, K. FPGA Implementation of Human Detection by HOG Features with AdaBoost. IEICE Trans. Inf. Syst. 2013, E96D, 1676–1684. doi:10.1587/transinf.E96.D.1676. 530. Broesch, J. Digital Signal Processing: Instant Access; Instant Access, Elsevier Science: Amsterdam, The The Netherlands, 2008. 531. Banerjee, A.; Dhar, A.; Banerjee, S. FPGA realization of a CORDIC based FFT processor for biomedical signal processing. MMicroprocess. Microsyst. 2001, 25, 131–142. doi:10.1016/S0141-9331(01)00106-5. 532. Oruklu, E.; Xiao, X.; Saniie, J. Reduced Memory and Low Power Architectures for CORDIC-based FFT Processors. J. Signal Process. Syst. Signal Image Video Technol. 2012, 66, 129–134. doi:10.1007/s11265-011-0586-x. 533. Gong, R.X.; Wei, J.Q.; Sun, D.; Xie, L.L.; Shu, P.F.; Meng, X.B. FPGA implementation of a CORDIC-based radix-4 FFT processor for real-time harmonic analyzer. In Proceedings of the 2011 7th International Conference on Natural Computation, ICNC 2011, Shanghai, China, 26–28 July 2011. doi:10.1109/ICNC.2011.6022441. 534. Zhou, J.; Dong, Y.; Dou, Y.; Lei, Y. Dynamic configurable floating-point FFT pipelines and hybrid-mode CORDIC on FPGA. In Proceedings of the International Conference on Embedded Software and Systems, Chengdu, China, 29–31 July 2008. 535. Kumar, V.; Ray, K.C.; Kumar, P. CORDIC-based VLSI architecture for real time implementation of flat top window. Microprocess. Microsyst. 2014, 38, 1063–1071. doi:10.1016/j.micpro.2014.07.004. Computation 2019, xx, 5 54 of 115 536. Xiong, Y.; Zhang, J.; Zhang, P. A CORDIC Based FFT Processor for MIMO Channel Emulator. In Proceedings of the 4th International Conference on Graphic and Image Processing (ICGIP), Singapore, Singapore, 6–7 October 2012. doi:10.1117/12.2010856. 537. Hemmert, K.; Underwood, K. An analysis of the double-precision floating-point FFT on FPGAs. In Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, USA, 18–20 April 2005. 538. Jiang, H.; Luo, H.; Tian, J.; Song, W. Design of an efficient FFT processor for OFDM systems. IEEE Trans. Consum. Electron. 2005, 51, 1099–1103. doi:10.1109/TCE.2005.1561830. 539. Boopal, P.P.; Garrido, M.; Gustafsson, O. A Reconfigurable FFT Architecture for Variable-Length and Multi-Streaming OFDM Standards. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19–23 May 2013. 540. Su, C.H.; Wu, J.M. Reconfigurable FFT design for low power OFDM communication systems. In Proceedings of the 10th IEEE International Symposium on Consumer Electronics (ISCE 2006), St Petersburg, Russia, 28 June–1 July 2006. 541. Tian, J.; Xu, Y.; Jiang, H.; Luo, H.; Song, W. Efficient algorithms of FFT butterfly for OFDM systems. In Proceedings of the 6th IEEE Circuits and Systems Symposium on Emerging Technologies, Shanghai, China, 31 May–2 June 2004. doi:10.1109/CASSET.2004.1321923. 542. Ferreira, M.L.; Barahimi, A.; Ferreira, J.C. Dynamically Reconfigurable FFT Processor for Flexible OFDM Baseband Processing. In Proceedings of the 11th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Istanbul, Turkey, 12–14 April 2016. 543. Ma, Z.g.; Yu, F.; Ge, R.f.; Wang, Z.k. An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays. J. Zhejiang-Univ.-Sci. -Comput. Electron. 2011, 12, 323–329. doi:10.1631/jzus.C1000258. 544. Patrikar, M.; Tehre, V. Design and Power Measurement of Different Points FFT using Radix-2 Algorithm for FPGA Implementation. In Proceedings of the International conference of Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 20–22 April 2017. 545. Garrido, M.; Angel Sanchez, M.; Luisa Lopez-Vallejo, M.; Grajal, J. A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2017, 25, 375–379. doi:10.1109/TVLSI.2016.2567784. 546. Ferizi, A.; Hoeher, B.; Jung, M.; Fischer, G.; Koelpin, A. Design and implementation of a fixed-point radix-4 FFT optimized for local positioning in wireless sensor networks. In Proceedings of the 9th International Multi-Conference on Systems, Signals and Devices, SSD 2012, Chemnitz, Germany, 20–23 March 2012. doi:10.1109/SSD.2012.6197958. 547. Mankar, A.; Das, A.D.; Prasad, N. FPGA Implementation of 16-Point Radix-4 Complex FFT Core Using NEDA. In Proceedings of the Students Conference on Engineering and Systems (SCES) - Inspiring Engineering and Systems for Sustainable Development, Allhabad, India, 12–14 April 2013. 548. Van Fleet, P. Discrete Wavelet Transformations: An Elementary Approach with Applications; Wiley: Hoboken, NJ, USA, 2011. 549. Li, L.; Zhou, G.; Fiethe, B.; Michalik, H.; Osterloh, B. Efficient implementation of the CCSDS 122.0-B-1 compression standard on a space-qualified field programmable gate array. J. Appl. Remote. Sens. 2013, 7. doi:10.1117/1.JRS.7.074595. 550. Gholipour, M. Design and Implementation of Lifting Based Integer Wavelet Transform for Image Compression Applications. In Proceedings of the International Conference on Digital Information and Communication Technology and Its Applications, Univ Bourgogne, Dijon, France, 21–23 June 2011. 551. Dang, P.; Chau, P. Discrete Wavelet Transform for image compression - A hardware approach. In Proceedings of the Conference on Image Display at Medical Imaging 1999, SAN DIEGO, CA, USA, 21–23 Fubruary 1999. doi:10.1117/12.349430. 552. Challa, K.V.; Krishna, P.V.; Rao, C.N. Design of a novel Architecture of 3-D Discrete Wavelet Transform for Image Processing through Video Compression; IEEE: 5, 2014. In Proceedings of the 3rd International Conference on Communications and Signal Processing (ICCSP), Melmaruvathur, India, 3–5 April 2014. 553. Swami, S.; Mulani, A. An efficient FPGA implementation of discrete wavelet transform for image compression. In Proceedings of the 2017 International Conference on Energy, Computation 2019, xx, 5 55 of 115 Communication, Data Analytics and Soft Computing, ICECDS 2017, Chennai, India, 1–2 August 2017, doi:10.1109/ICECDS.2017.8390088. 554. Mulani, A.; Mane, P. Area efficient high speed FPGA based invisible watermarking for image authentication. Indian J. Sci. Technol. 2016, 9. doi:10.17485/ijst/2016/v9i39/101888. 555. Singh, G.; Lamba, M.S. Efficient Hardware Implementation of Image Watermarking Using DWT and AES Algorithm. In Proceedings of the 39th National Systems Conference (NSC), Shiv Nadar Univ, Dadri, India, 14–16 December 2015. 556. Asaduzzaman, K.; Reaz, M.B.I.; Mohd-Yasin, F.; Sim, K.S.; Hussain, M.S. A Study on Discrete Wavelet-Based Noise Removal from EEG Signals. Adv. Comput. Biol. 2010, 680, 593–599. doi:10.1007/978-1-4419-5913-3_65. 557. Harender.; Sharma, R. DWT based epileptic seizure detection from EEG signal using k-NN classifier. In Proceedings of the 2017 International Conference on Trends in Electronics and Informatics, ICEI 2017, Tirunelveli, India, 11–12 May 2017. doi:10.1109/ICOEI.2017.8300806. 558. Harender.; Sharma, R.K. EEG Signal Denoising based on Wavelet Transform. In Proceedings of the International conference of Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 20–22 April 2017. 559. Zhang, C.; Wang, C.; Ahmad, M.O. A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform. IEEE Trans. Circuits Syst. -Regul. Pap. 2012, 59, 1775–1785. doi:10.1109/TCSI.2011.2180432. 560. Huang, Q.; Wang, Y.; Chang, S. High-performance FPGA implementation of discrete wavelet transform for image processing. In Proceedings of the 2011 Symposium on Photonics and Optoelectronics, SOPO 2011, Wuhan, China, 16–18 May 2011. doi:10.1109/SOPO.2011.5780507. 561. Padmavati, S.; Meshram, V.; Jayadevappa. A Hardware Implementation of Discrete Wavelet Transform for Compression of a Natural Image. In Proceedings of the International Conference on Algorithms, Methodology, Models and Applications in Emerging Technologies (ICAMMAET), Chennai, India, 16–18 February 2017. 562. Henzler, S. Time-to-Digital Converters; Springer Series in Advanced Microelectronics, Springer The Netherlands, 2010. 563. Palka, M.; Moskal, P.; Bednarski, T.; Bialas, P.; Czerwinski, E.; Kaplon, L.; Kochanowski, A.; Korcyl, G.; Kowal, J.; Kowalski, P.; et al. A novel method based solely on field programmable gate array (FPGA) units enabling measurement of time and charge of analog signals in positron emission tomography (PET). Bio-Algorithms Med.-Syst. 2014, 10. doi:10.1515/bams-2013-0104. 564. Wang, C.; Li, H.; Ramirez, R.A.; Zhang, Y.; Baghaei, H.; Liu, S.; An, S.; Wong, W.H. A Real Time Coincidence System for High Count-Rate TOF or Non-TOF PET Cameras Using Hybrid Method Combining AND-Logic and Time-Mark Technology. IEEE Trans. Nucl. Sci. 2010, 57, 708–714. doi:10.1109/TNS.2009.2039228. 565. Junnarkar, S.S.; Fried, J.; Southekal, S.; Pratte, J.F.; O’Connor, P.; Radeka, V.; Vaska, P.; Purschke, M.; Tornasi, D.; Woody, C.; et al. Next generation of real time data acquisition, calibration and control system for the RatCAP scanner. IEEE Trans. Nucl. Sci. 2008, 55, 220–224. doi:10.1109/TNS.2007.914037. 566. Wang, C.; Li, H.; Baghaei, H.; Zhang, Y.; Ramirez, R.A.; Liu, S.; An, S.; Wong, W.H. A Low-Cost Coincidence System with Capability of Multiples Coincidence for High Count-Rate TOF or Non-TOF PET Cameras Using Hybrid Method Combining AND-logic and Time-mark Technology. In Proceedings of the IEEE Nuclear Science Symposium Conference 2009, Orlando, FL, USA, 25–31 October 2009. doi:10.1109/NSSMIC.2009.5401842. 567. Al-Qudsi, B.; Ameri, A.; Bangert, A. Low cost highly precision time interval measurement unit for radar applications. In Proceedings of the 2012 the 7th German Microwave Conference, GeMiC 2012, Ilmenau, Germany, 12–14 March 2012. 568. Vasile, S.; Lipson, J. Low-cost LADAR imagers. In Proceedings of the Laser Radar Technology and Applications XIII, Orlando, FL, USA, 19–20 March 2008, doi:10.1117/12.781586. 569. Homulle, H.; Regazzoni, F.; Charbon, E. 200 MS/s ADC implemented in a FPGA employing TDCs. In Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2015, Monterey, CA, USA, 22 –24 February 2015. doi:10.1145/2684746.2689070. 570. Homulle, H.; Visser, S.; Charbon, E. A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications. IEEE Trans. Circuits Syst. -Regul. Pap. 2016, 63, 1854–1865. doi:10.1109/TCSI.2016.2599927. Computation 2019, xx, 5 56 of 115 571. Husemann, R.; Majolo, M.; Guimaraes, V.; Susin, A.; Roesler, V.; Lima, J.V. Hardware Integrated Quantization Solution for Improvement of Computational H.264 Encoder Module. In Proceedings of the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, Complutense Univ Madrid, Comp Sci Sch, Madrid, Spain, 27–29 September 2010. 572. Amer, I.; Badawy, W.; Jullien, G. A proposed hardware reference model for spatial transformation and quantization in H.264. J. Vis. Commun. Image Represent. 2006, 17, 533–552. doi:10.1016/j.jvcir.2005.05.011. 573. Husemann, R.; Majolo, M.; Susin, A.; Roesler, V.; de Lima, J.V. Highly Efficient Transforms Module Solution for a H.264/SVC Encoder. In Proceedings of the IEEE Annual Symposium on VLSI (ISVLSI), Telecommunicat Syst & Networks Dept, Lixouri, Greece, 5–7 July 2010. doi:10.1109/ISVLSI.2010.87. 574. Sanjeevannanavar, S.; Nagamani, A. Efficient design and FPGA implementation of JPEG encoder using verilog HDL. In Proceedings of the International Conference on Nanoscience, Engineering and Technology, ICONSET 2011, Chennai, India, 28–30 November 2011. doi:10.1109/ICONSET.2011.6168038. 575. De Silva, A.M.; Bailey, D.G.; Punchihewa, A. Exploring the Implementation of JPEG Compression on FPGA. In Proceedings of the 6th International Conference on Signal Processing and Communication Systems (ICSPCS), Gold Coast, Australia, 12–14 December 2012. 576. Szadkowski, Z. Front-End Board with Cyclone V as a Test High-Resolution Platform for the Auger_Beyond_2015 Front End Electronics. IEEE Trans. Nucl. Sci. 2015, 62, 985–992. doi:10.1109/TNS.2015.2426059. 577. Szadkowski, Z. Analysis of the efficiency of the spectral DCT trigger in arrays of surface detectors. In Proceedings of the 33rd International Cosmic Rays Conference, ICRC 2013, Rio de Janeiro, Brazil, 2–9 July 2013. 578. Szadkowski, Z. A spectral 1st level FPGA trigger for detection of very inclined showers based on a 16-point discrete cosine transform for the Pierre Auger Observatory. Nucl. Instruments Methods Phys. Res. Sect. -Accel. Spectrometers Detect. Assoc. Equip. 2009, 606, 330–343. doi:10.1016/j.nima.2009.03.255. 579. Szadkowski, Z. Trigger Board for the Auger Surface Detector With 100 MHz Sampling and Discrete Cosine Transform. IEEE Trans. Nucl. Sci. 2011, 58, 1692–1700. doi:10.1109/TNS.2011.2115252. 580. Jayalaxmi, H.; Ramachandran, S. An Efficient Hardware Realization of DCT Based Color Image Mosaicing System on FPGA. In Proceedings of the Conference on Computational Methods in Systems and Software (CoMeSySo), Szczecin, Poland, 12–14 September 2018. doi:10.1007/978-3-030-00184-1_18. 581. Houser, M.W.; Karantzalis, P. Chapter 469 - A digitally tuned anti-aliasing/reconstruction filter simplifies high performance DSP design. In Analog Circuit Design; Dobkin, B., Hamburger, J., Eds.; Newnes: Oxford, UK, 2015; pp. 1007–1008. doi:https://doi.org/10.1016/B978-0-12-800001-4.00469-5. 582. Abd Halim, W.; Abd Rahim, N.; Azri, M. Selective Harmonic Elimination for a Single-Phase 13-level TCHB Based Cascaded Multilevel Inverter Using FPGA. J. Power Electron. 2014, 14, 488–498. doi:10.6113/JPE.2014.14.3.488. 583. Subhashini, M.; Latha, P.; Bhagyaveni, M. Comparative analysis of harmonic distortion of a solar PV fed cascaded H-bridge multilevel inverter controlled by FPGA and diode clamped inverter. Indian J. Sci. Technol. 2015, 8. doi:10.17485/ijst/2015/v8i16/68652. 584. Halim, W.; Tengku, A.T.; Applasamy, K.; Jidin, A. Selective harmonic elimination based on newton-raphson method for cascaded H-bridge multilevel inverter. Int. J. Power Electron. Drive Syst. 2017, 8, 1193–1202. doi:10.11591/ijpeds.v8i3.pp1193-1202. 585. Porselvi, T.; Deepa, K.; Muthu, R. FPGA based selective harmonic elimination technique for multilevel inverter. Int. J. Power Electron. Drive Syst. 2018, 9, 166–173. doi:10.11591/ijpeds.v9n1.pp166-173. 586. Hwu, K.I.; Tu, W.C. Controllable and Dimmable AC LED Driver Based on FPGA to Achieve High PF and Low THD. IEEE Trans. Ind. Informatics 2013, 9, 1330–1342. doi:10.1109/TII.2012.2226042. 587. Hwu, K.I.; Tu, W.C.; Fang, Y.T. Dimmable AC LED Driver With Efficiency Improved Based on Switched LED Module. J. Disp. Technol. 2014, 10, 171–181. doi:10.1109/JDT.2013.2290624. 588. Hwu, K.I.; Shieh, J.J. Dimmable AC LED Driver Based on Series Drive. J. Disp. Technol. 2016, 12, 1097–1105. doi:10.1109/JDT.2016.2558041. 589. Hwu, K.I.; Yau, Y.T. Series-Based AC LED Driver with Efficiency Improved. Electr. Power Components Syst. 2018, 46, 637–646. doi:10.1080/15325008.2018.1463579. 590. Ramachandran, S.; Srinivasan, S. Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization. J. Syst. Archit. 2005, 51, 435–450. doi:10.1016/j.sysarc.2004.07.008. Computation 2019, xx, 5 57 of 115 591. Li, M.; Zhang, P.; Zhu, C.; Jia, H.; Xie, X.; Cong, J.; Gao, W. High Efficiency VLSI Implementation of an Edge-directed Video Up-scaler Using High Level Synthesis. In Proceedings of the IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, USA, 9–12 January 2015. 592. Safinaz, S.; Kumar, Ravi A., V. VLSI Realization of Lanczos Interpolation for a Generic Video Scaling Algorithm. In Proceedings of the 1st IEEE International Conference on Recent Advances in Electronics and Communication Technology (ICRAECT), Bengaluru, India, 16–17 March 2017. doi:10.1109/ICRAECT.2017.37. 593. Pastuszak, G.; Trochimiuk, M. Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder. J.-Real-Time Image Process. 2016, 11, 663–673. doi:10.1007/s11554-014-0422-1. 594. Pastuszak, G.; Trochimiuk, M. Algorithm and architecture design of the motion estimation for the H.265/HEVC 4K-UHD encoder. J.-Real-Time Image Process. 2016, 12, 517–529. doi:10.1007/s11554-015-0516-4. 595. Lung, C.Y.; Shen, C.A. A High-Throughput interpolator for Fractional Motion Estimation in High Efficient Video Coding (HEVC) systems. In Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Japan, 17–20 November 2014. 596. Shi, G.; Liu, W.; Zhang, L.; Li, F. An Efficient Folded Architecture for Lifting-Based Discrete Wavelet Transform. IEEE Trans. Circuits Syst. -Express Briefs 2009, 56, 290–294. doi:10.1109/TCSII.2009.2015393. 597. Jyotheswar, J.; Mahapatra, S. Efficient FPGA implementation of DWT and modified SPIHT for lossless image compression. J. Syst. Archit. 2007, 53, 369–378. doi:10.1016/j.sysarc.2006.11.009. 598. Kumar, C.A.; Madhavi, B.K.; Lalkishore, K. Pipeline and Parallel Processor Architecture for Fast Computation of 3D-DWT using Modified Lifting Scheme. In Proceedings of the IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), Dept Elect & Commun Engn, Chennai, India, 23–25 March 2016. 599. Ibraheem, M.; Hachicha, K.; Ahmed, S.; Lambert, L.; Garda, P. High-throughput parallel DWT hardware architecture implemented on an FPGA-based platform. J. Real Time Image Process. 2017, pp. 1–15. doi:10.1007/s11554-017-0711-6. 600. Mohammad, K.; Agaian, S. Efficient FPGA implementation of convolution. In Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, San Antonio, TX, USA, 11–14 October 2009. doi:10.1109/ICSMC.2009.5346737. 601. Song, P.F.; Pan, J.S.; Yang, C.S.; Lee, C.Y. An Efficient FPGA-Based Accelerator Design for Convolution. In Proceedings of the 8th IEEE International Conference on Awareness Science and Technology (iCAST), Chaoyang Univ Technol, Taichung, Taiwan, 8–10 November 2017. 602. Xue, D.; DeBrunner, L.S. An Effective Hardware Implementation of 1024-point Linear Convolution Based on Hirschman Optimal Transform. In Proceedings of the 51st IEEE Asilomar Conference on Signals Systems and Computers, Pacific Grove, CA, USA, 29 October–1 November 2017. 603. Wang, H.; Shao, M.; Liu, Y.; Zhao, W. Enhanced Efficiency 3D Convolution Based on Optimal FPGA Accelerator. IEEE Access 2017, 5, 6909–6916. doi:10.1109/ACCESS.2017.2699229. 604. Chan, A.; Roberts, G. A jitter characterization system using a component-invariant vernier delay line. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2004, 12, 79–95. doi:10.1109/TVLSI.2003.820531. 605. Aloisio, A.; Cevenini, F.; Giordano, R.; Izzo, V. Characterizing Jitter Performance of Multi Gigabit FPGA-Embedded Serial Transceivers. IEEE Trans. Nucl. Sci. 2010, 57, 451–455. doi:10.1109/TNS.2009.2032291. 606. Zielinski, M.; Kowalski, M.; Frankowski, R.; Chaberski, D.; Grzelak, S.; Wydzgowski, L. Accumulated jitter measurement of standard clock oscillators. Metrol. Meas. Syst. 2009, 16, 259–266. 607. Rethinam, S.; Rajagopalan, S.; Janakiraman, S.; Arumugham, S.; Amirtharajan, R. Jitters through dual clocks: An effective Entropy Source for True Random Number Generation. In Proceedings of the 8th International Conference on Computer Communication and Informatics (ICCCI), Coimbatore, India, 4–6 January 2018. 608. Marghescu, A.; Svasta, P. Into Generating True Random Numbers - a Practical Approach using FPGA. In Proceedings of the 21st IEEE International Symposium for Design and Technology in Electronic Packaging (SIITME), Brasov,Romania, 22–25 October 2015. 609. Tuncer, T.; Avaroglu, E.; Turk, M.; Ozer, A.B. Implementation of Non-periodic Sampling True Random Number Generator on FPGA. Inf.-Midem-J. Microelectron. Electron. Components Mater. 2014, 44, 296–302. 610. Smith, J. Introduction to Digital Filters: With Audio Applications; Music Signal Processing Series; W3K: Branson, MO, United States, 2007; Computation 2019, xx, 5 58 of 115 611. Wickert, M.A. Introduction to Signals and Systems. Available online: http://www.eas.uccs.edu/~mwickert/ ece2610/lecture_notes/ece2610_chap1.pdf (accessed on 4 November 2019). 612. Longa, P.; Miri, A. Area-efficient FIR filter design on FPGAs using distributed arithmetic. In Proceedings of the 6th IEEE International Symposium on Signal Processing and Information Technology, Vancouver, BC, Canada, 28–30 August 2006. doi:10.1109/ISSPIT.2006.270806. 613. Zhou, Y.; Shi, P. Distributed arithmetic for FIR filter implementation on FPGA. In Proceedings of the 2nd International Conference on Multimedia Technology, ICMT 2011, Hangzhou, China, 26–28 July 2011. doi:10.1109/ICMT.2011.6003032. 614. Mu, N.; Liu, G. Study on the FPGA implementation algorithm of effictive FIR filter based on remainder theorem. In Proceedings of the 2012 2nd International Conference on Consumer Electronics, Communications and Networks, CECNet 2012, Three Gorges, China, 21–23 April 2012. doi:10.1109/CECNet.2012.6201698. 615. Singhal, S.K.; Mohanty, B.K. Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic. J. Circuits Syst. Comput. 2016, 25. doi:10.1142/S0218126616500730. 616. Shanthala, S.; Kulkarni, S. High speed and low power FPGA implementation of FIR filter for DSP applications. Eur. J. Sci. Res. 2009, 31, 19–28. 617. Sreerama, R.G.; Chandrashekara, R.P. Design and FPGA implementation of high speed, low power digital up converter for power line communication systems. Eur. J. Sci. Res. 2009, 25, 234–249. 618. Sridevi, S.; Chowdary, A. Low power pilpelined FIR filter with enhanced row bypassing multiplier. Int. J. Commun. Antenna Propag. 2011, 1, 132–135. 619. Catlin, D. Estimation, Control, and the Discrete Kalman Filter; Applied Mathematical Sciences, Springer New York, 2012. 620. Lee, C.; Salcic, Z. High-performance FPGA-based implementation of Kalman filter. Microprocess. Microsyst. 1997, 21, 257–265. doi:10.1016/S0141-9331(97)00040-9. 621. Chen, G.; Guo, L. A high-performance hardware implementation of Kalman Filter. WSEAS Trans. Circuits Syst. 2005, 4, 1254–1259. 622. Suman, J.; Seventline, J. An efficient radar signal denoising for target detection using extended kalman filter. J. Theor. Appl. Inf. Technol. 2017, 95, 6585–6596. 623. Sabatelli, S.; Galgani, M.; Fanucci, L.; Rocchi, A. A Double-Stage Kalman Filter for Orientation Tracking With an Integrated Processor in 9-D IMU. IEEE Trans. Instrum. Meas. 2013, 62, 590–598. doi:10.1109/TIM.2012.2218692. 624. Sabatelli, S.; Galgani, M.; Fanucci, L.; Rocchi, A. A double stage Kalman filter for sensor fusion and orientation tracking in 9D IMU. In Proceedings of the 2012 IEEE Sensors Applications Symposium, SAS 2012, Brescia, Italy, 7–9 February 2012. doi:10.1109/SAS.2012.6166315. 625. Waheed, O.; Elfadel, I. FPGA sensor fusion system design for IMU arrays. In Proceedings of the 20th Symposium on Design, Test, Integration and Packaging of MEMS and MOEMS, DTIP 2018, Roma, Italy, 22–25 May 2018. doi:10.1109/DTIP.2018.8394227. 626. Reza, A. Adaptive noise filtering of image sequences in real time. WSEAS Trans. Syst. 2013, 12, 189–201. 627. Kara, G.; Orduyilmaz, A.; Serin, M.; Yildirim, A. Real Time Kalman Filter Implementation on FPGA Environment. In Proceedings of the 25th Signal Processing and Communications Applications Conference (SIU), Antalya, Turkey, 15–18 May 2017. 628. Abdelfatah, W.F.; Georgy, J.; Iqbal, U.; Noureldin, A. FPGA-Based Real-Time Embedded System for RISS/GPS Integrated Navigation. Sensors 2012, 12, 115–147. doi:10.3390/s120100115. 629. Jain, T.; Bansod, P.; Singh, K.C.; Mewara, M. Reconfigurable hardware for median filtering for image processing applications. In Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, ICETET 2010, Goa, India, 19–21 November 2010. doi:10.1109/ICETET.2010.172. 630. Xu, D.P.; Li, C.S. Design of median filter for digital image based on FPGA. Dianzi Qijian/J. Electron Devices 2006, 29, 1114–1117. 631. Fernandez, V.; Martinez-Navarrete, D.; Ventura-Arizmendi, C.; Paxtian, Z.; Ramirez-Rodriguez, J. Digital circuit architecture for a median filter of grayscale images based on sorting network. Int. J. Circuits, Syst. Signal Process. 2011, 5, 297–304. 632. Abadi, H.; Samavi, S.; Karimi, N. Low complexity median filter hardware for image impulsive noise reduction. J. Inf. Syst. Telecommun., 2, 85–94. doi:10.7508/jist.2014.02.003. Computation 2019, xx, 5 59 of 115 633. Matsubara, T.; Moshnyaga, V.; Hashimoto, K. A low-complexity and low power median filter design. In Proceedings of the 18th International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2010, Chengdu, China, 6–8 December 2010. doi:10.1109/ISPACS.2010.5704684. 634. Kalali, E.; Hamzaoglu, I. A Low Energy 2D Adaptive Median Filter Hardware. In Proceedings of the Conference on Design Automation Test in Europe (DATE), Alpexpo Congress Center, Grenoble, France, 9–13 March 2015. 635. Li, Y.; Su, G. Design of High Speed Median Filter Based on Neighborhood Processor. In Proceedings of the 6th IEEE International Conference on Software Engineering and Service Science (ICSESS), China Hall Sci & Technol, Beijing, China, 23–25 September 2015. 636. Luo, H.B.; Shi, Z.L.; Hui, Y.; Zhou, G.C. Real-time large window -sized 2D median filter based on multi - Phased grouping and sorting network. Hongwai Yu Jiguang Gongcheng/Infrared Laser Eng. 2008, 37, 935–939. 637. Wenjing, G.; Kemao, Q.; Haixia, W.; Feng, L.; Soon, S.H.; Sing, C.L. General Structure for Real-time Fringe Pattern Preprocessing and Implementation of Median Filter and Average Filter on FPGA. In Proceedings of the 9th International Symposium on Laser Metrology, Singapore, Singapore, 30 June–2 July 2008. doi:10.1117/12.814525. 638. Haykin, S.; Widrow, B.; Sons, J.W. Least-Mean-Square Adaptive Filters; Adaptive and Cognitive Dynamic Systems: Signal Processing, Learning, Communications and Control; Wiley: Hoboken, NJ, USA, 2003. 639. Chen, K.H.; Vu, H.S.; Weng, K.Y.; Huang, J.H.; Tsai, Y.T.; Liu, Y.C.; Wang, W.H. Design of An Efficient Active Noise Cancellation Circuit for In-ear Headphones. In Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Ishigaki, Japan, 17–20 November 2014. 640. Niras, C.; Kong, Y. LMS algorithm implementation in FPGA for noise reduction and echo cancellation. Institution of Engineering and Technology, 2012, Vol. 2012, pp. 193–195. In Proceedings of the 4th International Conference on Advances in Recent Technologies in Communication and Computing, ARTCom 2012, Bangalore, India, 19–20 October 2012. doi:10.1049/cp.2012.2525. 641. Qian, R.; Xia, W.; He, Z.; Liu, C. A low-cost echo cancellation algorithm in DTMB on-channel repeater. In Proceedings of the 2010 2nd International Conference on Signal Processing Systems, ICSPS 2010, Dalian, China, 5–7 July 2010. doi:10.1109/ICSPS.2010.5555698. 642. Shaikh, S.; Pujari, S. Migration from Microcontroller to FPGA based SoPC Design Case study: LMS Adaptive Filter Design on Xilinx Zynq FPGA with Embedded ARM Controller. In Proceedings of the International Conference on Automatic Control and Dynamic Optimization Techniques (ICACDOT), Int Inst Informat Technol, Pune, India, 9–10 September 2016. 643. Rasu, R.; Sundaram, P.S.; Santhiyakumari, N. FPGA based non-invasive heart rate monitoring system for detecting abnormalities in fetal. In Proceedings of the 2015 International Conference on Signal Processing And Communication Engineering Systems (SPACES), Guntur, India, 2–3 January 2015. 644. Subha, T.; Reshma, V. A Study of Non-invasive Heart Rate Monitoring System by using FPGA. In Materials Today: Proceedings; Elsevier Ltd.: Amsterdam, The The Netherlands, 2017; Volume 4, pp. 4228–4238. doi:10.1016/j.matpr.2017.02.126. 645. Ma, Z.G.; Wen, B.Y.; Zhou, H.; Bai, L.Y. CIC filter theory in DDC and implementation by using FPGA. Wuhan Univ. J. Nat. Sci. 2004, 9, 899–903. 646. Bhakthavatchalu, R.; Karthika, V.S.; Ramesh, L.; Aamani, B. Design of Optimized CIC Decimator and Interpolator in FPGA. In Proceedings of the IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing (iMac4s), Kottayam, India, 22–23 February 2013. 647. Elamaran, V.; Vaishnavi, R.; Rozario, A.M.; Joseph, S.M.; Cherian, A. CIC for decimation and interpolation using xilinx system generator. In Proceedings of the 2nd IEEE International Conference on Communications and Signal Processing (ICCSP), Adhiparasakthi Engn Coll, Dept Elect & Commun Engn, Melmaruvathur, India, 3–5 April 2013. 648. Vaishnavi, R.; Elamaran, V. Implementation of CIC filter for DUC/DDC. Int. J. Eng. Technol. 2013, 5, 357–365. 649. Liu, P.; Li, X.; Li, H.; Su, Z.; Zhang, H. Implementation of High Time Delay Accuracy of Ultrasonic Phased Array Based on Interpolation CIC Filter. Sensors 2017, 17. doi:10.3390/s17102322. 650. Milic, L.; Lutovac, M. Efficient algorithm for the design of high-speed elliptic IIR filters. AEU-Int. J. Electron. Commun. 2003, 57, 255–262. doi:10.1078/1434-8411-54100168. 651. Bhattacharyya, A.; Sharma, P.; Murali, N.; Murty, S.A.V.S. Development of FPGA based IIR Filter Implementation of 2-degree of freedom PID controller. In Proceedings of the Annual IEEE India Conference Computation 2019, xx, 5 60 of 115 - Engineering Sustainable Solutons, BITS Pilani, Hyderabad Campus, Hyderabad, India, 16–18 December 2011. 652. Toledo-Perez, D.; Martinez-Prado, M.; Rodriguez-Resendiz, J.; Tovar, A.S.; Marquez-Gutierrez, M. IIR Digital Filter Design Implemented on FPGA for Myoelectric Signals. In Proceedings of the 13th International Engineering Congress, CONIIN 2017, Querétaro, Mexico, 15–19 May 2017. doi:10.1109/CONIIN.2017.7968184. 653. Zhang, Y.; Zheng, D.; Xing, W.; Fan, S. Design of IIR filter in capacitive rotary position sensor based on FPGA. In Proceedings of the 8th IEEE International Symposium on Instrumentation and Control Technology, ISICT 2012, London, UK, 11–13 July 2012, doi:10.1109/ISICT.2012.6291598. 654. Yu, J.y.; Huang, D.; Pei, N.; Zhao, S.; Guo, J.; Xu, Y. CORDIC-based design of matched filter weighted algorithm for pulse compression system. In Proceedings of the IEEE 11th International Conference on Signal Processing (ICSP), Beijing, China, 21–25 October 2012. 655. Hai-bo, L.; An-bo, J.; Ling-yun, X.; Chun-yan, S. Edge Detection Using Matched Filter. In Proceedings of the 27th Chinese Control and Decision Conference (CCDC), Qingdao, China, 23–25 May 2015. 656. Kadhim, A.K.A.R.; Hussain, A.A.A. Hierarchical matched filter based on FPGA for mobile systems. Comput. Electr. Eng. 2009, 35, 549–555. doi:10.1016/j.compeleceng.2008.08.006. 657. Xu, Y.; Shuang, K. Implementation of high order matched filter on a FPGA chip. In Proceedings of the 4th International Congress on Image and Signal Processing, CISP 2011, Shanghai, China, 15–17 October 2011. doi:10.1109/CISP.2011.6100756. 658. Kniola, M.; Kawalec, A. Matched filter module as an application of modern FPGA in radar systems. In Proceedings of the Annual Radioelectronic Systems Conference, Jachranka, Poland, 14–16 November 2017. doi:10.1117/12.2317907. 659. Annadurai, S. Fundamentals of Digital Image Processing. Available online: https://www.cis.rit.edu/class/ simg361/Notes_11222010.pdf (accessed on 31 October 2019). 660. Scharstein, D. View Synthesis Using Stereo Vision; Lecture Notes in Computer Science; Springer: Berlin/Heidelberg, Germany, 2003. 661. Jin, S.; Cho, J.; Pham, X.D.; Lee, K.M.; Park, S.K.; Kim, M.; Jeon, J.W. FPGA Design and Implementation of a Real-Time Stereo Vision System. IEEE Trans. Circuits Syst. Video Technol. 2010, 20, 15–26. doi:10.1109/TCSVT.2009.2026831. 662. Ttofis, C.; Kyrkou, C.; Theocharides, T. A Low-Cost Real-Time Embedded Stereo Vision System for Accurate Disparity Estimation Based on Guided Image Filtering. IEEE Trans. Comput. 2016, 65, 2678–2693. doi:10.1109/TC.2015.2506567. 663. Chang, Q.; Maruyama, T. Real-Time Stereo Vision System: A Multi-Block Matching on CUP. IEEE Access 2018, 6, 42030–42046. doi:10.1109/ACCESS.2018.2859445. 664. Ding, J.; Liu, J.; Zhou, W.; Yu, H.; Wang, Y.; Gong, X. Real-time stereo vision system using adaptive weight cost aggregation approach. Eurasip J. Image Video Process. 2011. doi:10.1186/1687-5281-2011-20. 665. Fife, W.S.; Archibald, J.K. Improved Census Transforms for Resource-Optimized Stereo Vision. IEEE Trans. Circuits Syst. Video Technol. 2013, 23, 60–73. doi:10.1109/TCSVT.2012.2203197. 666. Tavera-Vaca, C.A.; Almanza-Ojeda, D.L.; Ibarra-Manzano, M.A. Analysis of the efficiency of the census transform algorithm implemented on FPGA. Microprocess. Microsyst. 2015, 39, 494–503. doi:10.1016/j.micpro.2015.08.002. 667. Hadjitheophanous, S.; Ttofis, C.; Georghiades, A.S.; Theocharides, T. Towards Hardware Stereoscopic 3D Reconstruction A Real-Time FPGA Computation of the Disparity Map. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden, Germany, 8–12 March 2010. 668. Michailidis, G.T.; Pajarola, R.; Andreadis, I. High Performance Stereo System for Dense 3-D Reconstruction. IEEE Trans. Circuits Syst. Video Technol. 2014, 24, 929–941. doi:10.1109/TCSVT.2013.2290575. 669. Lentaris, G.; Stamoulias, I.; Soudris, D.; Lourakis, M. HW/SW Codesign and FPGA Acceleration of Visual Odometry Algorithms for Rover Navigation on Mars. IEEE Trans. Circuits Syst. Video Technol. 2016, 26, 1563–1577. doi:10.1109/TCSVT.2015.2452781. 670. Matthies, L.; Maimone, M.; Johnson, A.; Cheng, Y.; Willson, R.; Villalpando, C.; Goldberg, S.; Huertas, A.; Stein, A.; Angelova, A. Computer vision on Mars. Int. J. Comput. Vis. 2007, 75, 67–92. doi:10.1007/s11263-007-0046-z. Computation 2019, xx, 5 61 of 115 671. Cho, J.; Mirzaei, S.; Oberg, J.; Kastner, R. FPGA-Based face detection system haar classifiers. In Proceedings of the 7th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA’09, Monterey, CA, USA, 22–24 February 2009. doi:10.1145/1508128.1508144. 672. Gajjar, A.; Yang, X.; Wu, L.; Koc, H.; Unwala, I.; Zhang, Y.; Feng, Y. An FPGA Synthesis of Face Detection Algorithm using HAAR Classifier. In Proceedings of the 2nd International Conference on Algorithms, Computing and Systems (ICACS), Beijing, China, 27–29 July 2018. doi:10.1145/3242840.3242851. 673. Luo, R.; Liu, H.H. Design and implementation of efficient hardware solution based sub-window architecture of Haar classifiers for real-time detection of face biometrics. In Proceedings of the 2010 IEEE International Conference on Mechatronics and Automation, ICMA 2010, Xi’an, China, 4–7 August 2010. doi:10.1109/ICMA.2010.5589229. 674. Cho, J.; Benson, B.; Mirzaei, S.; Kastner, R. Parallelized Architecture of Multiple Classifiers for Face Detection. In Proceedings of the 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Boston, MA, USA, 7–9 July 2009. doi:10.1109/ASAP.2009.38. 675. Nguyen, D.; Halupka, D.; Aarabi, P.; Sheikholeslami, A. Real-time face detection and lip feature extraction using field-programmable gate arrays. IEEE Trans. Syst. Man Cybern. Part -Cybern. 2006, 36, 902–912. doi:10.1109/TSMCB.2005.862728. 676. Jin, S.; Kim, D.; Nguyen, T.T.; Kim, D.; Kim, M.; Jeon, J.W. Design and Implementation of a Pipelined Datapath for High-Speed Face Detection Using FPGA. IEEE Trans. Ind. Informatics 2012, 8, 158–167. doi:10.1109/TII.2011.2173943. 677. Matai, J.; Irturk, A.; Kastner, R. Design and Implementation of an FPGA-based Real-Time Face Recognition System. In Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Campus Univ Utah, Salt Lake City, UT, USA, 1–3 May 2011. doi:10.1109/FCCM.2011.53. 678. Jin, S.; Kim, D.; Nguyen, T.T.; June, B.; Kim, D.; Jeon, J.W. An FPGA-based Parallel Hardware Architecture for Real-time Face Detection using a Face Certainty Map. In Proceedings of the 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Boston, MA, USA, 7–9 July 2009. doi:10.1109/ASAP.2009.36. 679. Wang, N.J.; Chang, S.C.; Chou, P.J. A Real-time Multi-face Detection System Implemented on FPGA; IEEE: 5, 2012. In Proceedings of the IEEE International Symposium on Intelligent Signal Processing and Communications Systems (ISPACS), New Taipei, Taiwan, 4–7 November 2012. 680. Chen, Y.P.; Liu, C.H.; Chou, K.Y.; Wang, S.Y. Real-Time and low-memory multi-face detection system design based on naive Bayes classifier using FPGA. In Proceedings of the 2016 International Automatic Control Conference, CACS 2016, Taichung, Taiwan, 9–11 November 2016. doi:10.1109/CACS.2016.7973875. 681. Xiao, J.; Zhang, J.; Zhu, M.; Yang, J.; Shi, L. Fast AdaBoost-Based Face Detection System on a Dynamically Coarse Grain Reconfigurable Architecture. IEICE Trans. Inf. Syst. 2012, E95D, 392–402. doi:10.1587/transinf.E95.D.392. 682. Irgens, P.; Bader, C.; Le, T.; Saxena, D.; Ababei, C. An efficient and cost effective FPGA based implementation of the Viola-Jones face detection algorithm. HardwareX 2017, 1, 68–75. doi:10.1016/j.ohx.2017.03.002. 683. Ahilan, A.; James, E.A.K. Design and Implementation of Real time Car Theft Detection in FPGA. In Proceedings of the 3rd International Conference on Advanced Computing (ICoAC), Anna Univ, Dept Comp Technol, Chennai, India, 14–16 December 2011. 684. Abbas, S.A.; Vicithra, G. Actualization of Face Detection in FPGA using Neural Network. In Proceedings of the IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), Dept Elect & Commun Engn, Chennai, India, 23–25 March 2016. 685. Chaple, G.; Daruwala, R.D. Design of Sobel Operator based Image Edge Detection Algorithm on FPGA. In Proceedings of the 3rd International Conference on Communications and Signal Processing (ICCSP), Melmaruvathur, India, 3–5 April 2014. 686. Khalid, A.R.; Paily, R. FPGA implementation of high speed and low power architectures for image segmentation using sobel operators. J. Circuits Syst. Comput. 2012, 21. doi:10.1142/S0218126612500508. 687. Koyuncu, I.; Cetin, O.; Katircioglu, F.; Tuna, M. Edge Dedection Application With FPGA Based Sobel Operator. In Proceedings of the 23nd Signal Processing and Communications Applications Conference (SIU), Inonu Univ, Malatya, Turkey, 16–19 May 2015. Computation 2019, xx, 5 62 of 115 688. Nausheen, N.; Seal, A.; Khanna, P.; Halder, S. A FPGA based implementation of Sobel edge detection. Microprocess. Microsyst. 2018, 56, 84–91. doi:10.1016/j.micpro.2017.10.011. 689. Ben Amara, A.; Pissaloux, E.; Atri, M. Sobel Edge Detection System Design and Integration on an FPGA Based HD Video Streaming Architecture. In Proceedings of the 11th International Design and Test Symposium (IDT), Hammamet, Tunisia, 18–20 December 2016. 690. Mahalle, A.G.; Shah, A.M. An Efficient Design for Canny Edge Detection Algorithm using Xilinx System Generator. In Proceedings of the 3rd IEEE International Conference on Research in Intelligent and Computing in Engineering (RICE), Univ Don Bosco, San Salvador, EI Salvador, 22–24 August 2018. 691. Mu, C.; Dong, Q.; Lian, J.; Peng, M. Embedded realization of a adaptive threshold edge detection base on Canny operator. In Proceedings of the International Conference on Vehicle and Mechanical Engineering and Information Technology, VMEIT 2014, Beijing, China, 19–20 February 2014. doi:10.4028/www.scientific.net/AMM.543-547.2766. 692. Xu, Z.; Yuan, K.; He, W. An implementation method of Canny edge detection algorithm on FPGA. In Proceedings of the 2011 International Conference on Electric Information and Control Engineering, ICEICE 2011, Wuhan, China, 15–17 April 2011. doi:10.1109/ICEICE.2011.5778193. 693. Yasri, I.; Hamid, N.H.; Ali, N.B.Z. VLSI Based Edge Detection Hardware Accelerator for Real Time Video Segmentation System. In Proceedings of the 4th International Conference on Intelligent and Advanced Systems (ICIAS) and A Conference of World Engineering, Science and Technology Congress (ESTCON), Kuala Lumpur, Malaysia, 12–14 June 2012. 694. Ontiveros-Robles, E.; Gonzalez-Vazquez, J.L.; Castro, J.R.; Castillo, O. A Hardware Architecture for Real-Time Edge Detection Based on Interval Type-2 Fuzzy Logic. In Proceedings of the IEEE International Conference on Fuzzy Systems (FUZZ-IEEE), Vancouver, BC, Canada, 24–29 July 2016. 695. Ontiveros-Robles, E.; Gonzalez Vazquez, J.; Castro, J.R.; Castillo, O. A FPGA-Based Hardware Architecture Approach for Real-Time Fuzzy Edge Detection. Nat.-Inspired Des. Hybrid Intell. Syst. 2017, 667, 517–539. doi:10.1007/978-3-319-47054-2_34. 696. Shukla, A.J.; Patel, V.; Gajjar, N. Implementation of Edge Detection Algorithms in Real Time on FPGA. In Proceedings of the 5th Nirma University International Conference on Engineering (NUiCONE), Ahmedabad, India, 26–28 November 2015. 697. Jianying, F.; Xin, C.; Zhigang, F.; Yao, F. The real time infrared image acquisition and processing system design based on FPGA. Int. J. Multimed. Ubiquitous Eng. 2016, 11, 297–308. doi:10.14257/ijmue.2016.11.2.29. 698. Anderson, S.; Dang, P.; Chau, P. Configurable hardware for image segmentation. In Proceedings of the Conference on Machine Vision Applications in Industrial Inspection VII, San Jose, CA, USA, 25–26 January 1999. doi:10.1117/12.341139. 699. Raj, A.S.M.; Jose, C.; Supriya, M.H. Hardware realization of canny edge detection algorithm for underwater image segmentation using field programmable gate arrays. J. Eng. Sci. Technol. 2017, 12, 2536–2550. 700. Kornaros, G. A soft multi-core architecture for edge detection and data analysis of microarray images. J. Syst. Archit. 2010, 56, 48–62. doi:10.1016/j.sysarc.2009.11.004. 701. Sterpone, L.; Violante, M. A new FPGA-based edge detection system for the gridding of DNA microarray images. In Proceedings of the 24th IEEE Instrumentation and Measurement Technology Conference, Warsaw, Poland, 1–3 May 2007. 702. Kyrkou, C.; Ttofis, C.; Theocharides, T. A Hardware Architecture for Real-Time Object Detection Using Depth and Edge Information. ACM Trans. Embed. Comput. Syst. 2013, 13. doi:10.1145/2539036.2539050. 703. Kyrkou, C.; Theocharides, T. Accelerating object detection via a visual-feature-directed search cascade: algorithm and field programmable gate array implementation. J. Electron. Imaging 2016, 25. doi:10.1117/1.JEI.25.4.041013. 704. Chen, S.L.; Tuan, M.C. VLSI Implementation of an Adaptive Block Partition Decision Object-Detection Design for Real-Time 4K2K Video Display. J. Disp. Technol. 2016, 12, 1570–1580. doi:10.1109/JDT.2016.2611617. 705. Naskar, R.; Chakraborty, R. Reversible Digital Watermarking: Theory and Practices; Synthesis Lectures on Information Security, Privacy, and Trust; Morgan & Claypool Publishers: San Rafael, California, USA, 2014. 706. Mohanty, S.P.; Kougianos, E. Real-time perceptual watermarking architectures for video broadcasting. J. Syst. Softw. 2011, 84, 724–738. doi:10.1016/j.jss.2010.12.012. Computation 2019, xx, 5 63 of 115 707. Mohanty, S.P.; Kougianos, E.; Cai, W.; Ratnani, M. VLSI Architectures of Perceptual Based Video Watermarking for Real-Time Copyright Protection. In Proceedings of the 10th International Symposium on Quality Electronic Design, San Jose, CA, USA, 16–18 March 2009. doi:10.1109/ISQED.2009.4810350. 708. Megalingam, R.K.; Krishnan, V.B.; Sarma, V.V.; Mithun, M.; Srikumar, R. Hardware Implementation of Low Power, High Speed DCT/IDCT Based Digital Image Watermarking. In Proceedings of the International Conference on Computer Technology and Development, Kota Kinabalu, Malaysia, 13–15 November 2009. doi:10.1109/ICCTD.2009.195. 709. ElAraby, W.S.; Madian, A.H.; Ashour, M.A.; Wahdan, A.M. Hardware Realization of DC Embedding Video Watermarking Technique based on FPGA. In Proceedings of the 22nd International Conference on Microelectronics (ICM 2010), Cairo, Egypt, 19–22 December 2010. doi:10.1109/ICM.2010.5696189. 710. Erozan, A.T.; Baskir, S.G.; Ors, B. Hardware/Software Codesign for Watermarking in DCT Domain. In Proceedings of the 21st Signal Processing and Communications Applications Conference (SIU), Cyprus, 24–26 April 2013. 711. Hampannavar, N.; Joseph, S.; Bidhul, C.; Arunachalam, V. FPGA implementation of DWT for audio watermarking application. Int. J. Eng. Technol. 2013, 5, 2196–2200. 712. Mulani, A.; Mane, P. Watermarking and cryptography based image authentication on reconfigurable platform. Bull. Electr. Eng. Informatics 2017, 6, 181–187. doi:10.11591/eei.v6i2.651. 713. Singh, G.M.; Kohli, M.S.; Diwakar, M. A Review of Image Enhancement Techniques in Image Processing. Technol. Innov. Res. 2013, 5, 2321–4135. 714. Reza, A. Realization of the Contrast Limited Adaptive Histogram Equalization (CLAHE) for real-time image enhancement. J. Vlsi Signal Process. Syst. Signal Image Video Technol. 2004, 38, 35–44. doi:10.1023/B:VLSI.0000028532.53893.82. 715. Chen, Y.; Zhu, M. Multiple sub-histogram equalization low light level image enhancement and realization on FPGA. Chin. Opt. 2014, 7, 225–233. doi:10.3788/CO.20140702.0225. 716. Li, X.; Ni, G.; Cui, Y.; Pu, T.; Zhong, Y. Real-time image histogram equalization using FPGA. In Proceedings of the Conference on Electronic Imaging and Multimedia Systems II, Beijing, China, 18–19 September 1998. doi:10.1117/12.319719. 717. Unal, B.; Akoglu, A. Resource Efficient Real-Time Processing of Contrast Limited Adaptive Histogram Equalization. In Proceedings of the 26th International Conference on Field-Programmable Logic and Applications (FPL), Ecole Polytechnique Federale de Lausanne, Lausanne, Switzerland, 29 August–2 September 2016. doi:10.1109/FPL.2016.7577362. 718. Hines, G.; Rahman, Z.U.; Jobson, D.; Woodell, G. DSP implementation of the retinex image enhancement algorithm. In Proceedings of the Visual Information Processing XIII, Orlando, FL, USA, 15–16 April 2004. doi:10.1117/12.544500. 719. Li, Y.; Zhang, H.; You, Y.; Sun, M. A multi-scale retinex implementation on FPGA for an outdoor application. In Proceedings of the 4th International Congress on Image and Signal Processing, CISP 2011, Shanghai, China, 15–17 October 2011. doi:10.1109/CISP.2011.6100606. 720. Raj, A.S.M.; Supriya, M.H. Underwater Image Enhancement using Single Scale Retinex on a Reconfigurable Hardware. In Proceedings of the International Symposium on Ocean Electronics (SYMPOL), Kochi, India, 18–20 November 2015. 721. Wang, B.J.; Liu, S.Q.; Cheng, Y.B. Real-time image processing system for IRFPA based on FPGA. Hongwai Yu Jiguang Gongcheng/Infrared Laser Eng. 2006, 35, 655–658. 722. ShengZhong.; DanShi.; BoWang.; KeLi. An Improved Implementation of Infrared Focal Plane Image Enhancement Algorithm Based on FPGA. In Proceedings of the 7th Symposium on Multispectral Image Processing and Pattern Recognition (MIPPR) - Parallel Processing of Images and Optimization and Medical Imaging Processing, Guilin, China, 4–6 November 2011. doi:10.1117/12.901839. 723. Paolini, A.; Bonnett, J.; Kozacik, S.; Kelmelis, E. Development of an Embedded Atmospheric Turbulence Mitigation Engine In Proceedings of the Conference on Long-Range Imaging II, Anaheim, CA, USA, 11 April 2017. doi:10.1117/12.2263204. 724. Droege, D.R.; Hardie, R.C.; Allen, B.S.; Dapore, A.J.; Blevins, J.C. A Real-Time Atmospheric Turbulence Mitigation and Super-Resolution Solution for Infrared Imaging Systems. In Proceedings of the Conference on Infrared Imaging Systems - Design, Analysis, Modeling, and Testing XXIII, Baltimore, MD, USA, 24–26 April 2012. doi:10.1117/12.920323. Computation 2019, xx, 5 64 of 115 725. Genovese, M.; Napoli, E. FPGA-based architecture for real time segmentation and denoising of HD video. J.-Real-Time Image Process. 2013, 8, 389–401. doi:10.1007/s11554-011-0238-1. 726. Appiah, K.; Hunter, A.; Dickinson, P.; Meng, H. Accelerated hardware video object segmentation: From foreground detection to connected components labelling. Comput. Vis. Image Underst. 2010, 114, 1282–1291. doi:10.1016/j.cviu.2010.03.021. 727. Ratnayake, K.; Amer, A. An FPGA-based implementation of spatio-temporal object segmentation. In Proceedings of the IEEE International Conference on Image Processing (ICIP 2006), Atlanta, GA, USA, 8–11 October 2006. doi:10.1109/ICIP.2006.312920. 728. Saha, S.; Uddin, K.H.; Islam, M.S.; Jahiruzzaman, M.; Hossain, A.B.M.A. Implementation of Simplified Normalized Cut Graph Partitioning Algorithm on FPGA for Image Segmentation. In Proceedings of the 8th International Conference on Software, Knowledge, Information Management and Applications (SKIMA), Dhaka, Bangladesh, 18–20 December 2014. 729. Craciun, S.; Kirchgessner, R.; George, A.D.; Lam, H.; Principe, J.C. A real-time, power-efficient architecture for mean-shift image segmentation. J.-Real-Time Image Process. 2018, 14, 379–394. doi:10.1007/s11554-014-0459-1. 730. Cho, J.U.; Jin, S.H.; Pham, X.D.; Jeon, J.W.; Byun, J.E.; Kang, H. A real-time object tracking system using a particle filter. In Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, Beijing, China, 9–13 October 2006. doi:10.1109/IROS.2006.282066. 731. Musavi, S.H.A.; Chowdhry, B.S.; Kumar, T.; Pandey, B.; Kumar, W. IoTs Enable Active Contour Modeling Based Energy Efficient and Thermal Aware Object Tracking on FPGA. Wirel. Pers. Commun. 2015, 85, 529–543. doi:10.1007/s11277-015-2753-z. 732. Liu, S.; Papakonstantinou, A.; Wang, H.; Chen, D. Real-time object tracking system on FPGAs. In Proceedings of the 2011 Symposium on Application Accelerators in High-Performance Computing, SAAHPC 2011, Knoxville, TN, USA, 19–20 July 2011. doi:10.1109/SAAHPC.2011.22. 733. Sivanantham, S.; Paul, N.; Iyer, R. Object tracking algorithm implementation for security applications. Far East J. Electron. Commun. 2016, 16, 1–13. doi:10.17654/EC016010001. 734. Zawadzki, A.; Gorgon, M. Automatically controlled pan-tilt smart camera with FPGA based image analysis system dedicated to real-time tracking of a moving object. J. Syst. Archit. 2015, 61, 681–692. doi:10.1016/j.sysarc.2015.08.003. 735. Zhuang, H.; Low, K.S.; Yau, W.Y. Multichannel Pulse-Coupled-Neural-Network-Based Color Image Segmentation for Object Detection. IEEE Trans. Ind. Electron. 2012, 59, 3299–3308. doi:10.1109/TIE.2011.2165451. 736. Kyrkou, C.; Theocharides, T. SCoPE: Towards a systolic array for SVM object detection. IEEE Embed. Syst. Lett. 2009, 1, 46–49. doi:10.1109/LES.2009.2034709. 737. Kyrkou, C.; Theocharides, T. Accelerating FPGA-based object detection via a visual information extraction cascade. In Proceedings of the 9th International Conference on Distributed Smart Cameras, ICDSC 2015, Seville, Spain, 8–11 September 2015. doi:10.1145/2789116.2789147. 738. Watson, D.; Morison, G.; Ahmadinia, A.; Buggy, T. A Novel Hardware Accelerator for Embedded Object Detection Applications. IEEE Trans. Emerg. Top. Comput. 2017, 5, 551–562. doi:10.1109/TETC.2016.2520888. 739. Mitsunari, K.; Yu, J.; Onoye, T.; Hashimoto, M. Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 2018, E101A, 1298–1307. doi:10.1587/transfun.E101.A.1298. 740. Kyrkou, C.; Theocharides, T. A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2011, 19, 1034–1047. doi:10.1109/TVLSI.2010.2048224. 741. Kyrkou, C.; Theocharides, T. A Parallel Hardware Architecture for Real-Time Object Detection with Support Vector Machines. IEEE Trans. Comput. 2012, 61, 831–842. doi:10.1109/TC.2011.113. 742. Zhao, J.; Huang, X.; Massoud, Y. An Efficient Real-Time FPGA Implementation for Object Detection. In Proceedings of the 12th IEEE International New Circuits and Systems Conference (IEEE NEWCAS), Trois-Rivieres, QC, Canada, 22–25 June 2014. 743. Bravo, I.; Mazo, M.; Lazaro, J.L.; Gardel, A.; Jimenez, P.; Pizarro, D. An Intelligent Architecture Based on Field Programmable Gate Arrays Designed to Detect Moving Objects by Using Principal Component Analysis. Sensors 2010, 10, 9232–9251. doi:10.3390/s101009232. Computation 2019, xx, 5 65 of 115 744. Chowdary, M.K.; Babu, S.S.; Babu, S.S.; Khan, H. FPGA Implementation of Moving Object Detection in Frames by Using Background Subtraction Algorithm. In Proceedings of the 2nd IEEE International Conference on Communications and Signal Processing (ICCSP), Adhiparasakthi Engn Coll, Dept Elect & Commun Engn, Melmaruvathur, India, 3–5 April 2013. 745. Pagire, V.R.; Kulkarni, C.V. FPGA Based Moving Object Detection. In Proceedings of the 4th International Conference on Computer Communication and Informatics (ICCCI), Coimbatore, India, 3–5 January 2014. 746. Khan, A.; Khan, M.U.K.; Bilal, M.; Kyung, C.M. Hardware Architecture and Optimization of Sliding Window Based Pedestrian Detection on FPGA for High Resolution Images by Varying Local Features. In Proceedings of the 23rd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Daejeon, Korea, 5–7 October 2015. 747. Miyoshi, T.; Shibata, T. A hardware-friendly object detection algorithm based on variable-block-size directional-edge histograms. In Proceedings of the 2010 World Automation Congress, WAC 2010, Kobe, Japan, 19–23 September 2010. 748. Khan, A.; Khan, M.U.K.; Bilal, M.; Kyung, C.M. A Hardware Accelerator for Real Time Sliding Window Based Pedestrian Detection on High Resolution Images. In Proceedings of the 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Daejeon, Korea, 5–7 October 2015. doi:10.1007/978-3-319-46097-0_3. 749. Zhang, P.; Xu, Z.; Liu, P.; Zhao, Y.; Wang, L.; Ma, Y.; Wang, J. Real time object detection based on FPGA with big data. In Proceedings of the 4th International Conference on Big Data Computing and Communications, BIGCOM 2018, Chicago, IL, USA, 7–9 August 2018. doi:10.1109/BIGCOM.2018.00015. 750. Genovese, M.; Napoli, E.; Petra, N. Hardware Performance Versus Video Quality Trade-off for Gaussian Mixture Model based Background Identification Systems. In Proceedings of the 6th International Conference on Digital Image Processing (ICDIP), Athens, Greece, 5–6 April 2014. doi:10.1117/12.2064404. 751. Genovese, M.; Napoli, E.; Petra, N. OpenCV compatible real time processor for background foreground identification. In Proceedings of the 22nd International Conference on Microelectronics (ICM 2010), Cairo, Egypt, 19–22 December 2010. doi:10.1109/ICM.2010.5696190. 752. Genovese, M.; Napoli, E. An FPGA-based real-time background identification circuit for 1080p video. In Proceedings of the 8th International Conference on Signal Image Technology and Internet Based Systems (SITIS), Univ Bourgogne, Sorrento, Italy, 25–29 November 2012. 753. Martin, J.; Zuloaga, A.; Cuadrado, C.; Lazaro, J.; Bidarte, U. Hardware implementation of optical flow constraint equation using FPGAs. Comput. Vis. Image Underst. 2005, 98, 462–490. doi:10.1016/j.cviu.2004.10.002. 754. Wei, Z.; Lee, D.J.; Nelson, B. FPGA-based real-time optical flow algorithm design and implementation. J. Multimed. 2007, 2, 38–45. doi:10.4304/jmm.2.5.38-45. 755. Gultekin, G.K.; Saranli, A. An FPGA based high performance optical flow hardware design for computer vision applications. Microprocess. Microsyst. 2013, 37, 270–286. doi:10.1016/j.micpro.2013.01.001. 756. Seyid, K.; Richaud, A.; Capoccia, R.; Leblebici, Y. FPGA-Based Hardware Implementation of Real-Time Optical Flow Calculation. IEEE Trans. Circuits Syst. Video Technol. 2018, 28, 206–216. doi:10.1109/TCSVT.2016.2598703. 757. Allaoui, R.; Mouane, H.H.; Asrih, Z.; Mars, S.; El Hajjouji, I.; El Mourabit, A. FPGA-based implementation of Optical flow Algorithm. In Proceedings of the 3rd International Conference on Electrical and Information Technologies (ICEIT), Rabat, Morocco, 15–18 November 2017. 758. Tagzout, S.; Achour, K.; Djekoune, O. Hough transform algorithm for FPGA implementation. In Proceedings of the IEEE Annual Workshop on Signal Processing Systems: Design and Implementation, Lafayette, IN, USA, 11–13 October 2000. doi:10.1109/SIPS.2000.886737. 759. Chen, Z.H.; Su, A.W.Y.; Sun, M.T. Resource-Efficient FPGA Architecture and Implementation of Hough Transform. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2012, 20, 1419–1428. doi:10.1109/TVLSI.2011.2160002. 760. Ruben Geninatti, S.; Benavides Benitez, J.I.; Hernandez Calvino, M.; Guil Mata, N.; Gomez Luna, J. FPGA Implementation of the Generalized Hough Transform. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, 9–11 December 2009. doi:10.1109/ReConFig.2009.78. Computation 2019, xx, 5 66 of 115 761. Djekoune, A.O.; Messaoudi, K.; Amara, K. Incremental circle hough transform: An improved method for circle detection. Optik 2017, 133, 17–31. doi:10.1016/j.ijleo.2016.12.064. 762. Pozzobon, N.; Montecassiano, F.; Zotto, P. A novel approach to Hough Transform for implementation in fast triggers. Nucl. Instruments Methods Phys. Res. Sect. -Accel. Spectrometers Detect. Assoc. Equip. 2016, 834, 81–97. doi:10.1016/j.nima.2016.07.020. 763. Johl, J. Configurable hardware implementation of H.264 decoder. In Proceedings of the Conference on Applications of Digital Image Processing XXVI, San Diego, CA, USA, 5–8 August 2003. doi:10.1117/12.508716. 764. Pastuszak, G.; Jakubowski, M. Adaptive Computationally Scalable Motion Estimation for the Hardware H.264/AVC Encoder. IEEE Trans. Circuits Syst. Video Technol. 2013, 23, 802–812. doi:10.1109/TCSVT.2012.2223791. 765. Nunez-Yanez, J.L.; Nabina, A.; Hung, E.; Vafiadis, G. Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2012, 20, 437–448. doi:10.1109/TVLSI.2010.2104166. 766. Pastuszak, G.; Jakubowski, M. Optimization of the Adaptive Computationally-Scalable Motion Estimation and Compensation for the Hardware H.264/AVC Encoder. J. Signal Process. Syst. Signal Image Video Technol. 2016, 82, 391–402. doi:10.1007/s11265-015-1021-5. 767. Ben Atitallah, A.; Arous, S.; Loukil, H.; Masmoudi, N. Hardware implementation and validation of the fast variable block size motion estimation architecture for H.264/AVC. Aeu-Int. J. Electron. Commun. 2012, 66, 701–710. doi:10.1016/j.aeue.2011.12.014. 768. Feki, O.; Grandpierre, T.; Masmoudi, N.; Akil, M. Optimized implementation of H.264/AVC motion estimation on a mixed architecture using synDEx-mix. Int. Rev. Comput. Softw. 2016, 11, 395–402. doi:10.15866/irecos.v11i5.8764. 769. Parlak, M.; Adibelli, Y.; Hamzaoglu, I. A Novel Computational Complexity and Power Reduction Technique for H.264 Intra Prediction. IEEE Trans. Consum. Electron. 2008, 54, 2006–2014. doi:10.1109/TCE.2008.4711266. 770. Roszkowski, M.; Pastuszak, G. Intra Prediction for the Hardware H.264/AVC High Profile Encoder. J. Signal Process. Syst. Signal Image Video Technol. 2014, 76, 11–17. doi:10.1007/s11265-013-0820-9. 771. Adibelli, Y.; Parlak, M.; Hamzaoglu, I. Computation and power reduction techniques for H.264 intra prediction. Microprocess. Microsyst. 2012, 36, 205–214. doi:10.1016/j.micpro.2011.12.003. 772. Wang, W.; Xie, Y.; Lin, T.; Hu, J. A fast mode decision algorithm and its hardware design for H.264/AVC intra prediction. Commun. Comput. Inf. Sci. 2014, 437, 48–56. 773. Korah, R.; Perinbam, J.R.P. FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder. J. Signal Process. Syst. Signal Image Video Technol. 2008, 53, 261–269. doi:10.1007/s11265-008-0163-0. 774. Pastuszak, G. Quantization selection in the high-throughput H. 264/AVC encoder based on the RD. In Proceedings of the Conference on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments, Poland, 27 May–2 June 2013. doi:10.1117/12.2034705. 775. Klosowski, M.; Pankiewicz, B.; Wojcikowski, M. DCT transform accelerator for image compression in vision Sensors [Akcelerator transformacji DCT do kompresji obrazu w sensorach wizyjnych]. Prz. Elektrotechniczny 2015, 91, 97–100. doi:10.15199/48.2015.09.25. 776. Souza, R.; Da, R.J.L.; Agostini, L.; Porto, R. Optimized 16x16 discrete cosine transform architecture for homogeneity-based H.264/AVC intra mode decision. In Proceedings of the 8th Southern Programmable Logic Conference, SPL 2012, Bento Goncalves, Brazil, 20–23 March 2012. doi:10.1109/SPL.2012.6211789. 777. Koumaras, H.; Kourtis, M.; Martakos, D. Benchmarking the encoding efficiency of H.265/HEVC and H.264/AVC. In Proceedings of the 2012 Future Network Mobile Summit (FutureNetw), Berlin, Germany, 4–6 July 2012 . 778. Srinivasarao, B.K.N.; Chakrabarti, I.; Ahmad, M.N. High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter. IET Circuits Devices Syst. 2015, 9, 377–383. doi:10.1049/iet-cds.2014.0310. 779. Zhou, D.; Wang, S.; Sun, H.; Zhou, J.; Zhu, J.; Zhao, Y.; Zhou, J.; Zhang, S.; Kimura, S.; Yoshimura, T.; Goto, S. 14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications. In Proceedings of the 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 31 January–4 Febuary 2016. doi:10.1109/ISSCC.2016.7418009. Computation 2019, xx, 5 67 of 115 780. Alcocer, E.; Gutierrez, R.; Lopez-Granado, O.; Malumbres, M. Design and implementation of an efficient hardware integer motion estimator for an HEVC video encoder. J. -Real-Time Image Process. 2016, pp. 1–11. doi:10.1007/s11554-016-0572-4. 781. Nalluri, P.; Alves, L.N.; Navarro, A. High speed sad architectures for variable block size motion estimation in hevc video coding. In Proceedings of the IEEE International Conference on Image Processing (ICIP), Paris, France, 27–30 October 2014. 782. Sun, H.; Zhou, L.; Xu, H.; Sun, T.; Wang, Y. A High-efficiency HEVC Entropy Decoding Hardware Architecture. In Proceedings of the 2015 17th International Conference on Advanced Communication Technology (ICACT), Global IT Res Inst (GiRI), PyeonhChang, South Africa, 1–3 July 2015. 783. Ding, D.; Liu, F.; Qi, H.; Yao, Z. An FPGA-friendly CABAC-encoding architecture with dataflow modelling programming. Imaging Sci. J. 2018, 66, 346–354. doi:10.1080/13682199.2018.1477486. 784. Habermann, P.; Chi, C.; Alvarez-Mesa, M.; Juurlink, B. Application-Specific Cache and Prefetching for HEVC CABAC Decoding. IEEE Multimed. 2017, 24, 72–85. doi:10.1109/MMUL.2017.12. 785. Han, Y.; Koh, J.; Kwon, S.; Yoo, S.; Youn, D. Design and implementation of the MPEG-2 multi-channel audio decoder. IEICE Trans. Inf. Syst. 1996, E79D, 759–763. 786. Gao, R.; Xu, D.; Bentley, J. Reconfigurable hardware implementation of an improved parallel architecture for MPEG-4 motion estimation in mobile applications. IEEE Trans. Consum. Electron. 2003, 49, 1383–1390. doi:10.1109/TCE.2003.1261244. 787. Brzuchalski, G. Huffman coding in Advanced Audio Coding standard. In Proceedings of the Conference on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments, Wilga, Poland, 28 May–3 June 2012. doi:10.1117/12.2000138. 788. Brzuchalski, G.; Pastuszak, G. Energy Balance in Advanced Audio Coding Encoder bit-distortion loop algorithm. In Proceedings of the Conference on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments, Poland, 27 May–2 June 2013. doi:10.1117/12.2035278. 789. Ibraheem, M.S.; Hachicha, K.; Romain, O. Fast and Parallel AAC Decoder Architecture for a Digital Radio Mondiale 30 Receiver. IEEE Access 2017, 5, 14638–14646. doi:10.1109/ACCESS.2017.2731902. 790. Suzuki, J.; Ono, S. Entropy CODEC from behavioral description based LSI-CAD for fully programmable image coding system. Des. Autom. Embed. Syst. 1996, 1, 231–255. doi:10.1007/BF00133304. 791. Schumacher, P.; Paluszkiewicz, M.; Ballantyne, R.; Turney, R. An efficient JPEG2000 encoder implemented on a platform FPGA. In Proceedings of the Conference on Applications of Digital Image Processing XXVI, San Diego, CA, USA, 5–8 August 2003. doi:10.1117/12.512542. 792. Schumacher, P. An efficient, optimized JPEG2000 tier-1 coder hardware implementation. In Proceedings of the Conference on Visual Communications and Image Processing 2003, Lugano, Switzerland, 8–11 July 2003. doi:10.1117/12.503084. 793. Fatemi, O.; Asadzadeh, P. Novel efficient architecture for JPEG2000 Entropy coder. In Proceedings of the Visual Communications and Image Processing 2003, Lugano, Switzerland, 8–11 July 2003. doi:10.1117/12.503327. 794. Marcellin, M.W.; Gormish, M.J.; Bilgin, A.; Boliek, M.P. An overview of JPEG-2000. In Proceedings of the DCC 2000. Data Compression Conference, Snowbird, UT, USA, 28–30 March 2000. doi:10.1109/DCC.2000.838192. 795. Liu, K.; Wu, C.K.; Li, Y.S.; Zhuang, H.Y. Bit plane-parallel coder for EBCOT and its VLSI architecture. Jisuanji Xuebao/Chin. J. Comput. 2004, 27, 928–935. 796. Zhu, Y.X.; Zhang, J.; Wang, Y.; Zheng, N.N. Full pass-parallel architecture for EBCOT-Tier1 encoder in JPEG2000. Dianzi Yu Xinxi Xuebao/J. Electron. Inf. Technol. 2006, 28, 2362–2366. 797. Ghodhbani, R.; Saidani, T.; Horrigue, L.; Atri, M. Analysis and Implementation of Parallel Causal Bit Plane Coding In JPEG2000 Standard. In Proceedings of the World Congress on Computer Applications and Information Systems (WCCAIS), Hammamet, Tunisia, 17–19 January 2014. 798. Mert, Y.M.; Yilmaz, O.; Kazak, H.E.; Karakus, K.; Ismailoglu, N.; Oektem, R. Lossy Coding Improvement of EBCOT Design for Onboard JPEG2000 Image Compression. In Proceedings of the 6th International Conference on Recent Advances in Space Technologies (RAST), Istanbul, Turkey, 12–14 June 2013. 799. Sarawadekar, K.; Banerjee, S. A high speed bit plane coder for JPEG 2000 and it’s FPGA implementation. In Proceedings of the 17th European Signal Processing Conference, EUSIPCO 2009, Glasgow, UK, 24–28 August 2009. Computation 2019, xx, 5 68 of 115 800. Guo, J.; Li, Y.S.; Wu, C.K.; Liu, K.; Wang, K.Y. Efficient DWT-EBCOT combined VLSI architecture with low memory for JPEG2000. Dianzi Yu Xinxi Xuebao/J. Electron. Inf. Technol. 2009, 31, 731–735. 801. O’Reilly Media, I. Big Data Now: 2012 Edition; O’Reilly Media: Sebastopol, CA, USA, 2012. 802. Dean, J.; Ghemawat, S. MapReduce: Simplified Data Processing on Large Clusters. Commun. ACM 2008, 51, 107–113. doi:10.1145/1327452.1327492. 803. Shan, Y.; Wang, B.; Yan, J.; Wang, Y.; Xi, N.; Yang, H. FPMR: Map Reduce Framework on FPGA A Case Study of RankBoost Acceleration. In Proceedings of the 18th ACM International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, 21–23 February 2010. 804. Zhang, X.; Wu, Y.; Zhao, C. MrHeter: improving MapReduce performance in heterogeneous environments. Clust. Comput.- J. Netw. Softw. Tools Appl. 2016, 19, 1691–1701. doi:10.1007/s10586-016-0625-2. 805. Wang, Z.; Zhang, S.; He, B.; Zhang, W. Melia: A MapReduce Framework on OpenCL-Based FPGAs. IEEE Trans. Parallel Distrib. Syst. 2016, 27, 3547–3560. doi:10.1109/TPDS.2016.2537805. 806. Diamantopoulos, D.; Kachris, C. High-level Synthesizable Dataflow MapReduce Accelerator for FPGA-coupled Data Centers. In Proceedings of the International Conference on Embedded Computer Systems Architectures Modeling and Simulation, Samos, Greece, 20–23 July 2015. 807. Liang, S.; Yin, S.; Liu, L.; Guo, Y.; Wei, S. A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration. IEEE Comput. Archit. Lett. 2016, 15, 69–72. doi:10.1109/LCA.2015.2458318. 808. Neshatpour, K.; Malik, M.; Sasan, A.; Rafatirad, S.; Mohsenin, T.; Ghasemzadeh, H.; Homayoun, H. Energy-efficient acceleration of MapReduce applications using FPGAs. J. Parallel Distrib. Comput. 2018, 119, 1–17. doi:10.1016/j.jpdc.2018.02.004. 809. Neshatpour, K.; Malik, M.; Ghodrat, M.A.; Sasan, A.; Homayoun, H. Energy-Efficient Acceleration of Big Data Analytics Applications Using FPGAs. In Proceedings of the IEEE International Conference on Big Data, Santa Clara, CA, USA, 29 October–1 November 2015. 810. Kachris, C.; Diamantopoulos, D.; Sirakoulis, G.C.; Soudris, D. An FPGA-based Integrated MapReduce Accelerator Platform. J. Signal Process. Syst. Signal Image Video Technol. 2017, 87, 357–369. doi:10.1007/s11265-016-1108-7. 811. Sharafeddin, M.; Saghir, M.; Akkary, H.; Artail, H.; Hajj, H. On the effectiveness of accelerating MapReduce functions using the Xilinx Vivado HLS tool. Int. J. High Perform. Syst. Archit. 2016, 6, 1–12. doi:10.1504/IJHPSA.2016.076197. 812. Jain, V. Big Data and Hadoop; KHANNA Publishers: Delhi, India, 2017. 813. Alhamali, A.; Salha, N.; Morcel, R.; Ezzeddine, M.; Hamdan, O.; Akkary, H.; Hajj, H. FPGA-Accelerated Hadoop Cluster for Deep Learning Computations. In Proceedings of the IEEE 15th International Conference on Data Mining Workshops (ICDMW), ATlantic city, NJ, USA, 14–17 November 2015. doi:10.1109/ICDMW.2015.148. 814. Kaitoua, A.; Hajj, H.; Saghir, M.A.R.; Artail, H.; Akkary, H.; Awad, M.; Sharafeddine, M.; Mershad, K. Hadoop Extensions for Distributed Computing on Reconfigurable Active SSD Clusters. ACM Trans. Archit. Code Optim. 2014, 11, 191–216. doi:10.1145/2608199. 815. Plugariu, O.; Calin, A.; Petrica, L. Evaluation of a low-power hadoop cluster based on the zynq arm-fpga soc. Univ. Politeh. Buchar. Sci. Bull. Ser. -Electr. Eng. Comput. Sci. 2017, 79, 125–136. 816. Abdul Ghaffar Shoro, T.R.S. Big Data Analysis: Apache Spark Perspective. Glob. J. Comput. Sci. Technol. 2015. 817. Hou, J.; Zhu, Y.; Kong, L.; Wang, Z.; Du, S.; Song, S.; Huang, T. A Case Study of Accelerating Apache Spark with FPGA. In Proceedings of the 17th IEEE International Conference on Trust, Security and Privacy in Computing and Communications and 12th IEEE International Conference on Big Data Science and Engineering, Trustcom/BigDataSE 2018, New York, NY, USA, 1–3 August 2018. doi:10.1109/TrustCom/BigDataSE.2018.00123. 818. Morcel, R.; Ezzeddine, M.; Akkary, H. FPGA-based Accelerator for Deep Convolutional Neural Netw. for the SPARK Environment. In Proceedings of the IEEE International Conference on Smart Cloud (IEEE SmartCloud), New York City, NY, USA, 18–20 November 2016. doi:10.1109/SmartCloud.2016.31. 819. Xekalaki, M.; Fumero, J.; Kotselidis, C. Challenges and proposals for enabling dynamic heterogeneous execution of Big Data frameworks. In Proceedings of the 10th IEEE International Conference on Computation 2019, xx, 5 69 of 115 Cloud Computing Technology and Science (IEEE CloudCom), Nicosia, Cyprus, 10–13 December 2018. doi:10.1109/CloudCom2018.2018.00070. 820. Hidri, K.; Bilas, A.; Kozanitis, C. HetSpark: A Framework that Provides Heterogeneous Executors to Apache Spark. In Proceedings of the 7th International Young Scientists Conference on Computational Science, YSC 2018, Heraklion, Greece, 2–6 July 2018. doi:10.1016/j.procs.2018.08.244. 821. Kachris, C.; Sirakoulis, G.C.; Soudris, D. A MapReduce scratchpad memory for multi-core cloud computing applications. Microprocess. Microsyst. 2015, 39, 599–608. doi:10.1016/j.micpro.2015.08.007. 822. Muller, J. Elementary Functions: Algorithms and Implementation; Computer Science, Birkhäuser Basel: Basel, Switzerland, 2006. 823. Tang, A.; Yu, L.; Han, F.; Zhang, Z. CORDIC-based FFT Real-time Processing Design and FPGA Implementation. In Proceedings of the 12th IEEE International Colloquium on Signal Processing & its Applications (CSPA), Melaka, Malaysia, 4–6 March 2016. 824. Angarita, F.; Canet, M.J.; Sansaloni, T.; Perez-Pascual, A.; Valls, J. Efficient mapping of CORDIC algorithm for OFDM-based WLAN. J. Signal Process. Syst. Signal Image Video Technol. 2008, 52, 181–191. doi:10.1007/s11265-007-0146-6. 825. Lee, K.; Kim, J.; Lee, J.; Cho, Y. A compact CORDIC algorithm for synchronization of carrier frequency offset in OFDM modems. IEICE Trans. Commun. 2006, E89B, 952–954. doi:10.1093/ietcom/e89-b.3.952. 826. Jain, N.; Mishra, B. DCT and CORDIC on a Novel Configurable Hardware; IEEE: 6, 2015; pp. 51–56. In Proceedings of the IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Vasavi Coll Engn, Hyderabad, India, 27–29 November 2015. 827. Mane, M.; Patil, D.; Sutaone, M.S.; Sadalage, A. Implementation of DCT using variable iterations CORDIC algorithm on FPGA. In Proceedings of the First International Conference on Computational Systems and Communications (ICCSC), Trivandrum, India, 17–18 December 2014. 828. Pereira, K.; Athanas, P.; Lin, H.; Feng, W. Spectral method characterization on FPGA and GPU accelerators. In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, 30 November–2 December 2011. doi:10.1109/ReConFig.2011.83. 829. Palsodkar, P.; Gurjar, A. Improved Fused Floating Point Add-Subtract and Multiply-Add Unit for FFT Implementation. In Proceedings of the 2nd International Conference on Devices, Circuits and Systems (ICDCS), Combiatore, India, 6–8 March 2014. 830. Palsodkar, P.; Gurjar, A. Improved Fused Floating Point Add-Subtract Unit for FFT Implementation. In Proceedings of the International Conference on Electronics and Communication Systems (ICECS), Coimbatore, India, 13–14 February 2014. 831. Canto-Navarro, E.; Lopez-Garcia, M.; Ramos-Lara, R. Floating-point accelerator for biometric recognition on FPGA embedded systems. J. Parallel Distrib. Comput. 2018, 112, 20–34. doi:10.1016/j.jpdc.2017.09.010. 832. Kim, J.S.; Jung, S. Implementation of neural network hardware based on a floating point operation in an FPGA - art. no. 679451. In Proceedings of the 4th International Conference on Metronics and Information Technology (ICMIT 2007), Gifu, Japan, 5–6 December 2007. 833. Renteria-Cedano, J.A.; Aguilar-Lobo, L.M.; Ortega-Cisneros, S.; Loo-Yau, J.R.; Raygoza-Panduro, J.J. FPGA Implementation of a NARX Network for Modeling Nonlinear Systems. In Proceedings of the 19th Iberoamerican Congress on Pattern Recognition (CIARP), Puerto Vallarta, Mexico, 1–5 November 2014. 834. Rane, S.M.; Wagh, T.; Malathi, P. FPGA Implementation of Addition/Subtraction Module for Double Precision Floating Point Numbers Using Verilog; IEEE: 4, 2014. In Proceedings of the International Conference on Advances in Engineering and Technology Research (ICAETR), Unnao, India, 1–2 August 2014. 835. Ramesh, A.P.; Tilak, A.V.N.; Prasad, A.M. An FPGA Based High Speed IEEE-754 Double Precision Floating Point Multiplier U sing Verilog. In Proceedings of the International Conference on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), Tiruvannamalai, India, 7–9 January 2013. 836. Zhou, J.; Dou, Y.; Lei, Y.; Xu, J.; Dong, Y. Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. In Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications, Dalian Univ Technol, Dalian, China, 25–27 September 2008. Computation 2019, xx, 5 70 of 115 837. Duarte, R.; Neto, H.; Vestias, M. Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. In Proceedings of the 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, Patras, Greece, 27–29 August 2009. doi:10.1109/DSD.2009.199. 838. Amirtharajah, R. Chapter 24 - Distributed Arithmetic. In Reconfigurable Computing; Hauck, S.; Dehon, A., Eds.; Systems on Silicon, Morgan Kaufmann: Burlington, NJ, USA, 2008; pp. 503–512. doi:https://doi.org/10.1016/B978-012370522-8.50032-7. 839. Wang, W.; Swamy, M.; Ahmad, M. Novel design and FPGA implementation of DA-RNS FIR filters. J. Circuits Syst. Comput. 2004, 13, 1233–1249. doi:10.1142/S0218126604001970. 840. Krishnaveni, K.; Ranjith, C.; Rani, S.P.J.V. Evolvable Hardware Architecture Using Genetic Algorithm for Distributed Arithmetic FIR Filter. In Proceedings of the International Conference on Artificial Intelligence and Evolutionary Computations in Engineering Systems (ICAIECES), SRM Univ, Chennai, India, 19–21 May 2016. doi:10.1007/978-981-10-3174-8_26. 841. Das, G.; Maity, K.; Sau, S. Hardware Implementation of Parallel FIR Filter Using Modified Distributed Arithmetic. In Proceedings of the 2nd Annual International Conference on Data Science and Business Analytics, ICDSBA 2018, ChangSha, China, 21–23 September 2018. doi:10.1109/ICDSBA.2018.00015. 842. Pai, A.; Benkrid, K.; Crookes, D. Embedded reconfigurable DCT architectures using adder-based distributed arithmetic. In Proceedings of the 7th International Workshop on Computer Architecture for Machine Perception, Palermo, Italy, 4–6 July 2005. 843. Elias, T.S.; Dhanusha, P.B. Area Efficient Fully Parallel Distributed Arithmetic Architecture for One-Dimensional Discrete Cosine Transform. In Proceedings of the International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), Kanyakumari, India, 10–11 July 2014. 844. Senapati, R.; Prasad, P.; Shabnam, S.; Jagadeesh, C.; Srinath, K. An optimised distributed arithmetic architecture for 8x8 DTT. Int. J. Eng. Technol. 2015, 7, 1278–1290. 845. Nair, M.; Mamatha, I.; Tripathi, S. Distributed arithmetic based hybrid architecture for multiple transforms. In Proceedings of the International Conference on Signal Processing and Communication, ICSC 2018, Uttar Pradesh, India, 21–23 March 2018. doi:10.1007/978-981-13-2553-3_22. 846. Jing, C.; Bin, H.Y. Efficient wavelet transform on FPGA using advanced distributed arithmetic. In Proceedings of the 8th International Conference on Electronic Measurement and Instruments, Xi’an, China, 16–18 August 2007. 847. Papadhopulli, I.; Cico, B. Implementation in FPGA of 3D discrete wavelet transform for imaging noise removal. In Proceedings of the 4th ICT Innovations Conference on Secure and Intelligent Systems, Ohrid, North Macedonia, 12–15 September 2012. doi:10.1007/978-3-642-37169-1_36. 848. Shah, D.; Vithlani, C. FPGA realization of DA-based 2D-discrete wavelet transform for the proposed image compression approach. In Proceedings of the 2011 Nirma University International Conference on Engineering: Current Trends in Technology, NUiCONE 2011, Gujarat, India, 8–10 December 2011. doi:10.1109/NUiConE.2011.6153233. 849. Liao, H.; Yin, M.; Cheng, Y. A parallel implementation of the Smith-Waterman algorithm for massive sequences searching. In Proceedings of the 26th Annual International Conference of the IEEE-Engineering-in-Medicine-and-Biology-Society, San Francisco, CA, USA, 1-5 September 2004. 850. Hasan, L.; Al-Ars, Z.; Nawaz, Z.; Bertels, K. Hardware implementation of the smith-waterman algorithm using recursive variable expansion. In Proceedings of the 2008 3rd International Design and Test Workshop, IDT 2008, Monastir, Tunisia, 20–22 December 2008. doi:10.1109/IDT.2008.4802483. 851. Marmolejo-Tejada, J.M.; Trujillo-Olaya, V.; Renteria-Mejia, C.P.; Velasco-Medina, J. Hardware Implementation of the Smith-Waterman Algorithm using a Systolic Architecture. In Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems (LASCAS), Santiago, Chile, 25–28 February 2014. 852. Zou, D.; Dou, Y.; Xia, F.; Ni, S.C. FPGA-based smith-waterman algorithm accelerator with backtracking. Guofang Keji Daxue Xuebao/J. Natl. Univ. Def. Technol. 2009, 31, 29–32. 853. Meng, X.; Chaudhary, V. A High-Performance Heterogeneous Computing Platform for Biological Sequence Analysis. IEEE Trans. Parallel Distrib. Syst. 2010, 21, 1267–1280. doi:10.1109/TPDS.2009.165. 854. Al Junid, S.A.M.; Haron, M.A.; Abd Majid, Z.; Halim, A.K.; Osman, F.N.; Hashim, H. Development of Novel Data Compression Technique for Accelerate DNA Sequence Alignment Based on Smith-Waterman Computation 2019, xx, 5 71 of 115 Algorithm. In Proceedings of the 3rd UKSim European Symposium on Computer Modeling and Simulation, Athens, Greece, 25–27 November 2009. 855. Hasib, S.; Motwani, M.; Saxena, A. Importance of aho-corasick string matching algorithm in real world applications. Int. J. Comput. Sci. Inf. Technol. 2013, 4, 467–469. 856. Baker, Z.; Prasanna, V. High-throughput linked-pattern matching for intrusion detection systems. In Proceedings of the 2005 Symposium on Architectures for Networking and Communications Systems, ANCS 2005, Princeton, NJ, USA, 26–28 October 2006. doi:10.1109/ANCS.2005.4675279. 857. Pandey, A.; Khare, N. String matching technique based on hardware: A comparative analysis. In Proceedings of the 2nd International Conference on Advances in Computing and Information Technology, ACITY-2012, Chennai, India, 13–15 July 2012. doi:10.1007/978-3-642-31513-8_35. 858. Pontarelli, S.; Bianchi, G.; Teofili, S. Traffic-Aware Design of a High-Speed FPGA Network Intrusion Detection System. IEEE Trans. Comput. 2013, 62, 2322–2334. doi:10.1109/TC.2012.105. 859. Dominguez, A.; Carballo, P.P.; Nunez, A. Programmable SoC platform for Deep Packet Inspection using enhanced Boyer-Moore algorithm. In Proceedings of the 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), Madrid, Spain, 12–14 July 2017. 860. Zengin, S.; Schmidt, E.G. A Fast and Accurate Hardware String Matching Module with Bloom Filters. IEEE Trans. Parallel Distrib. Syst. 2017, 28, 305–317. doi:10.1109/TPDS.2016.2577033. 861. Meghana, V.; Suresh, M.; Sandhya, S.; Aparna, R.; Gururaj, C. SoC Implementation of Network Intrusion Detection Using Counting Bloom Filter. In Proceedings of the IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology (RTEICT), Sri Venkateshwara Coll Engn, Dept Elect & Commun Engn, Bengaluru, India, 20–21 May 2016. 862. Lee, D.U.; Gaffar, A.A.; Cheung, R.C.C.; Mencer, O.; Luk, W.; Constantinides, G.A. Accuracy-guaranteed bit-width optimization. IEEE Trans.-Comput.-Aided Des. Integr. Circuits Syst. 2006, 25, 1990–2000. doi:10.1109/TCAD.2006.873887. 863. Jin, R.; Jiang, J.; Dou, Y. Accuracy Evaluation of Long Short Term Memory Network Based Language Model with Fixed-Point Arithmetic. In Proceedings of the 13th International Symposium on Applied Reconfigurable Computing (ARC), Delft, The Netherlands, 3–7 April 2017. doi:10.1007/978-3-319-56258-2_24. 864. Mohanty, R.; Anirudh, G.; Pradhan, T.; Kabi, B.; Routray, A. Design and Performance Analysis of Fixed-Point Jacobi SVD Algorithm on Reconfigurable System. IERI Procedia, 2014, 7, 21–27. 865. Jerez, J.L.; Constantinides, G.A.; Kerrigan, E.C. Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing. In Proceedings of the 20th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Toronto, ON, Canada, 29 April–1 May 2012. doi:10.1109/FCCM.2012.19. 866. Pradhan, T.; Kabi, B.; Mohanty, R.; Routray, A. Development of numerical linear algebra algorithms in dynamic fixed-point format: a case study of Lanczos tridiagonalization. Int. J. Circuit Theory Appl. 2016, 44, 1222–1262. doi:10.1002/cta.2159. 867. Jiang, J.; Hu, R.; Lujan, M.; Dou, Y. Empirical Evaluation of Fixed-Point Arithmetic for Deep Belief Networks. In Proceedings of the 9th International Applied Reconfigurable Computing Symposium (ARC), Los Angeles, CA, USA, 25–27 March 2013. 868. Jiang, J.; Hu, R.; Lujan, M. A flexible memory controller supporting deep belief networks with fixed-point arithmetic. In Proceedings of the 2013 IEEE 37th Annual Computer Software and Applications Conference, COMPSAC 2013, Boston, MA, USA, 22–26 July 2013. doi:10.1109/IPDPSW.2013.98. 869. Gupta, A. The Power of Vedic Maths; Jaico Publishing House, 2004. 870. Tiwari, H.D.; Gankhuyag, G.; Kim, C.M.; Cho, Y.B. Multiplier design based on ancient Indian Vedic Mathematics. In Proceedings of the International SoC Design Conference 2008, Busan, Korea, 24–25 November 2008. 871. Mehta, P.; Gawali, D. Conventional versus Vedic mathematical method for hardware implementation of a multiplier. In Proceedings of the International Conference on Advances in Computing, Control and Telecommunication Technologies, ACT 2009, Trivandrum, Kerala, India, 28–29 December 2009. doi:10.1109/ACT.2009.162. 872. Kunchigi, V.; Kulkarni, L.; Kulkarni, S. High speed and area efficient vedic multiplier. In Proceedings of the 2012 International Conference on Devices, Circuits and Systems, ICDCS 2012, Coimbatore, India, 15–16 March 2012. doi:10.1109/ICDCSyst.2012.6188747. Computation 2019, xx, 5 72 of 115 873. Huddar, S.R.; Rao, S.; Kalpana, M.; Mohan, S. Novel High Speed Vedic Mathematics Multiplier using Compressors. In Proceedings of the IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing (iMac4s), Kottayam, India, 22–23 February 2013. 874. Verma, G.; Maheshwari, S.; Sukhbani, K.V.; Baishander, N.; Singhland, I.; Pandey, B. Low power squarer design using Ekadhikena Purvena on 28nm FPGA. Int. J. Control Autom. 2016, 9, 281–288. doi:10.14257/ijca.2016.9.5.27. 875. Madhok, S.; Pandey, B.; Kaur, A.; Minver, M.; Akbar, H.D. HSTL IO standard based energy efficient multiplier design using Nikhilam navatashcaramam dashatah on 28nm FPGA. Int. J. Control Autom. 2015, 8, 35–44. doi:10.14257/ijca.2015.8.8.05. 876. Thapliyal, H.; Arabnia, H. A time-area-power efficient multiplier and square architecture based on ancient Indian Vedic Mathematics. In Proceedings of the Internation Conference on Embedded Systems and Applications/International Conference on VLSI, Las Vegas, NV, USA, 21–24 June 2004. 877. Ammendola, R.; Biagioni, A.; Frezza, O.; Lamanna, G.; Lonardo, A.; Lo Cicero, F.; Paolucci, P.S.; Pantaleo, F.; Rossetti, D.; Simula, F.; Sozzi, M.; Tosoratto, L.; Vicini, P. NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs. J. Instrum. 2014, 9. doi:10.1088/1748-0221/9/02/C02023. 878. Galli, L.; Baldini, A.; Cattaneo, P.W.; Cei, F.; De Gerone, M.; Dussoni, S.; Gatti, F.; Grassi, M.; Morsani, F.; Nicolo, D.; Papa, A.; Ritt, S.; Signorelli, G. Operation and performance of the trigger system of the MEG experiment. J. Instrum. 2014, 9. doi:10.1088/1748-0221/9/04/P04022. 879. Clemencio, F.; Blanco, A.; Carolino, N.; Loureiro, C. The trigger system of a large area RPC TOF-tracker muon telescope. J. Instrum. 2018, 13. doi:10.1088/1748-0221/13/08/T08001. 880. Duarte, J.; Han, S.; Harris, P.; Jindariani, S.; Kreinar, E.; Kreis, B.; Ngadiuba, J.; Pierini, M.; Rivera, R.; Tran, N.; Wu, Z. Fast inference of deep Neural Netw. in FPGAs for particle physics. J. Instrum. 2018, 13. doi:10.1088/1748-0221/13/07/P07027. 881. Andrei, V.; Hanke, P.; Jongmanns, J.; Khomich, A.; Meier, K.; Schmitt, K.; Schultz-Coulon, H.C.; Stamen, R.; Stock, P.; Wessels, M. The upgrade of the PreProcessor system of the ATLAS level-1 calorimeter trigger. J. Instrum. 2012, 7. doi:10.1088/1748-0221/7/12/C12026. 882. Anderson, J.; Andreani, A.; Andreazza, A.; Annovi, A.; Atkinson, M.; Auerbach, B.; Beretta, M.; Bevacqua, V.; Blair, R.; Blazey, G.; et al. FTK: a Fast Track Trigger for ATLAS. J. Instrum. 2012, 7. doi:10.1088/1748-0221/7/10/C10002. 883. Bauss, B.; Buescher, V.; Degele, R.; Ji, W.; Moritz, S.; Reiss, A.; Schaefer, U.; Simioni, E.; Tapprogge, S.; Wenzel, V. An FPGA based Topological Processor prototype for the ATLAS Level-1 Trigger upgrade. J. Instrum. 2012, 7. doi:10.1088/1748-0221/7/12/C12007. 884. Annovi, A.; Beretta, M.; Bogdan, M.; Cipriani, R.; Citraro, S.; Faulkner, G.; Gatta, M.; Giannetti, P.; Lanza, A.; Luciano, P.; et al. Design of a hardware track finder (Fast TracKer) for the ATLAS trigger. J. Instrum. 2014, 9. doi:10.1088/1748-0221/9/01/C01045. 885. Zhang, Y.Y.; Li, Z.; Yang, L.; Zhang, S.W. An efficient CSA architecture for montgomery modular multiplication. Microprocess. Microsyst. 2007, 31, 456–459. doi:10.1016/j.micpro.2006.12.003. 886. Alkar, A.; Sonmez, R. A hardware version of the RSA using the Montgomery’s algorithm with systolic arrays. Integr. Vlsi J. 2004, 38, 299–307. doi:10.1016/j.vlsi.2004.07.018. 887. Lee, J.W.; Chung, S.C.; Chang, H.C.; Lee, C.Y. An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor. In Proceedings of the 14th International Workshop on Cryptographic Hardware and Embedded Systems (CHES), Katholieke Univ, Leuven, Belgium, 9–12 September 2012. 888. Wang, W.; Huang, X. A Novel Fast Modular Multiplier Architecture for 8,192-bit RSA Cryposystem. In Proceedings of the IEEE Conference on High Performance Extreme Computing (HPEC), Waltham, MA, USA, 10–12 September 2013. 889. Peddapelli, S. Pulse Width Modulation: Analysis and Performance in Multilevel Inverters; De Gruyter, 2016. 890. Mekhilef, S.; Rahim, N. Xilinx FPGA based three-phase PWM inverter and its application for utility connected PV system. In Proceedings of the 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering, Beijing, China, 28–31 October 2002. 891. Ohshima, M.; Masada, E. Novel three-phase current-regulated digital PWM and its behavioral analysis. Electr. Eng. Jpn. 2005, 150, 62–77. doi:10.1002/eej.10330. Computation 2019, xx, 5 73 of 115 892. Mekhilef, S.; Rahim, N. Generation of three-phase PWM inverter using xilinx FPGA and its application for utility connected PV system. Int. J. Eng. Trans. B Appl. 2004, 17, 271–276. 893. Sontakke, J.A.; Choudhary, G. Design of Digital Controller Using Pole Placement Technique for Single Phase PWM Inverter and Its Implementation on FPGA. In Proceedings of the International Conference on Nascent Technologies in Engineering (ICNTE), Vashi, India, 27–28 January 2017. 894. Xiaoming, Z.; Feng, S.; Yunping, C. A repetitive learning boost converter control of neutral line active power filter based on FPGA and DSP. In Proceedings of the 8th International Power Engineering Conference, IPEC 2007, Singapore, Singapore, 3–6 December 2007. 895. Batarseh, M.G.; Shoubaki, E.; Batarseh, I. A Dynamic, Linearly-Shifted, Fixed-Slope Digital-Ramp Control Technique for Improved Transient Response in DC - DC Converters. In Proceedings of the 4th International Conference on Electric Power and Energy Conversion Systems (EPECS), Sharjah, United Arab Emirates, 24–26 November 2015. 896. Channappanavar, R.; Mishra, S.; Singh, R. An Inductor Current Estimator for Digitally Controlled Synchronous Buck Converter. IEEE Trans. Power Electron. 2018. doi:10.1109/TPEL.2018.2863958. 897. Lahari, M.; Vedula, S.; Rao, V. Real time models for FPGA based control of power electronic converters: A graphical programming approach. In Proceedings of the 2015 IEEE IAS Joint Industrial and Commercial Power Systems / Petroleum and Chemical Industry Conference, ICPSPCIC 2015, Hyderabad, India, 19–21 November 2015. doi:10.1109/CICPS.2015.7974054. 898. Bharatiraja, C.; Reddy, H.; Sri, R.N.; Saisuma, S. FPGA based design and validation of asymmetrical reduced switch multilevel inverter. Int. J. Power Electron. Drive Syst.. 2016, 7, 340–348. doi:10.11591/ijpeds.v7.i2.pp340-348. 899. Bin, I.B.; Arshad, M.; Thangaprakash, S. FPGA based implementation of selective harmonic elimination PWM for cascaded multilevel inverter. Int. Rev. Model. Simul. 2012, 5, 1919–1926. 900. Anjali, K.R.; Padmasuresh, L.; Muthukumar, P. Genetic algorithm based 15 level multilevel inverter with SHE PWM. Int. J. Eng. Technol. 2018, 7, 893–897. 901. Mohan, V.; Stalin, N.; Jeevananthan, S. A tactical chaos based PWM technique for distortion restraint and power spectrum shaping in induction motor drives. Int. J. Power Electron. Drive Syst. 2015, 5, 383–392. 902. Wagner, F.; Schmuki, R.; Wagner, T.; Wolstenholme, P. Modeling Software with Finite State Machines: A Practical Approach; CRC Press: Boca Raton, FL, USA, 2006. 903. Li, L.W.; Gui, W.H.; Hu, X.L. A FPGA-based design method of low power fault-tolerance finite state machine. Hunan Daxue Xuebao/J. Hunan Univ. Nat. Sci. 2010, 37, 77–82. 904. Saleem, A.; Khan, S. Low power state machine design on FPGAs. In Proceedings of the 2010 3rd International Conference on Advanced Computer Theory and Engineering, ICACTE 2010, Chengdu, China, 20–22 August 2010. doi:10.1109/ICACTE.2010.5579416. 905. Donzellini, G.; Ponta, D. Digital design laboratory. In Proceedings of the 15th Biennial Baltic Electronics Conference, BEC 2016, Tallinn, Estonnia, 3–5 October 2016. doi:10.1109/BEC.2016.7743730. 906. Donzellini, G.; Ponta, D. Introducing Field Programmable Gate Arrays with Deeds Projects. In Proceedings of the 4th Interdisciplinary Engineering Design Education Conference (IEDEC), Santa Clara, CA, USA, 3 March 2014. 907. Brucker, P. Scheduling Algorithms; Springer: Berlin/Heidelberg, Germany, 2013. 908. Cardoso, J. On combining temporal partitioning and sharing of functional units in compilation for reconfigurable architectures. IEEE Trans. Comput. 2003, 52, 1362–1375. doi:10.1109/TC.2003.1234532. 909. Ahmadinia, A.; Bobda, C.; Koch, D.; Majer, M.; Teich, J. Task scheduling for heterogeneous reconfigurable computers. In Proceedings of the 17th Symposium on Integrated Circuits and Systems Design (SBCCI 2004), Porto De Galinhas, Brazil, 7–11 September 2004. doi:10.1145/1016568.1016582. 910. Gohringer, D.; Hubner, M.; Zeutebouo, E.; Becker, J. CAP-OS: Operating system for runtime scheduling, task mapping and resource management on reconfigurable multiprocessor architectures. In Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010, Atlanta, GA, USA, 19–23 April 2010. doi:10.1109/IPDPSW.2010.5470732. 911. Kohutka, L.; Stopjakova, V. Task Scheduler for Dual-Core Real-Time Systems. In Proceedings of the 23rd International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES), Lodz, Poland, 23–25 June 2016. Computation 2019, xx, 5 74 of 115 912. Kohutka, L.; Stopjakova, V. Reliable real-time task scheduler based on Rocket Queue architecture. Microelectron. Reliab. 2018, 84, 7–19. doi:10.1016/j.microrel.2017.12.007. 913. Cayssials, R.; Duval, M.; Ferro, E.; Alimenti, O. uRT51: An embedded real-time processor implemented on FPGA devices. Lat. Am. Appl. Res. 2007, 37, 35–40. 914. Ferrandi, F.; Lanzi, P.L.; Pilato, C.; Sciuto, D.; Tumeo, A. Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2010, 29, 911–924. doi:10.1109/TCAD.2010.2048354. 915. Luo, J.; Jha, N.K. Power-efficient scheduling for heterogeneous distributed real-time embedded systems. IEEE Trans.-Comput.-Aided Des. Integr. Circuits Syst. 2007, 26, 1161–1170. doi:10.1109/TCAD.2006.885736. 916. Wolfram, S. Cellular automata as models of complexity. Nature 1984, 311, 419. 917. Anghelescu, P.; Sofron, E.; Rincu, C.I.; Iana, V.G. Programmable cellular automata based encryption algorithm. In Proceedings of the 31st International Semiconductor Conference, Sinaia, Romania, 13–15 October 2008. doi:10.1109/SMICND.2008.4703423. 918. Anghelescu, P.; Ionita, S.; Sofron, E. Encryption Technique with Programmable Cellular Automata (ETPCA). J. Cell. Autom. 2010, 5, 79–105. 919. Fuster-Sabater, A.; Eugenia Pazo-Robles, M.; Caballero-Gil, P. A simple linearization of the self-shrinking generator by means of cellular automata. Neural Netw. 2010, 23, 461–464. doi:10.1016/j.neunet.2009.12.008. 920. Slav, C.; Balan, T.; Franti, E.; Dascalu, M. Exploring the cellular automata phenomenology for cryptographic applications. WSEAS Trans. Commun. 2005, 4, 186–191. 921. Anghelescu, P. FPGA Implementation of Programmable Cellular Automata Encryption Algorithm for Network Communications. Comput. Syst. Sci. Eng. 2016, 31, 361–370. 922. Ioana, D.; Radu, D. FPGA Implementation and Evaluation of two Cryptographically Secure Hybrid Cellular Automata. In Proceedings of the 10th International Conference on Communications (COMM), Bucharest, Romania, 29–31 May 2014. 923. Anghelescu, P.; Ionita, S.; Iana, V.G. FPGA implementation of cellular automata based encryption algorithm for internet communications. In Proceedings of the 2011 International Conference for Internet Technology and Secured Transactions, ICITST 2011, Abu Dhabi, United Arab Emirates, 11–14 December 2011. 924. Shackleford, B.; Tanaka, M.; Carter, R.; Snider, G. FPGA implementation of neighborhood-of-four cellular automata random number generators. In Proceedings of the FPGA 2002: Tenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, 24–26 February 2002. 925. Petrica, L. FPGA optimized cellular automaton random number generator. J. Parallel Distrib. Comput. 2018, 111, 251–259. doi:10.1016/j.jpdc.2017.05.022. 926. Mocanu, D.; Gheolbanoiu, A.; Hobincu, R.; Petrica, L. Global feedback self-programmable cellular automaton random number generator. Rev. Tec. De La Fac. De Ing. Univ. Del Zulia 2016, 39, 1–9. 927. Shackleford, B.; Tanaka, M.; Carter, R.; Snider, G. Random number generators implemented with neighborhood-of-four, non-locally connected cellular automata. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 2002, E85A, 2612–2623. 928. Saravakos, P.; Sirakoulis, G.C. Modeling employees behavior in workplace dynamics. J. Comput. Sci. 2014, 5, 821–833. doi:10.1016/j.jocs.2014.05.001. 929. Vourkas, I.; Sirakoulis, G.C. FPGA based Cellular Automata for Environmental Modeling. In Proceedings of the 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), Seville, Spain, 9–12 December 2012. 930. Radulescu, V. A synchronization model for automata arrays; , 2008. In Proceedings of the 27th IASTED International Conference on Modelling, Identification, and Control, Innsbruck, Austria, 11–13 February 2008. 931. Kalogeropoulos, G.; Sirakoulis, G.C.; Karafyllidis, I. Cellular automata on FPGA for real-time urban traffic signals control. J. Supercomput. 2013, 65, 664–681. doi:10.1007/s11227-013-0952-5. 932. Georgoudas, I.G.; Kyriakos, P.; Sirakoulis, G.C.; Andreadis, I.T. An FPGA implemented cellular automaton crowd evacuation model inspired by the electrostatic-induced potential fields. Microprocess. Microsyst. 2010, 34, 285–300. doi:10.1016/j.micpro.2010.06.001. 933. Progias, P.; Sirakoulis, G.C. An FPGA processor for modelling wildfire spreading. Math. Comput. Model. 2013, 57, 1436–1452. doi:10.1016/j.mcm.2012.12.005. Computation 2019, xx, 5 75 of 115 934. Tsompanas, M.A.; Sirakoulis, G.; Karafyllidis, I. Modeling memory resources distribution on multicore processors using games on cellular automata lattices. In Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW 2010, Atlanta, GA, USA, 19–23 April 2010. doi:10.1109/IPDPSW.2010.5470700. 935. Georgoudas, I.G.; Sirakoulis, G.C.; Scordilis, E.M.; Andreadis, I.T. On-chip earthquake simulation model using potentials. Nat. Hazards 2009, 50, 519–537. doi:10.1007/s11069-008-9255-1. 936. Tsiftsis, A.; Sirakoulis, G.C.; Lygouras, J. FPGA Design of a Cellular Automaton Model for Railway Traffic Flow with GPS Module. In Proceedings of the 9th International Conference on Cellular Automata for Research and Industry, Univ Camerino, Ascoli Piceno, Italy, 21–24 September 2010. 937. Hansson, A.; Mortveit, H.; Tripp, J.; Gokhale, M. Urban traffic simulation modeling for reconfigurable hardware. In Proceedings of the 3rd Industrial Simulation Conference 2005, Fraunhofer-IPK, Berlin, Germany, 9–11 June 2005. 938. Ntinas, V.G.; Moutafis, B.E.; Trunfio, G.A.; Sirakoulis, G.C. Parallel fuzzy cellular automata for data-driven simulation of wildfire spreading. J. Comput. Sci. 2017, 21, 469–485. doi:10.1016/j.jocs.2016.08.003. 939. Giitsidis, T.; Sirakoulis, G.C. Simulation of aircraft disembarking and emergency evacuation. In Proceedings of the 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), Turin, Italy, 12–14 February 2014. doi:10.1109/PDP.2014.96. 940. Chatziagorakis, P.; Sirakoulis, G.C. Cellular automata simulation of saltwater intrusion in coastal aquifer. Int. J. Parallel Emergent Distrib. Syst. 2016, 31, 517–528. doi:10.1080/17445760.2015.1077523. 941. Encinas, J. Phase Locked Loops; Microwave and RF Techniques and Applications; Springer: New York, NY, USA, 2012. 942. Machida, H.; Kobayashi, F. PLL/PID motor control system by using time-domain operation of PWM signal. In Proceedings of the Annual Conference on the Society-of-Instrument-and-Control-Engineers, Kagawa Univ, Takamatsu, Japan, 17–20 September 2007. 943. MacHida, H.; Inoue, T.; Kobayashi, F. Highly precise rotational speed control by a hybrid of PLL and repetitive control. IEEJ Trans. Electron. Inf. Syst. 2012, 132, 738–743. doi:10.1541/ieejeiss.132.738. 944. MacHida, H.; Kambara, M.; Tanaka, K.; Kobayashi, F. A motor speed servo system based on the dual loop PLL. IEEJ Trans. Electron. Inf. Syst. 2011, 131, 337–342. doi:10.1541/ieejeiss.131.337. 945. Linn, Y. A self-normalizing symbol synchronization lock detector for QPSK and BPSK. IEEE Trans. Wirel. Commun. 2006, 5, 347–353. doi:10.1109/TWC.2006.02014. 946. Linn, Y. Robust M-PSK Phase Detectors for Carrier Synchronization PLLs in Coherent Receivers: Theory and Simulations. IEEE Trans. Commun. 2009, 57, 1794–1805. doi:10.1109/TCOMM.2009.06.070342. 947. Shamla, B.; Devi, G.K.G. Design and Implementation of Costas loop for BPSK Demodulator. In Proceedings of the Annual IEEE India Conference (INDICON), Kochi, India, 7–9 December 2012. 948. Helal, B.M.; Hsu, C.M.; Johnson, K.; Perrott, M.H. A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop. IEEE J.-Solid-State Circuits 2009, 44, 1391–1400. doi:10.1109/JSSC.2009.2015816. 949. Sunter, S.; Roy, A. Noise-insensitive digital BIST for any PLL or DLL. J. Electron.-Test.-Theory Appl. 2008, 24, 461–472. doi:10.1007/s10836-007-5061-z. 950. Aloisio, A.; Giordano, R.; Izzo, V. Phase Noise Issues With FPGA-Embedded DLLs and PLLs in HEP Applications. IEEE Trans. Nucl. Sci. 2011, 58, 1664–1671. doi:10.1109/TNS.2011.2143727. 951. Egan, T.; Mourad, S. Characterization and verification of phase-locked loops. In Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference (IMTC/2001), Budapest, Hungary, 21–23 May 2001. 952. Aloisio, A.; Giordano, R.; Izzo, V. Jitter issues in clock conditioning with FPGAs. In Proceedings of the 2010 17th IEEE-NPSS Real Time Conference, RT10, Lisbon, Portugal, 24–28 May 2010. doi:10.1109/RTC.2010.5750386. 953. Mandal, M.; Sarkar, B.C. Ring oscillators: Characteristics and applications. Indian J. Pure Appl. Phys. 2010, 48, 136–145. 954. Merli, D.; Schuster, D.; Stumpf, F.; Sigl, G. Semi-invasive EM attack on FPGA RO PUFs and countermeasures. In Proceedings of the 6th Workshop on Embedded Systems Security, WESS’11, Taipei, Taiwan, 9–14 October 2011. doi:10.1145/2072274.2072276. Computation 2019, xx, 5 76 of 115 955. Stanciu, A.; Cirstea, M.N.; Moldoveanu, F.D. Analysis and Evaluation of PUF-Based SoC Designs for Security Applications. IEEE Trans. Ind. Electron. 2016, 63, 5699–5708. doi:10.1109/TIE.2016.2570720. 956. Du, C.; Bai, G. A Novel Relative Frequency Based Ring Oscillator Physical Unclonable Function. In Proceedings of the IEEE 17th International Conference on Computational Science and Engineering (CSE), Chengdu, China, 19–21 December 2014. doi:10.1109/CSE.2014.129. 957. Zhang, J.; Tan, X.; Zhang, Y.; Wang, W.; Qin, Z. Frequency Offset-Based Ring Oscillator Physical Unclonable Function. IEEE Trans.-Multi-Scale Comput. Syst. 2018, 4, 711–721. doi:10.1109/TMSCS.2018.2877737. 958. Junnarkar, S.S.; O’Connor, P.; Fontaine, R. FPGA based self calibrating 40 picosecond resolution, wide range Time to Digital Converter. In Proceedings of the IEEE Nuclear Science Symposium/Medical Imaging Conference, Dresden, Germany, 19–25 October 2008. 959. Junnarkar, S.S.; O’Connor, P.; Vaska, P.; Fontaine, R. FPGA-Based Self-Calibrating Time-to-Digital Converter for Time-of-Flight Experiments. IEEE Trans. Nucl. Sci. 2009, 56, 2374–2379. doi:10.1109/TNS.2009.2025180. 960. Ozawa, Y.; Ida, T.; Sakurai, S.; Jiang, R.; Takahashi, R.; Kobayashi, H.; Shiota, R. Sar tdc architecture for one-shot timing measurement with full digital implementation. In Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), Xiamen, China, 6–9 November 2017. 961. Dinh, V.L.; Nguyen, X.T.; Lee, H.J. A New FPGA Implementation of a Time-to-Digital Converter Supporting Run-Time Estimation of Operating Condition Variation. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 27–30 May 2018. 962. Luan, D.V.; Truong, N.X.; Lee, H.J. An FPGA Implementation of a Time-to-Digital Converter with a Ring Oscillator and Buffers. In Proceedings of the 17th Annual International Conference on Electronics, Information, and Communication (ICEIC), Honolulu, HI, USA, 24–27 January 2018. 963. Avaroglu, E.; Tuncer, T.; Ozer, A.B.; Ergen, B.; Turk, M. A novel chaos-based post-processing for TRNG. Nonlinear Dyn. 2015, 81, 189–199. doi:10.1007/s11071-015-1981-9. 964. Boehl, E.; Lewis, M.; Galkin, S. A True Random Number Generator with On-Line Testability. In Proceedings of the 19th IEEE European Test Symposium (ETS), Paderborn, Germany, 26–30 May 2014. 965. Wieczorek, P.Z. Secure TRNG with Random Phase Stimulation. In Proceedings of the Conference on Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments, Wilga, Poland, 28 May–6 June 2017. doi:10.1117/12.2280979. 966. Jessa, M.; Matuszewski, L. Producing random bits with delay-line-based ring oscillators. Int. J. Electron. Telecommun. 2013, 59, 41–50. doi:10.2478/eletel-2013-0005. 967. Zalivako, S.; Ivaniuk, A. The use of physical unclonable functions for true random number sequences generation. Autom. Control Comput. Sci. 2013, 47, 156–164. doi:10.3103/S0146411613030085. 968. Ma, G.; Liang, H.; Yao, L.; Huang, Z.; Yi, M.; Xu, X.; Zhou, K. A Low-cost High-efficiency True Random Number Generator on FPGAs. In Proceedings of the 27th IEEE Asian Test Symposium (ATS), Hefei, China, 15–18 October 2018. doi:10.1109/ATS.2018.00021. 969. Sarkisla, M.A.; Ergun, S. An Area Efficient True Random Number Generator Based on Modified Ring Oscillators. In Proceedings of the 14th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Chengdu, China, 26–30 October 2018. 970. Garipcan, A.M.; Erdem, E. Hardware Design and Analysis of Ring Oscillator Based Noise Source for True Random Number Generators. In Proceedings of the International Conference on Artificial Intelligence and Data Processing (IDAP), Inonu Univ, Malatya, Turkey, 28–30 September 2018. 971. Martin, H.; Martin-Holgado, P.; Peris-Lopez, P.; Morilla, Y.; Entrena, L. On the Entropy of Oscillator-Based True Random Number Generators under Ionizing Radiation. Entropy 2018, 20. doi:10.3390/e20070513. 972. Sarkisla, M.A.; Ergun, S. Ring Oscillator Based Random Number Generator Using Wake-up and Shut-down Uncertainties. In Proceedings of the 3rd Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Hong Kong, China, Univ Sci & Technol, Hong Kong, China, Univ Sci & Technol Jockey Club Ins, Hong Kong, China„ China, 17–18 December 2018. 973. Zhou, Z.; Li, T.; Takahashi, T.; Ho, E. Design of a universal space vector PWM controller based on FPGA. In Proceedings of the 19th Annual IEEE Applied Power Electronics Conference, Aachen, Germany, 22–26 February 2004. 974. Pan, S.B.; Chen, Z.X.; Pan, J.M. Novel SVPWM method for DC rail resonant inverter. Zhongguo Dianji Gongcheng Xuebao/Proc. Chin. Soc. Electr. Eng. 2007, 27, 65–69. Computation 2019, xx, 5 77 of 115 975. Yuan, Z.; Fei-peng, X.; Zhao-yong, Z. Realization of an FPGA-Based space-vector PWM controller. In Proceedings of the CES/IEEE 5th International Power Electronics and Motion Control Conference, Shanghai Jiao Tong Univ, Shanghai, China, 14–16 August 2006. 976. Zhang, C.Y.; Li, Y.B.; Peng, Y.L.; Zhen, X.F. A direct phase control scheme for unity power factor three-phase Buck type rectifier based on SVPWM. In Proceedings of the 5th International Conference on Machine Learning and Cybernetics, Dalian, China, 13–16 August 2006. 977. Han, F.; Fang, J.; Liu, G. Design and implementation of SVPWM switching power amplifiers for active magnetic bearing. Diangong Jishu Xuebao/Trans. China Electrotech. Soc. 2009, 24, 119–124. 978. Vashishtha, S.; Rekha, K. A survey: Space vector PWM (SVPWM) in 3ph voltage source inverter (VSI). Int. J. Electr. Comput. Eng. 2018, 8, 11–18. doi:10.11591/ijece.v8i1.pp11-18. 979. Sumam, M.; Shiny, G. Rapid prototyping of high performance FPGA controller for an induction motor drive. In Proceedings of the 8th International Conference on Power and Energy Systems, ICPES 2018, Colombo, Sri Lanka, 21–22 December 2018. doi:10.1109/ICPESYS.2018.8626891. 980. Panda, A.; Rajput, P.; Shukla, B. FPGA implementation of 8, 16 and 32 bit LFSR with maximum length feedback polynomial using VHDL. In Proceedings of the International Conference on Communication Systems and Network Technologies, CSNT 2012, Rajkot, India, 11–13 May 2012. doi:10.1109/CSNT.2012.168. 981. Sewak, K.; Rajput, P.; Panda, A. FPGA implementation of 16 bit BBS and LFSR PN sequence generator: A comparative study. In Proceedings of the 2012 IEEE Students’ Conference on Electrical, Electronics and Computer Science: Innovation for Humanity, SCEECS 2012, Bhopal, India, 1–2 March 2012. doi:10.1109/SCEECS.2012.6184758. 982. Xiao-chen, G.; Min-xuan, Z. Uniform Random Number Generator using Leap-Ahead LFSR Architecture. In Proceedings of the International Conference on Computer and Communications Security, Hong Kong, China„ China, 5–6 December 2009. doi:10.1109/ICCCS.2009.11. 983. Kumar, A.; Saraswat, S.K.; Agrawal, T. Design of 4-bit LFSR on FPGA. In Proceedings of the 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Delhi, India, 3–5 July 2017. 984. Datta, D.; Datta, B.; Dutta, H.S. Design and Implementation of Multibit LFSR on FPGA to Generate Pseudorandom Sequence Number. In Proceedings of the 2nd International Conference on Devices for Integrated Circuit (DevIC), Kalyani, India, 23–24 March 2017. 985. Amsaad, F.; Sherif, A.; Dawoud, A.; Niamat, M.; Kose, S. A Novel FPGA-based LFSR PUF Design for IoT and Smart Applications. In Proceedings of the IEEE National Aerospace and Electronics Conference (NAECON), Dayton, OH, USA, 23–26 July 2018. 986. Shouqian, Y.; Lili, Y.; Weihai, C.; Zhaojin, W. Implementation of a multi-channel UART controller based on FIFO technique and FPGA. In Proceedings of the 2007 2nd IEEE Conference on Industrial Electronics and Applications, ICIEA 2007, Harbin, China, 23–25 May 2007. doi:10.1109/ICIEA.2007.4318890. 987. Jusoh, N.; Ibrahim, A.; Haron, M.; Sulaiman, F. An FPGA implementation of shift converter block technique on FIFO for UART. In Proceedings of the 2011 4th IEEE International RF and Microwave Conference, RFM 2011, Seremban, Malaysia, 12–14 December 2011. doi:10.1109/RFM.2011.6168758. 988. Ma, Y.; Zhang, T.; Li, J. Application of FIFO integrated by FPGA in high overload storage measurement system. Yi Qi Yi Biao Xue Bao/Chinese Journal of Scientific Instrument 2006, 27, 2350–2351. 989. Peng, L.; Youchun, M.; Jinming, L. Application of FIFO Integrated Into FPGA in the Image Acquisition and Storage System. In Proceedings of the 8th International Symposium on Test Measure, Chongqing, China, 23–26 August 2009. 990. Liu, W.; Lei, Y.; Ni, M.; Chai, X. Application of software FIFO in communication of multi-DSP. Jisuanji Gongcheng/Comput. Eng. 2005, 31, 228–230. 991. Zhang, X.; Wang, J.; Wang, Y.; Chen, D.; Lai, J. BRAM-based Asynchronous FIFO in FPGA with Optimized Cycle Latency. In Proceedings of the IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Xi’an, China, 29 October–1 November 2012. 992. Yu, X.F.; Liu, X.B.; Hu, B.L.; Wei, C.Y. Design of FIFO in high speed data storage system based on FPGA. Hedianzixue Yu Tance Jishu/Nucl. Electron. Detect. Technol. 2010, 30, 59–62. 993. Ji, X.; Jiang, H.; Xiao, C.; Wang, Y. Software FIFO based interconnection between DSP and FPGA in video encoding system. In Proceedings of the 2010 3rd International Congress on Image and Signal Processing, CISP 2010, Yantai, China, 16–18 October 2010. doi:10.1109/CISP.2010.5647310. Computation 2019, xx, 5 78 of 115 994. Ashour, H. Design, Simulation and Realization of a Parametrizable, Configurable and Modular Asynchronous FIFO. In Proceedings of the Proceedings of the Science and Information Conference (SAI), Science and Information Organization, London, UK, 28–30 July 2015. 995. Nakahara, H.; Sasao, T.; Nakanishi, H.; Iwai, K. An RNS FFT Circuit Using LUT Cascades Based on a Modulo EVMDD. In Proceedings of the 45th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2015, Waterloo, ON, Canada, 18–20 May 2015. doi:10.1109/ISMVL.2015.41. 996. Gerard, B.; Kammerer, J.G.; Merkiche, N. Contributions to the Design of Residue Number System Architectures. In Proceedings of the IEEE 22nd Symposium on Computer Arithmetic ARITH 22, Lyon, France, 22–24 June 2015. doi:10.1109/ARITH.2015.25. 997. Ningo, N.; Sone, M. Efficient key management FPGA-based cryptosystem using the RNS and iterative coding. Int. J. Inf. Commun. Technol. 2010, 2, 302–322. doi:10.1504/IJICT.2010.034973. 998. Olsen, E.B. RNS Hardware Matrix Multiplier for High Precision Neural Network Acceleration. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 27–30 May 2018. 999. Mensah, P.; Bankas, E.; Iddrisu, M. RNS Smith-Waterman Accelerator based on the moduli set 2n , 2n−1 , 2n−1 -1. In Proceedings of the 7th IEEE International Conference on Adaptive Science and Technology, ICAST 2018, Accra, Ghana, 22–24 August 2018. doi:10.1109/ICASTECH.2018.8506938. 1000. Chervyakov, N.I.; Babenko, M.G.; Kuchukov, V.A. Research of Effective Methods of Conversion from Positional Notation to RNS on FPGA. In Proceedings of the IEEE Russia Section Young Researchers in Electrical and Electronic Engineering Conference (EIConRus), St Petersburg Electrotechn Univ LETI, St Petersburg, Russia, 1–3 February 2017. 1001. Manabe, T.; Shibata, Y.; Oguri, K. FPGA Implementation of a Real-Time Super-Resolution System Using Flips and an RNS-Based CNN. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 2018, E101A, 2280–2289. doi:10.1587/transfun.E101.A.2280. 1002. Zabolotny, W.M. DMA implementations for FPGA-based data acquisition systems. In Proceedings of the Conference on Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments, Wilga, Poland, 28 May–6 June 2017. doi:10.1117/12.2280937. 1003. Bian, X.J.; Chen, F.S.; Long, F.L.; Chen, J.; Qiao, X.J. Research of DMA communication based on FPGA and DSP platform applied to digital quench detection device. Hedianzixue Yu Tance Jishu/Nucl. Electron. Detect. Technol. 2012, 32, 1366–1371. 1004. Rota, L.; Caselle, M.; Chilingaryan, S.; Kopmann, A.; Weber, M. A PCIe DMA Architecture for Multi-Gigabyte Per Second Data Transmission. IEEE Trans. Nucl. Sci. 2015, 62, 972–976. doi:10.1109/TNS.2015.2426877. 1005. Eckert, M.; Podebrad, I.; Klauer, B. Hardware Based Security Enhanced Direct Memory Access. In Proceedings of the 14th IFIP-TC 6 and TC-11 International Conference on Communications and Multimedia Security (CMS), Magdeburg, Germany, 25–26 September 2013. 1006. Jones, A.; Hoare, R.; Kourtev, I.; Fazekas, J.; Kusic, D.; Foster, J.; Boddie, S.; Muaydh, A. In Proceedings of the 11th IEEE International Conference on Electronics, Circuits and Systems, Tel Aviv, Israel, 13–15 December 2004. 1007. Hoare, R.; Tung, S.; Werger, K. A 64-way SIMD processing architecture on an FPGA. In Proceedings of the Proceedings of the Fifteenth IASTED International Conference on Parallel and Distributed Computing and Systems, Marina del Rey, CA, USA, 3–5 November 2003. 1008. Yi, H.; Peng, X.j.; Jian, D.; Cao, X.k. A Novel Simulation Technique for Scalable SIMD Architectures based on Limited FPGA Resource. In Proceedings of the International Conference on Software, Multimedia and Communication Engineering, Hong Kong, China, 20–21 September 2015. 1009. He, Y.; Ren, J.; Wen, M.; Yang, Q.; Wu, N.; Zhang, C.; Guo, M. Research on FPGA-based paging-simulation model for SIMD architecture. Jisuanji Yanjiu Yu Fazhan/Comput. Res. Dev. 2011, 48, 9–18. 1010. Hasan, L.; Khawaja, Y.; Bais, A. A systolic array architecture for the smith-waterman algorithm with high performance cell design. In Proceedings of the Informatics 2008 and Data Mining 2008, MCCSIS’08 - IADIS Multi Conference on Computer Science and Information Systems, Amsterdam, 22–27 July 2008. 1011. Karra, M.C.; Bekakos, M.P.; Milovanovic, I.Z.; Milovanovic, E.I. FPGA Implementation of a Unidirectional Systolic Array Generator for Matrix-Vector Multiplication. In Proceedings of the IEEE International Conference on Signal Processing and Communications, Dubai, United Arab Emirates, 24–27 November 2007. Computation 2019, xx, 5 79 of 115 1012. Wang, N.C.; Biglieri, E.; Yao, K. Systolic Arrays for Lattice-Reduction-Aided MIMO Detection. J. Commun. Networks 2011, 13, 481–493. doi:10.1109/JCN.2011.6112305. 1013. Woods, R.F.; Mccanny, J.V.; Mcwhirter, J.G. From bit level systolic arrays to HDTV processor chips. J. Signal Process. Syst. Signal Image Video Technol. 2008, 53, 35–49. doi:10.1007/s11265-007-0132-z. 1014. Karra, M.C.; Bekakos, M.P. A FPGA-based systolic array prototype implementing the quadrant interlocking factorization method. J. Supercomput. 2006, 37, 319–331. doi:10.1007/s11227-006-6633-x. 1015. Huang, K.; Xie, G.; Li, R.; Xiong, S. Fast and deterministic hash table lookup using discriminative bloom filters. J. Netw. Comput. Appl. 2013, 36, 657–666. doi:10.1016/j.jnca.2012.12.031. 1016. Mcvicar, N.; Lin, C.C.; Hauck, S. K-mer Counting Using Bloom Filters with an FPGA-Attached HMC. In Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, USA, 30 April–2 May 2017. doi:10.1109/FCCM.2017.23. 1017. Cho, J.M.; Choi, K. An FPGA Implementation of High-Throughput Key-Value Store Using Bloom Filter. In Proceedings of the International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, 28–30 April 2014. 1018. Chen, Y.; Schmidt, B.; Maskell, D.L. A Reconfigurable Bloom Filter Architecture for BLASTN. In Proceedings of the 22nd International Conference on Architecture of Computing Systems, Delft Univ Technol, Delft, The Netherlands, 10–13 March 2009. 1019. Zhou, Z.; Fu, W.L.; Song, T.; Liu, Q.Y. Fast URL lookup using parallel bloom filters. Tien Tzu Hsueh Pao/Acta Electron. Sin. 2015, 43, 1833–1840. doi:10.3969/j.issn.0372-2112.2015.09.023. 1020. Yu, H.; Cong, R.; Chen, L.; Lei, Z. Blocking pornographic, illegal websites by internet host domain using FPGA and bloom filter. In Proceedings of the 2010 2nd IEEE International Conference on Network Infrastructure and Digital Content, IC-NIDC 2010, Beijing, China, 24–26 September 2010. doi:10.1109/ICNIDC.2010.5657855. 1021. Banks, J.; Carson, J.; Nelson, B. Discrete-event System Simulation; Prentice-Hall international series in industrial and systems engineering; Prentice Hall: Upper Saddle River, NJ, USA, 1996. 1022. Word, D.; Bednar, R.; Zenor, J.J.; Hingorani, N.G. High-Speed Real-Time Simulation for Power Electronic Systems. Simul.-Trans. Soc. Model. Simul. Int. 2008, 84, 441–456. doi:10.1177/0037549708098830. 1023. Kiffe, A.; Riediger, W.; Schulte, T. Advanced preprocessing and correction-methods for automated generation of FPGA-based simulation of power Electronics. In Proceedings of the 2013 15th European Conference on Power Electronics and Applications, EPE 2013, Lille, France, 2–6 September 2013. doi:10.1109/EPE.2013.6634677. 1024. Futo, A.; Kokenyesi, T.; Varjasi, I.; Suto, Z.; Vajk, I.; Balogh, A.; Balazs, G.G. Real-Time HIL Simulation of the Discontinuous Conduction Mode in Voltage Source PWM Power Converters. J. Power Electron. 2017, 17, 1535–1544. doi:10.6113/JPE.2017.17.6.1535. 1025. Ni, Y.; Zhang, J. Design and Simulation of A Rectifier Controller Based on Fuzzy PID. In Proceedings of the International Conference on Logistics Engineering, Management and Computer Science (LEMCS), Shenyang, China, 29–31 July 2015. 1026. Kiffe, A.; Schulte, T. FPGA-based Hardware-in-the-Loop Simulation of a Rectifier with Power Factor Correction. In Proceedings of the 17th European Conference on Power Electronics and Applications (EPE ECCE-Europe), Geneva, Switzerland, 8–10 September 2015. 1027. Kidokoro, H.; Nakahara, M. FPGA-Based Hardware-in-the-Loop Simulator of High Switching Frequency Power Converters. In Proceedings of the IEEE International Telecommunications Energy Conference (INTELEC), Namba, China, 18–22 October 2015. 1028. Matar, M.; Iravani, R. FPGA Implementation of the Power Electronic Converter Model for Real-Time Simulation of Electromagnetic Transients. IEEE Trans. Power Deliv. 2010, 25, 852–860. doi:10.1109/TPWRD.2009.2033603. 1029. Dinavahi, V.; Iravani, R.; Bonert, R. Design of a real-time digital simulator for a D-STATCOM system. IEEE Trans. Ind. Electron. 2004, 51, 1001–1008. doi:10.1109/TIE.2004.834954. 1030. Blanchette, H.F.; Ould-Bachir, T.; David, J.P. A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters. IEEE Trans. Ind. Electron. 2012, 59, 4555–4567. doi:10.1109/TIE.2011.2182021. Computation 2019, xx, 5 80 of 115 1031. Ould-Bachir, T.; Blanchette, H.F.; Al-Haddad, K. A Network Tearing Technique for FPGA-Based Real-Time Simulation of Power Converters. IEEE Trans. Ind. Electron. 2015, 62, 3409–3418. doi:10.1109/TIE.2014.2365752. 1032. Matar, M.; Paradis, D.; Iravani, R. Real-time simulation of modular multilevel converters for controller hardware-in-the-loop testing. IET Power Electron. 2016, 9, 42–50. doi:10.1049/iet-pel.2015.0012. 1033. Dinavahi, V.; Iravani, M.; Bonert, R. Real-time digital simulation and experimental verification of a D-STATCOM interfaced with a digital controller. Int. J. Electr. Power Energy Syst. 2004, 26, 703–713. doi:10.1016/j.ijepes.2004.05.003. 1034. Bachir, T.O.; Dufour, C.; Belanger, J.; Mahseredjian, J.; David, J.P. A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits. Math. Comput. Simul. 2013, 91, 167–177. doi:10.1016/j.matcom.2012.07.021. 1035. Dufour, C.; Cense, S.; Belanger, J. FPGA-based switched reluctance motor drive and DC-DC converter models for high-bandwidth HIL real-time simulator. In Proceedings of the 2013 15th European Conference on Power Electronics and Applications, EPE 2013, Lille, France, 2–6 September 2013. doi:10.1109/EPE.2013.6632007. 1036. Figueroa, H.P.; Bastos, J.L.; Monti, A.; Dougal, R. A modular real-time simulation platform based on the virtual test bed. In Proceedings of the IEEE International Symposium on Industrial Electronics, Montreal, QC, Canada, 9–13 July 2006. doi:10.1109/ISIE.2006.295700. 1037. Le-Huy, P.; Guerette, S.; Dessaint, L.A.; Le-Huy, H. Real-time simulation of power Electronics in power systems using an FPGA. In Proceedings of the 19th IEEE Canadian Conference on Electrical and Computer Engineering, Ottawa, Canada, 7–10 May 2006. 1038. Razzaghi, R.; Mitjans, M.; Rachidi, F.; Paolone, M. An automated FPGA real-time simulator for power Electronics and power systems electromagnetic transient applications. Electr. Power Syst. Res. 2016, 141, 147–156. doi:10.1016/j.epsr.2016.07.022. 1039. Ould-Bachir, T.; Saad, H.; Dennetiere, S.; Mahseredjian, J. CPU/FPGA-Based Real-Time Simulation of a Two-Terminal MMC-HVDC System. IEEE Trans. Power Deliv. 2017, 32, 647–655. doi:10.1109/TPWRD.2015.2508381. 1040. Montano, F.; Ould-Bachir, T.; David, J.P. An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters. IEEE Trans. Ind. Electron. 2018, 65, 636–644. doi:10.1109/TIE.2017.2716880. 1041. Matar, M.; Iravani, R. The Reconfigurable-Hardware Real-Time and Faster-Than-Real-Time Simulator for the Analysis of Electromagnetic Transients in Power Systems. IEEE Trans. Power Deliv. 2013, 28, 619–627. doi:10.1109/TPWRD.2012.2229723. 1042. Bahri, I.; Naouar, M.W.; Monmasson, E.; Slama-Belkhodja, I.; Charaabi, L. Design of an FPGA-Based Real-Time Simulator for Electrical System. In Proceedings of the 13th International Power Electronics and Motion Control Conference, Poznan, Poland, 1–3 September 2008. doi:10.1109/EPEPEMC.2008.4635458. 1043. Wang, X.; Zhang, B.; Chen, X. Implementation of fine granularity parallelization in power system real-time simulation. Tianjin Daxue Xuebao (Ziran Kexue Yu Gongcheng Jishu Ban)/J. Tianjin Univ. Sci. Technol. 2016, 49, 513–519. doi:10.11784/tdxbz201506073. 1044. Gregoire, L.A.; Fortin-Blanchette, H.; Al-Haddad, K.; Li, W.; Belanger, J. Real-Time Simulation of Modular Multilevel Converter on FPGA with sub-microsecond Time-Step. In Proceedings of the 40th Annual Conference of the IEEE-Industrial-Electronics-Society (IECON), Dallas, TX, USA, 29 October–1 November 2014. 1045. Liu, C.; Ma, R.; Bai, H.; Gechter, F.; Gao, F. A new approach for FPGA-based real-time simulation of power electronic system with no simulation latency in subsystem partitioning. Int. J. Electr. Power Energy Syst. 2018, 99, 650–658. doi:10.1016/j.ijepes.2018.01.053. 1046. Zhang, H.; Sun, J. FPGA-Based Simulation of Power Electronics Using Iterative Methods; IEEE: 6, 2014; pp. 2202–2207. In Proceedings of the International Power Electronics Conference (IPEC-ECCE-ASIA), Hiroshima, Japan, 18–21 May 2014. 1047. Jiang, Z.; Hossain, S.; Huang, H. A Distributed, Real-Time Simulation Platform for Aerospace Power System Design, Testing and Evaluation. In Proceedings of the IEEE National Aerospace and Electronics Conference (NAECON) / Ohio Innovation Summit (OIS) / IEEE Symposium on Monitoring and Surveillance Research, Dayton, OH, USA, 25–29 July 2016. Computation 2019, xx, 5 81 of 115 1048. Hadizadeh, A.; Hashemi, M.; Labbaf, M.; Parniani, M. A Matrix-Inversion Technique for FPGA-Based Real-Time EMT Simulation of Power Converters. IEEE Trans. Ind. Electron. 2019, 66, 1224–1234. doi:10.1109/TIE.2018.2833058. 1049. Heras Cervantes, M.; Garcia Ramirez, M.C.; Correa Gomez, J.; Tellez Anguiano, A.C.; Martinez Cardenas, F. Real-Time Simulation of a Buck Converter for educational purposes in a LabVIEW (R)-programmed FPGA. In Proceedings of the IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC), Ixtapa, Mexico, 5–7 November 2014. 1050. Wang, K.; Xu, J.; Li, G.; Tai, N.; Tong, A.; Hou, J. A Generalized Associated Discrete Circuit Model of Power Converters in Real-Time Simulation. IEEE Trans. Power Electron. 2019, 34, 2220–2233. doi:10.1109/TPEL.2018.2845658. 1051. Gregoire, L.A.; Wang, W.; Sleiman, M.; Al-Haddad, K. Benchmarking of Real-Time Simulation Model of Modular Multilevel Converter. In Proceedings of the 43rd Annual Conference of the IEEE-Industrial-Electronics-Society (IECON), Beijing, China, 29 October–1 November 2017. 1052. Wang, Y.; Liu, C.; Li, G. FPGA-based Real-time Modeling of Modular Multilevel Converters and Hardware-in-the-loop Simulation [Ji Yu FPGADe Mo Kuai Hua Duo Dian Ping Huan Liu Qi Shi Shi Fang Zhen Jian Mo Yu Ying Jian Zai Huan Shi Yan ]. Zhongguo Dianji Gongcheng Xuebao/Proc. Chin. Soc. Electr. Eng. 2018, 38, 3912–3920. doi:10.13334/j.0258-8013.pcsee.170437. 1053. Heras Cervantes, M.; Garcia Ramirez, M.C.; Martinez Cardenas, F.; Tellez Anguiano, A.C.; Correa Gomez, J. FPGA-Based Real-Time Simulation of a Full Bridge-RL load SPWM Inverte. In Proceedings of the IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC), Morelia, Mexico, 13–15 November 2013. 1054. Bai, H.; Luo, H.; Liu, C.; Ma, R.; Paire, D.; Gao, F. FPGA-based Real-Time Simulation of Floating Interleaved Boost Converter for FCEV Powertrain; IEEE: 6, 2018; pp. 90–95. In Proceedings of the IEEE Transportation and Electrification Conference and Expo (ITEC), Long Beach, CA, USA, 13–15 June 2018. 1055. Leal, M.S.R.; Simoes, L.D.; Franca, R.L.S.; Leal, M.M.; Costa, F.B.; Taveiros, F.E. Methodology to Perform Real-Time Simulation of Power Systems Using an FPGA-Based Platform. In Proceedings of the 3rd Workshop on Communication Networks and Power Systems (WCNPS), Univ Brasilia, Brasilia, Brazil, 7–9 November 2018. 1056. Zhu, J.; Teng, G.; Qin, Y.; Hu, H. Multi-FPGA Based Real-time Simulation System for Power Electronics. Dianli Xitong Zidonghua/Autom. Electr. Power Syst. 2017, 41, 137–143. doi:10.7500/AEPS20160907050. 1057. Pellauer, M.; Adler, M.; Kinsy, M.; Parashar, A.; Emer, J. HAsim: FPGA-Based High-Detail Multicore Simulation Using Time-Division Multiplexing. In Proceedings of the 17th IEEE International Symposium on High-Performance Computer Architecture (HPCA), San Antonio, TX, USA, 12–16 February 2011. 1058. Straka, M.; January, K.; Kotasek, Z. SEU simulation framework for Xilinx FPGA: First step towards testing fault tolerant systems. In Proceedings of the 2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011, Oulu, Finland, 31 August –2 September 2011. doi:10.1109/DSD.2011.32. 1059. Papamichael, M. Fast scalable FPGA-based Network-on-Chip simulation models. In Proceedings of the 9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011, Cambridge, UK, 11–13 July 2011. doi:10.1109/MEMCOD.2011.5970513. 1060. Vaidya, P.; Lee, J.J. Simulation of hybrid computer architectures: simulators, methodologies and recommendations. In Proceedings of the International Conference on Very Large Scale Integration, Georgia Inst Technol, Atlanta, GA, USA, 15–17 October 2007. 1061. Chen, X.; Zhang, G.; Wang, H.; Wu, R.; Wu, P.; Zhang, L. MRP: Mix Real Cores and Pseudo Cores for FPGA-based Chip-multiprocessor Simulation. In Proceedings of the Conference on Design Automation Test in Europe (DATE), Alpexpo Congress Center, Grenoble, France, 9–13 March 2015. 1062. Graas, E.; Brown, E.; Lee, R. An FPGA-based approach to high-speed simulation of conductance-based neuron models. Neuroinformatics 2004, 2, 417–435. doi:10.1385/NI:2:4:417. 1063. Bailey, J.A.; Wilcock, R.; Wilson, P.R.; Chad, J.E. Behavioral simulation and synthesis of biological neuron systems using synthesizable VHDL. Neurocomputing 2011, 74, 2392–2406. doi:10.1016/j.neucom.2011.04.001. 1064. Pourhaj, P.; Teng, D.H.Y. FPGA based pipelined architecture for action potential simulation in biological neural systems. In Proceedings of the 23rd Canadian Conference on Electrical and Computer Engineering (CCECE), Calgary, AB, Canada, 2–5 May 2010. Computation 2019, xx, 5 82 of 115 1065. Liang, Z.; Huang, C. The Simulation of neural oscillations during propofol anesthesia based on the FPGA platform. Springer Verlag: Berlin/Heidelberg, Germany, 2018; Volume 459. doi:10.1007/978-981-10-6496-8_10. 1066. Quinn, H.M.; Black, D.A.; Robinson, W.H.; Buchner, S.P. Fault Simulation and Emulation Tools to Augment Radiation-Hardness Assurance Testing. IEEE Trans. Nucl. Sci. 2013, 60, 2119–2142. doi:10.1109/TNS.2013.2259503. 1067. Ke-Ying, Z.; Hong-Xia, G.; Yin-Hong, L.; Ru-Yu, F.; Wei, C.; Dong-Sheng, L.; Gang, G.; Yi-Hua, Y. First principles simulation technique for characterizing single event effects. Chin. Phys. B 2011, 20. doi:10.1088/1674-1056/20/6/068501. 1068. Bernardeschi, C.; Cassano, L.; Domenici, A.; Gennaro, G.; Pasquariello, M. Simulated injection of radiation-induced logic faults in FPGAs. In Proceedings of the 3rd International Conference on Advances in System Testing and Validation Lifecycle, VALID 2011, Barcelona, Spain, 23–29 October 2011. 1069. Grecki, M. VHDL Simulation considering Single Event Upsets (SEUs). In Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings, Boston, MA, USA, 7–11 May 2006. 1070. Abbes, H.; Ben Ayed, M.; Abid, H.; Abid, M. Design verification based on Hardware-In-the-Loop simulation for photovoltaic system. In Proceedings of the International Multi-Conference on Systems, Signals and Devices (SSD), Mahdia, Tunisia, 16–19 March 2015. 1071. Rakotozafy, M.; Poure, P.; Saadate, S.; Bordas, C.; Leclere, L. Real-time digital simulation of power Electronics systems with Neutral Point Piloted multilevel inverter using FPGA. Electr. Power Syst. Res. 2011, 81, 687–698. doi:10.1016/j.epsr.2010.10.034. 1072. Debreceni, T.; Koekenyesi, T.; Sueto, Z.; Varjasi, I. FPGA-based Real-Time Hardware-In-the-Loop Simulator of a Mini Solar Power Station. In Proceedings of the IEEE International Energy Conference (ENERGYCON), Dubrovnik, Croatia, 13–16 May 2014. 1073. Chekired, F.; Larbes, C.; Mellit, A. FPGA-based real time simulation of ANFIS-MPPT controller for photovoltaic systems. Int. Rev. Model. Simul. 2011, 4, 2361–2366. 1074. Li, P.; Wang, Z.; Ding, C.; Yu, H.; Wang, C. A Design of Grid-connected PV System for Real-time Transient Simulation Based on FPGA. In Proceedings of the General Meeting of the IEEE-Power-and-Energy-Society, Denver, CO, USA, 26–30 July 2015. 1075. Handong, B.; Zhiguo, Z.; Zhiwen, L. Design and Implementation of an FPGA-based Real Time Simulation System for Photovoltaic Power Generation; IEEE: 5, 2014. In Proceedings of the IEEE Transportation Electrification Conference and Expo (ITEC Asia-Pacific), Beijing, China, 31 August–3 September 2014. 1076. Cie, Z.; Wang, Z.; Li, P.; Ding, C. A Real-time Transient Simulator of Grid-connected Photovoltaic/Battery System Based on FPGA. In Proceedings of the 5th International Conference on Electric Utility Deregulation and Restructuring and Power Technologies (DRPT), Changsha, China, 26–29 November 2015. 1077. Palahalli, H.; Huo, Y.; Gruosso, G. Real Time Simulation of Photovoltaic System using FPGA. In Proceedings of the International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM), Amalfi, Italy, 20–22 June 2018. 1078. Li, F.; Wu, F.; Li, M.; Xie, Z.; Zhang, X.; Xu, J. Research on Real-time Simulation and Modeling of High-permeability Distributed Photovoltaic Power Generation Clusters. In Proceedings of the 2018 IEEE International Power Electronics and Application Conference and Exposition, PEAC 2018, Shenzhen, China, 4–7 November 2018. doi:10.1109/PEAC.2018.8590311. 1079. Podgorski, P.; Scislowski, D.; Kowalinski, M.; Mrozek, T.; Steslicki, M.; Barylak, J.; Barylak, A.; Sylwester, J.; Krucker, S.; Hurford, G.J.; et al. Hardware simulator of Caliste-SO detectors for STIX instrument. In Proceedings of the Conference on Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments, Poland, 27 May–2 June 2013. doi:10.1117/12.2035285. 1080. Idris, F.M.; Abdullah, W.A.T.W.; Ibrahim, Z.A.; Kamaluddin, B. Design and Simulation of FPGA-Based Readout Control of A High-Energy Electron-Proton Collision Calorimeter. In Proceedings of the International Conference on Neutron and X-Ray Scattering 2009, Kuala Lumpur, Malaysia, 29 June–1 July 2009. 1081. Brekke, N.; Roehrich, D.; Ullaland, K.; Gruner, R. Trigger Performance Simulation of a High Speed ADC-Based TOF-PET Read-Out System. IEEE Trans. Nucl. Sci. 2012, 59, 1910–1914. doi:10.1109/TNS.2012.2197413. 1082. Zhou, Y.; Mei, T. FPGA based real time simulation for electrical machines. IFAC Proc. Vol. 2005, 38, 256–261. Computation 2019, xx, 5 83 of 115 1083. Bo, Z.; Xu, J. Interpolation method in hardware-in-the-loop simulation for brushless DC motor. In Proceedings of the 2014 11th World Congress on Intelligent Control and Automation, WCICA 2014, Shenyang, China, 29 June–4 July 2014. doi:10.1109/WCICA.2014.7053720. 1084. Kredo, Kurtis, I.; Zenor, J.; Bednar, R.; Crosbie, R. FPGA-Accelerated Simulink Simulations of Electrical Machines. In Proceedings of the IEEE Electric Ship Technologies Symposium (ESTS), Alexandria, VA, USA, 21–24 June 2015. 1085. Filatov, V.; Chumaeva, M.; Porvatov, A. Simulation of the electric drive motor in numerically controlled metal-cutting machines. Russ. Eng. Res. 2015, 35, 447–451. doi:10.3103/S1068798X15060039. 1086. Matar, M.; Iravani, R. Massively Parallel Implementation of AC Machine Models for FPGA-Based Real-Time Simulation of Electromagnetic Transients. IEEE Trans. Power Deliv. 2011, 26, 830–840. doi:10.1109/TPWRD.2010.2086499. 1087. Dufour, C.; Cense, S.; Jalili-Marandi, V.; Belanger, J. Review of state-of-the-art solver solutions for HIL simulation of power systems, power electronic and motor drives. In Proceedings of the 2013 15th European Conference on Power Electronics and Applications, EPE 2013, Lille, France, 2–6 September 2013. doi:10.1109/EPE.2013.6632001. 1088. Mojlish, S.; Erdogan, N.; Levine, D.; Davoudi, A. Review of Hardware Platforms for Real-Time Simulation of Electric Machines. IEEE Trans. Transp. Electrif. 2017, 3, 130–146. doi:10.1109/TTE.2017.2656141. 1089. Tola, S.; Sengupta, M. Real-time simulation of an induction motor in different reference frames on a fpga platform. In Proceedings of the IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES), Cent Power Res Inst, Bengaluru, India, 16–19 December 2012. 1090. Tzanis, N.; Proiskos, G.; Birbas, M.; Birbas, A. FPGA-assisted distribution grid simulator. In Proceedings of the 14th International Symposium on Applied Reconfigurable Computing, ARC 2018, Santorini, Greece, 2–4 May 2018. doi:10.1007/978-3-319-78890-6_51. 1091. Zhang, B.; Fu, S.; Jin, Z.; Hu, R. A Novel FPGA-Based Real-Time Simulator for Micro-Grids. Energies 2017, 10. doi:10.3390/en10081239. 1092. Zhang, B.; Zhao, D.; Jin, Z.; Wu, Y. Multivalued Coefficient Prestorage and Block Parallel Method for Real-Time Simulation of Microgrid on FRTDS. Energies 2017, 10. doi:10.3390/en10091248. 1093. Chengdi, D.; Peng, L.; Wang, C.; Wang, Z.; Dawei, Y.; Jin, Z.; Zheng, L. A design and implementation of FPGA-based real-time simulator for distribution system with DG integration. In Proceedings of the 2016 China International Conference on Electricity Distribution, CICED 2016, Xi’an, China, 10 –13 August 2016. doi:10.1109/CICED.2016.7576075. 1094. Wang, X.; Zhang, B.; Qiao, P. A Block Hierarchical Parallel Method for Real-Time Simulation of Microgrid. Diangong Jishu Xuebao/Trans. China Electrotech. Soc. 2017, 32, 104–111. 1095. Zhai, X.; Lin, C.; Gregoire, L.A.; Wang, W.; Li, W.; Zhang, F.; Joos, G. Multi-rate Real-time Simulation of Modular Multilevel Converter for HVDC Grids Application. In Proceedings of the 43rd Annual Conference of the IEEE-Industrial-Electronics-Society (IECON), Beijing, China, 29 October–1 November 2017. 1096. Monga, M.; Roggow, D.; Karkee, M.; Sun, S.; Tondehal, L.K.; Steward, B.; Kelkar, A.; Zambreno, J. Real-time simulation of dynamic vehicle models using a high-performance reconfigurable platform. Microprocess. Microsyst. 2015, 39, 720–740. doi:10.1016/j.micpro.2015.08.014. 1097. Zhang, Y.y.; Liu, C.g.; Yang, G.j. Electric Drive Armored Vehicle Real-time Simulation Research. In Proceedings of the 3rd International Conference on Machinery, Materials Science and Energy Engineering (ICMMSEE), Wuhan, China, 18–19 July 2015. 1098. Ciornei, S.M.; Nemes, R.O.; Ruba, M.; Husar, C.; Hedesiu, H.; Martis, C. Real-Time Simulation of a Complete Electric Vehicle Based on NI VeriStand Integration Platform. In Proceedings of the 10th International Conference and Expositions on Electrical and Power Engineering (EPE), Iasi,Romania, 18–19 October 2018. 1099. Zhang, Y.; Liu, C.; Ma, X.; Liao, Z. Real-time simulation research on electric drive system of armored vehicle. Xitong Fangzhen Xuebao/J. Syst. Simul. 2017, 29, 107–114. doi:10.16182/j.issn1004731x.joss.201701015. 1100. Jung, Y.K.; Mak, F.; Qingele, F.; Alzahid, I. WEX-HIL: Design of a Wireless Extensible Hardware-in-the-loop Real-time Simulator for Electric Vehicle Applications. In Proceedings of the IEEE Frontiers in Education Conference (FIE), Gannon Univ, Erie, PA, USA, 12–15 October 2016. 1101. Mohammed, O.A.; Abed, N.Y. Real-time simulation of electric machine drives with hardware-in-the-loop. Compel Int. J. Comput. Math. Electr. Electron. Eng. 2008, 27, 929–938. doi:10.1108/03321640810878351. Computation 2019, xx, 5 84 of 115 1102. Popescu, S.; Gontean, A.; Budura, G. Hardware Co-Simulation of the BPSK and QPSK Systems on FPGA. In Proceedings of the 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems (PDeS), Brno, Czech Republic, 23–25 May 2012. 1103. Hao, W.; Shen, M.; Zhao, H. Optimal design and simulation for multi-rate symbol timing recovery in software radio QPSK demodulation. In Proceedings of the 3rd International Conference on Computational Electromagnetics and its Applications, Beijing, China, 1–4 November 2004. 1104. Wang, T.; Wang, Q.; Liu, D.; Liao, M.; Wang, K.; Cao, L.; Zhao, L.; Iyer, R.; Illikkal, R.; Du, J.; Wang, L. Hardware/Software Co-Simulation for Last Level Cache Exploration. In Proceedings of the IEEE International Conference on Networking, Architecture, and Storage, Zhangjiajie, China, 9–11 July 2009. doi:10.1109/NAS.2009.66. 1105. Thompson, C.; Gould, M.; Topham, N. High Speed Cycle-Approximate Simulation of Embedded Cache-Incoherent and Coherent Chip-Multiprocessors. Int. J. Parallel Program. 2018, 46, 1247–1282. doi:10.1007/s10766-018-0566-x. 1106. Kriston, A.; Inzelt, G.; Farago, I.; Szabo, T. Simulation of the transient behavior of fuel cells by using operator splitting techniques for real-time applications. Comput. Chem. Eng. 2010, 34, 339–348. doi:10.1016/j.compchemeng.2009.11.006. 1107. Ma, R.; Liu, C.; Zheng, Z.; Gechter, F.; Briois, P.; Gao, F. CPU-FPGA based real-time simulation of fuel cell electric vehicle. Energy Convers. Manag. 2018, 174, 983–997. doi:10.1016/j.enconman.2018.08.099. 1108. Wang, H.X.; Quan, Y.H.; Xing, M.D.; Zhang, S.H. Fast realization of SAR echo simulation based on FPGA. Xi Tong Gong Cheng Yu Dian Zi Ji Shu/Syst. Eng. Electron. 2010, 32, 2284–2289. doi:10.3969/j.issn.1001-506X.2010.11.06. 1109. Zheng, Z.; Li, J.Q.; Wu, S.L. Design of a radar signal simulator based on virtex-II series FPGA. J. Beijing Inst. Technol. (English Ed.) 2006, 15, 106–110. 1110. Benigni, A.; Adler, F.; Mura, F.; Dick, C.; De, D.R.; Monti, A. A new advanced wind-farm real-time simulator platform. In Proceedings of the 3rd EPE Wind Energy Chapter Symposium 2010, Stafford, UK, 15–16 April 2010. 1111. Ma, X.; Cross, P. A novel condition monitoring and real-time simulation system for wind turbines. In Proceedings of the European Wind Energy Conference and Exhibition, EWEC 2013, Vienna, Austria, 4–7 February 2013. 1112. Shang-Ping, W.; Qiao-Mei, M.; Ya-Ling, Z.; You-Sheng, L. An Authentication Protocol for RFID Tag and its Simulation. J. Netw. 2011, 6, 446–453. doi:10.4304/jnw.6.3.446-453. 1113. Wei, L.; Ma, L. Design and simulation of RFID special IP core based on FPGA technolgy. In Proceedings of the 2010 2nd International Conference on Industrial and Information Systems, IIS 2010, Dalian, China,10–11 July 2010. doi:10.1109/INDUSIS.2010.5565709. 1114. Keane, J.; Bradley, C.; Ebeling, C. A compiled accelerator for biological cell signaling simulations. In Proceedings of the ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004, Monterey, CA, USA, 22–24 February 2004. 1115. Chapuis, Y.A.; Zhou, L.; Casner, D.; Ai, H.; Herve, Y. FPGA-in-the-loop for control emulation of distributed MEMS simulation using VHDL-AMS. In Proceedings of the 1st Workshop on Hardware and Software Implementation and Control of Distributed MEMS, dMEMS 2010, Besancon, France, 28–29 June 2010. doi:10.1109/dMEMS.2010.21. 1116. Kelmelis, E.J.; Durbano, J.P.; Humphrey, J.R.; Ortiz, F.E.; Curt, P.F. Modeling and simulation of nanoscale devices with a desktop supercomputer. In Proceedings of the Conference on Nanomodeling II, San Diego, CA, USA, 13–15 August 2006. doi:10.1117/12.681085. 1117. Frank, M.P.; Oniciuc, L.; Meyer-Baese, U.H.; Chiorescu, I. A space-efficient quantum computer simulator suitable for high-speed FPGA implementation. In Proceedings of the Conference on Quantum Information and Computation VII, Orlando, FL, USA, 16–17 April 2009. doi:10.1117/12.817924. 1118. Giannoutakis, K.; Makaratzis, A.; Tzovaras, D.; Filelis-Papadopoulos, C.; Gravvanis, G. On the power consumption modeling for the simulation of heterogeneous HPC clouds. In Proceedings of the 1st International Workshop on Cloud-Next Generation, CloudNG 2017, co-located with European Conference on Computer Systems, EuroSys 2017, Belgrade, Serbia, 23–26 April 2017. doi:10.1145/3068126.3068127. 1119. Zarandy, A.; Nagy, Z.; Vanek, B.; Zsedrovits, T.; Kiss, A.; Nemeth, M. A five-camera vision system for UAV visual attitude calculation and collision warning. In Proceedings of the 9th International Computation 2019, xx, 5 85 of 115 Conference on Computer Vision Systems, ICVS 2013, Saint Petersburg, Russia, 16–18 July 2013. doi:10.1007/978-3-642-39402-7_2. 1120. Carey, S.J.; Barr, D.R.W.; Dudek, P. Low power high-performance smart camera system based on SCAMP vision sensor. J. Syst. Archit. 2013, 59, 889–+. doi:10.1016/j.sysarc.2013.03.016. 1121. Deepa, P.; Vasanthanayaki, C. FPGA based efficient on-chip memory for image processing algorithms. Microelectron. J. 2012, 43, 916–928. doi:10.1016/j.mejo.2012.05.001. 1122. Malik, P. Hardware architecture dedicated for arithmetic mean filtration implemented in FPGA. In Proceedings of the 8th International Conference on Computer Engineering and Systems (ICCES), Cairo, Egypt, 26–28 November 2013. 1123. Basheer, J.; Murugesh, V. FPGA implementation of a novel Gaussian filter using power optimized approximate adders. Indones. J. Electr. Eng. Comput. Sci. 2018, 11, 1048–1059. doi:10.11591/ijeecs.v11.i3.pp1048-1059. 1124. Podlubne, A.; Haase, J.; Kalms, L.; Akguen, G.; Ali, M.; Khan, H.u.H.; Kamal, A.; Goehringer, D. Low Power Image Processing Applications on FPGAs using Dynamic Voltage Scaling and Partial Reconfiguration. In Proceedings of the 12th Conference on Design and Architectures for Signal and Image Processing (DASIP), Porto, Portugal, 10–12 October 2018. 1125. Parlak, M.; Hamzaoglu, I. Low power H.264 deblocking filter hardware implementations. IEEE Trans. Consum. Electron. 2008, 54, 808–816. doi:10.1109/TCE.2008.4560164. 1126. Adibelli, Y.; Parlak, M.; Hamzaoglu, I. Pixel Similarity Based Computation and Power Reduction Technique for H.264 Intra Prediction. IEEE Trans. Consum. Electron. 2010, 56, 1079–1087. doi:10.1109/TCE.2010.5506042. 1127. Aysu, A.; Sayilar, G.; Hamzaoglu, I. A Low Energy Adaptive Hardware for H.264 Multiple Reference Frame Motion Estimation. IEEE Trans. Consum. Electron. 2011, 57, 1377–1383. doi:10.1109/TCE.2011.6018897. 1128. Adibelli, Y.; Parlak, M.; Hamzaoglu, I. A Computation and Power Reduction Technique for H.264 Intra Prediction. In Proceedings of the 13th Euromicro Conference on Digital System Design on Architectures, Methods and Tools, Lille, France, 1–3 September 2010. doi:10.1109/DSD.2010.115. 1129. Senthilkumar, G.; Hariprasath, S. A Low Power Architecture for H.264 Encoder in Intra Prediction Mode. In Proceedings of the 3rd International Conference on Communications and Signal Processing (ICCSP), Melmaruvathur, India, 3–5 April 2014. 1130. Nagaraju, S.; Reddy, P.S. Low Power Pattern Matching Scheme through FSM State Transition for Next Generation NIDS System. In Proceedings of the 2nd IEEE International Conference on Electrical, Computer and Communication Technologies (IEEE ICECCT), SVS Coll Engn, Coimbatore, India, 22–24 February 2017. 1131. Sweety.; Pandey, B.; Kumar, T.; Das, T. Design of Power Optimized Memory Circuit Using High Speed Transreceiver Logic IO Standard on 28nm Field Programmable Gate Array. In Proceedings of the International Conference on Optimization, Reliabilty, and Information Technology (ICROIT), Faridabad, India, 6–8 February 2014. 1132. Agrawal, T.; Kumar, A.; Saraswat, S.K. Design of Low Power SRAM on Artix-7 FPGA. In Proceedings of the 2nd International Conference on Communication Control and Intelligent Systems (CCIS), Mathura, India, 18–20 November 2016. 1133. Sweety.; Dhankar, M.; Kajal, R.; Kalia, K.; Vashishta, K.; Kumar, A. Energy efficient memory design using low voltage complementary metal oxide semiconductor on 28nm FPGA. Indian J. Sci. Technol. 2015, 8. doi:10.17485/ijst/2015/v8i17/76237. 1134. Jamal, H.; Farhan, S.M.; Khan, S.A. Low power area efficient high data rate 16bit AES crypto processor. In Proceedings of the 18th International Conference on Microelectronics (ICM 2006), King Fahd Univ Petr & Minerals, Dhahran, Saudi Arabia, 16–18 December 2006. 1135. Dalmisli, K.V.; Ors, B. Design of new tiny circuits for aes encryption algorithm. In Proceedings of the 3rd International Conference on Signals, Circuits and Systems, Medenine, Tunisia, 6–8 November 2009. 1136. Li, Y.; Zhang, X.; Jiang, A. Design of AES coprocessor used on the node of wireless sensor network. Beijing Daxue Xuebao (Ziran Kexue Ban)/Acta Sci. Nat. Univ. Pekin. 2009, 45, 426–430. 1137. Van, D.J.; Delgado-Frias, J.; Medidi, S. FPGA schemes with optimized routing for the advanced encryption standard. In Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008, Las Vegas, NV, USA, 14–17 July 2008. 1138. Dargie, W.; Poellabauer, C. Fundamentals of Wireless Sensor Networks: Theory and Practice; Wireless Communications and Mobile Computing; Wiley: Hoboken, NJ, USA, 2010. Computation 2019, xx, 5 86 of 115 1139. Moh’d, A.; Marzi, H.; Aslam, N.; Phillips, W.; Robertson, W. A secure platform of wireless sensor networks. In Proceedings of the 2nd International Conference on Ambient Systems, Networks and Technologies, ANT-2011 and 8th International Conference on Mobile Web Information Systems, MobiWIS 2011, Niagara Falls, ON, Canada, 19–21 September 2011. doi:10.1016/j.procs.2011.07.017. 1140. Houssain, H.; Badra, M.; Al-Somani, T. Hardware implementations of elliptic curve cryptography in wireless sensor networks. In Proceedings of the 2011 International Conference for Internet Technology and Secured Transactions, ICITST 2011, Abu Dhabi, United Arab Emirates, 11–14 December 2011. 1141. Al-Somani, T.; Houssain, H. Implementation of GF(2 m) elliptic curve cryptoprocessor on a nano FPGA. In Proceedings of the 2011 International Conference for Internet Technology and Secured Transactions, ICITST 2011, Abu Dhabi, United Arab Emirates, 11–14 December 2011. 1142. Leelavathi, G.; Shaila, K.; Venugopal, K.R. Elliptic Curve Cryptography Implementation on FPGA using Montgomery Multiplication for Equal Key and Data size over GF(2(m)) for Wireless Sensor Networks. In Proceedings of the IEEE Region 10 Conference (TENCON), Singapore, Singapore 22–25 November 2016. 1143. Leelavathi, G.; Shaila, K.; Venugopal, K.R. Implementation of Public Key Crypto Processor with Probabilistic Encryption on FPGA for Nodes in Wireless Sensor Networks. In Proceedings of the 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), IISC, Bengaluru, India, 10–12 July 2018. 1144. Parrilla, L.; Castillo, E.; Lopez-Ramos, J.A.; Alvarez-Bermejo, J.A.; Garcia, A.; Morales, D.P. Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks. Sensors 2018, 18. doi:10.3390/s18010251. 1145. Pham, D.M.; Aziz, S.M. Object extraction scheme and protocol for energy efficient image communication over wireless sensor networks. Comput. Netw. 2013, 57, 2949–2960. doi:10.1016/j.comnet.2013.07.001. 1146. Engel, A.; Liebig, B.; Koch, A. Energy-efficient heterogeneous reconfigurable sensor node for distributed structural health monitoring. In Proceedings of the 6th Annual Conference on Design and Architectures for Signal and Image Processing, DASIP 2012, Karlsruhe, Germany, 23–25 October 2012. 1147. Li, Y.; Jia, Z.; Xie, S.; Liu, F. An hw reconfigurable node with novel scheduling in an energy-harvesting environment. Int. J. Innov. Comput. Inf. Control 2013, 9, 1715–1725. 1148. Chen, C.H.; Lin, M.Y.; Lin, W.H. Designing and Implementing a Lightweight WSN MAC Protocol for Smart Home Networking Applications. J. Circuits Syst. Comput. 2017, 26. doi:10.1142/S0218126617500438. 1149. Chaudhary, A.; Rusia, J.; Gourav, K.; Tripathi, P.; Pandey, J.; Majumdar, S.; Naugarhiya, A.; Acharya, B.; Majumder, S.; Verma, S. Design and Simulation of Physical Layer Blocks of ZigBee Transmitter. In Proceedings of the International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC), Palladam, India, 10–11 February 2017. 1150. Rodriguez-Araujo, J.; Rodriguez-Andina, J.J.; Farina, J.; Chow, M.Y. Field-Programmable System-on-Chip for Localization of UGVs in an Indoor iSpace. IEEE Trans. Ind. Informatics 2014, 10, 1033–1043. doi:10.1109/TII.2013.2294112. 1151. Brenot, F.; Piat, J.; Fillatreau, P. FPGA based hardware acceleration of a BRIEF correlator module for a monocular SLAM application. In Proceedings of the 10th International Conference on Distributed Smart Cameras, ICDSC 2016, Vienna, Austria, 12–15 September 2016. doi:10.1145/2967413.2967426. 1152. Lee, W.Y.; Bo-Jhih, C.; Wu, C.T.; Shih, C.L.; Tsai, Y.H.; Fan, Y.C.; Lee, C.Y.; Chen, T.H. Implementation of an FPGA-Based Vision Localization. In Proceedings of the 9th International Conference on Genetic and Evolutionary Computing (ICGEC), Univ Comp Studies, Yangon, Myanmar, 26–28 August 2015. doi:10.1007/978-3-319-23207-2_23. 1153. Hu, C.; Xiong, X.; Ren, W.; He, D. Localization and navigation for indoor mobile robot on embedded system. Huazhong Keji Daxue Xuebao (Ziran Kexue Ban)/J. Huazhong Univ. Sci. Technol. (Nat. Sci. Ed. 2013, 41, 254–257. 1154. Sacchetin, M.C.; Lopes, J.J.; Wolf, D.F.; Silva, J.L.; Marques, E. Analysis and implementation of localization and mapping algorithms for mobile robots based on reconfigurable computing. Lat. Am. Appl. Res. 2007, 37, 31–34. 1155. Segura, M.; Hashemi, H.; Sisterna, C.; Mut, V. Experimental Demonstration of Self-Localized Ultra Wideband Indoor Mobile Robot Navigation System. In Proceedings of the International Conference on Indoor Positioning and Indoor Navigation (IPIN), Zurich, Switzerland, 15–17 September 2010. Computation 2019, xx, 5 87 of 115 1156. Segura, M.; Sisterna, C.; Guzzo, M.; Ensinck, G.; Gil, C. Ultra wideband digital receiver implemented on FPGA for mobile robot indoor self-localization. In Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011, Cordoba, Spain, 13–15 April 2011. doi:10.1109/SPL.2011.5782632. 1157. Girau, B.; Boumaza, A. Embedded harmonic control for dynamic trajectory planning on FPGA. In Proceedings of the IASTED International Conference on Artificial Intelligence and Applications, Innsbruck, Austria, 12–14 February 2007. 1158. Schmidt, M.; Fey, D. An optimized FPGA implementation for a parallel path planning algorithm based on Marching Pixels. In Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2010, Cancun, Mexico, 13–15 December 2010. doi:10.1109/ReConFig.2010.18. 1159. Sridharan, K.; Priya, T.; Kumar, P. Architecturally-efficient computation of shortest paths for a mobile robot. In Proceedings of the 2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009, Kuala Lumpur, Malaysia, 4–6 October 2009. doi:10.1109/ISIEA.2009.5356447. 1160. Nada, A.; Bashiri, A. Integration of multibody system dynamics with sliding mode control using FPGA technique for trajectory tracking problems. In Proceedings of the ASME 2018 Dynamic Systems and Control Conference, DSCC 2018, Hyatt Regency Atlanta, GA, USA, 30 September–3 October 2018. doi:10.1115/DSCC2018-9108. 1161. Koziol, S.; Brink, S.; Hasler, J. A Neuromorphic Approach to Path Planning Using a Reconfigurable Neuron Array IC. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2014, 22, 2724–2737. doi:10.1109/TVLSI.2013.2297056. 1162. Sudha, N.; Mohan, A.R. Design of a hardware accelerator for path planning on the Euclidean distance transform. J. Syst. Archit. 2008, 54, 253–264. doi:10.1016/j.sysarc.2007.06.003. 1163. Koziol, S.; Wunderlich, R.; Hasler, J.; Stilman, M. Single-Objective Path Planning for Autonomous Robots Using Reconfigurable Analog VLSI. IEEE Trans. Syst. Man-Cybern.-Syst. 2017, 47, 1301–1314. doi:10.1109/TSMC.2016.2573833. 1164. De, L.F.M.; Echanobe, J.; Del, C.I.; Susperregui, L.; Maurtua, I. Development of an embedded system for visual servoing in an industrial scenario. In Proceedings of the 5th International Symposium on Industrial Embedded Systems, SIES 2010, Trento, Italy, 7–9 July 2010. doi:10.1109/SIES.2010.5551391. 1165. Wang, F.; Huang, D.; Sheng, G. A pipelined reconfigurable architecture for real-time image processing of robot vision servoing. In Proceedings of the IEEE International Conference on Mechatronics and Automation, Harbin, China, 5–8 August 2007. doi:10.1109/ICMA.2007.4303905. 1166. Dhipa, M.; Jeyakkannan, N.; Chandrasekar, A. Hardware accelerated stereo imaging for visual servoing. In Proceedings of the Proceedings of Online International Conference on Green Engineering and Technologies (IC-GET), Coimbatore, India, 27 November 2015. 1167. Perez, J.; Alabdo, A.; Pomares, J.; Garcia, G.J.; Torres, F. FPGA-based visual control system using dynamic perceptibility. Robot.-Comput.-Integr. Manuf. 2016, 41, 13–22. doi:10.1016/j.rcim.2016.02.005. 1168. Lyu, C.; Chen, H.; Jiang, X.; Li, P.; Liu, Y. Real-time object tracking system based on field-programmable gate array and convolution neural network. Int. J. Adv. Robot. Syst. 2017, 14. doi:10.1177/1729881416682705. 1169. Haenssler, O.C.; Wieghaus, M.F.; Kostopoulos, A.; Doundoulakis, G.; Aperathitis, E.; Fatikow, S.; Kiriakidis, G. Multimodal microscopy test standard for scanning microwave, electron, force and optical microscopy. J.-Micro-Bio Robot. 2018, 14, 51–57. doi:10.1007/s12213-018-0108-z. 1170. Bin Azhar, M.; Dimond, K. Design of an FPGA based adaptive neural controller for intelligent robot navigation. In Proceedings of the Joint Meeting of the 28th EUROMICRO Conference/EUROMICRO Symposium on Digital System Design, Dortmund, Germany, 4–6 September 2002. doi:10.1109/DSD.2002.1115380. 1171. Chinnaaiah, M.C.; Dubey, S.; Anusha, K.; Kumar, P.R.; Savithri, T.S. A Versatile Autonomous Navigation Algorithm for Smart Indoor Environment using FPGA based Robot. In Proceedings of the International Conference on Intelligent Computing, Instrumentation and Control Technologies (ICICICT), Kannur, India, 6–7 July 2017. 1172. Baquero, V.A.; Borrero, G.H.; Pedraza, I.; Magalhaes, D.; Becker, M.; De, P.C.G. Navigation control in FPGA for a differential-drive mobile robot. In Proceedings of the 2013 16th International Conference on Advanced Robotics, ICAR 2013, Montevideo, Uruguay, 25–29 November 2013. doi:10.1109/ICAR.2013.6766532. Computation 2019, xx, 5 88 of 115 1173. Chinnaiah, M.; Savitri, T.; Kumar, P. Novel approach in navigation of FPGA robots in robust indoor environment. In Proceedings of the International Conference on Advanced Robotics and Intelligent Systems, ARIS 2015, Taipei, Taiwan, 29– 31 May 2015. doi:10.1109/ARIS.2015.7158382. 1174. Georgoulas, C.; Andreadis, I. FPGA based disparity map computation with vergence control. Microprocess. Microsyst. 2010, 34, 259–273. doi:10.1016/j.micpro.2010.05.003. 1175. Buder, M. Dense realtime stereo matching using a memory efficient Semi-Global-Matching variant based on FPGAs. In Proceedings of the Conference on Real-Time Image and Video Processing, Brussels, Belgium, 19 April 2012. doi:10.1117/12.921147. 1176. Gudis, E.; van der Wal, G.; Kuthirummal, S.; Chai, S. Multi-Resolution Real-Time Dense Stereo Vision Processing in FPGA. In Proceedings of the 20th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Toronto, Canada, 29 April–1 May 2012. doi:10.1109/FCCM.2012.15. 1177. Ambrosch, K.; Humenberger, M.; Kubinger, W. A novel hardware architecture for an embedded stereo vision sensor. In Proceedings of the 18th International Symposium of the Danube-Adria-Association-for-Automation-and-Manufacturing, Zadar, Croatia, 24–27 October 2007. 1178. Sanjay, D.; Savithri, T.S.; Kumar, P.R. Person follower Robotic System. In Proceedings of the International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), Kanyakumari, India, 10–11 July 2014. 1179. Sanjay, D.; Kumar, P.R.; Savithri, T.S. Robotic system using Fuzzy logic for Person following. In Proceedings of the International Conference on Electrical, Electronics, Signals, Communication and Optimization (EESCO), Vignans Inst of Information Technology, Visakhapatnam, India, 24–25 January 2015. 1180. Tian, Q.; He, X. Real-time vision system for tracking object with DSP and FPGA architecture. Jisuanji Gongcheng/Comput. Eng. 2005, 31, 219–221. 1181. Vachhani, L.; Sridharan, K. Hardware-efficient prediction-correction-based generalized-Voronoi-diagram construction and FPGA implementation. IEEE Trans. Ind. Electron. 2008, 55, 1558–1569. doi:10.1109/TIE.2008.917161. 1182. Kumar, P.R.; Sridharan, K. VLSI-efficient scheme and FPGA realization for robotic mapping in a dynamic environment. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2007, 15, 118–123. doi:10.1109/TVLSI.2007.891100. 1183. Sudharsan, V.; Sridharan, K. Hardware-efficient path planning for a mobile robot and FPGA realization. In Proceedings of the 2012 IEEE 7th International Conference on Industrial and Information Systems, ICIIS 2012, Chennai, India, 6–9 August 2012. doi:10.1109/ICIInfS.2012.6304788. 1184. Sridharan, K.; Kumar, P.R.; Sudha, N.; Vachhani, L. A Novel CAM-Based Robotic Indoor Exploration Algorithm and Its Area-Efficient Implementation. In Proceedings of the 34th Annual Conference of the IEEE-Industrial-Electronics-Society, Orlando, FL, USA, 10–13 November 2008. 1185. Vachhani, L.; Sridharan, K. Hardware-efficient architecture for generalized Voronoi diagram construction using a prediction-correction approach. In Proceedings of the 15th International Conference on Advanced Computing and Communications, Indian Inst Technol Guwahati, Guwahati, India, 18–21 December 2007. doi:10.1109/ADCOM.2007.42. 1186. Ohkawa, T.; Yamashina, K.; Matsumoto, T.; Ootsu, K.; Yokota, T. Architecture Exploration of Intelligent Robot System using ROS-compliant FPGA Component. In Proceedings of the 27th International Symposium on Rapid System Prototyping (RSP) - Shortening the Path from Specification to Prototype, Pittsburgh, PA, USA, 6–7 October 2016. doi:10.1145/2990299.2990312. 1187. Yamashina, K.; Kimura, H.; Ohkawa, T.; Ootsu, K.; Yokota, T. cReComp : Automated Design Tool for ROS-Compliant FPGA Component. In Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC), Lyon, France, 21–23 September 2016. doi:10.1109/MCSoC.2016.47. 1188. Sugata, Y.; Ootsu, K.; Ohkawa, T.; Yokota, T. Acceleration of Publish/Subscribe Messaging in ROS-compliant FPGA Component. In Proceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017, Bochum, Germany, 7 –9 June 2017. doi:10.1145/3120895.3120904. 1189. Ohkawa, T.; Yamashina, K.; Kimura, H.; Ootsu, K.; Yokota, T. FPGA Components for Integrating FPGAs into Robot Systems. IEICE Trans. Inf. Syst. 2018, E101D, 363–375. doi:10.1587/transinf.2017RCP0011. 1190. Mysorewala, M.; Cheded, L. A project-based strategy for teaching robotics using NI’s embedded-FPGA platform. Int. J. Electr. Eng. Educ. 2013, 50, 139–156. doi:10.7227/IJEEE.50.2.4. Computation 2019, xx, 5 89 of 115 1191. Plaza, P.; Sancristobal, E.; Fernandez, G.; Castro, M.; Perez, C. Collaborative Robotic Educational Tool based on Programmable Logic and Arduino. In Proceedings of the Conference on Technologies Applied to Electronics Teaching (TAEE), Univ Sevilla, Sevilla, Spain, 22–24 June 2016. 1192. Plaza Merino, P.; Sancristobal Ruiz, E.; Carro Fernandez, G.; Castro Gil, M. Robotic Educational Tool to engage students on Engineering. In Proceedings of the IEEE Frontiers in Education Conference (FIE), Gannon Univ, Erie, PA, USA, 12–15 October 2016. 1193. Schwiegelshohn, F.; Kaestner, F.; Huebner, M. FPGA Design of Numerical Methods for the Robotic Motion Control Task exploiting High-Level Synthesis. In Proceedings of the IEEE International Conference on the Science of Electrical Engineering (ICSEE), Eilat, Israel, 16–18 November 2016. 1194. Lee, W.y.; Guo, J.S.; Chen, C.P. Motion Control Components’ Algorithms on a Chip for driving module. In Proceedings of the 8th International Conference on Power Electronics and Drive Systems (PEDS), Taipei, Taiwan, 2–5 November 2009. 1195. Jingwen, T.; Meijuan, G.; Jin, L.; Kai, L. A robot motion control system based on ARM. In Proceedings of the 26th Chinese Control Conference, Zhangjiajie, China, 26–31 July 2007. 1196. Parmar, Y.; Sridharan, K. Precomputation-based radix-4 CORDIC for approximate rotations and Hough transform. IET Circuits Devices Syst. 2018, 12, 413–423. doi:10.1049/iet-cds.2017.0492. 1197. Juang, Y.S.; Sung, T.Y.; Ko, L.T.; Li, C.L. FPGA Implementation of a CORDIC-Based Joint Angle Processor for a Climbing Robot. Int. J. Adv. Robot. Syst. 2013, 10. doi:10.5772/53377. 1198. Mahyuddin, M.N.; Wei, C.Z.; Arshad, M.R. Neuro-Fuzzy Algorithm implemented in Altera’s FPGA for Mobile Robot’s Obstacle Avoidance Mission. In Proceedings of the IEEE Region 10 Conference 2009, Singapore, Singapore, 23–26 November 2009. 1199. Mysorewala, M.; Alshehri, K.; Alkhayat, E.; Al-Ghusain, A.; Al-Yagoub, O. Design and Implementation of Fuzzy-Logic based Obstacle-Avoidance and Target-Reaching Algorithms on NI’s Embedded-FPGA Robotic Platform. In Proceedings of the 3rd IEEE Symposium on Computational Intelligence in Control and Automation (CICA), Singapore, Singapore, April 16–19 April 2013. 1200. Perez-D’Arpino, C.; Medina-Melendez, W.; Ralev, D.; Guzman, J.; Fermin, L.; Carlos Grieco, J.; Fernandez-Lopez, G.; Armada, M. FPGA-based artificial vision system for robot and obstacles detection under strong luminosity variability. In Proceedings of the 12th International Conference on Climbing and Walking Robots the Support Technologies for Mobile Machines (CLAWAR), Istanbul, Turkey, 9–11 September 2009. doi:10.1142/9789814291279_0134. 1201. Siswoyo, B.; Choiron, M.A.; Irawan, Y.S.; Wardana, I.N.G. System Architecture and FPGA Embedding of Compact Fuzzy Logic Controller for Arm Robot Joints. In Proceedings of the International Conference on Mechanical Engineering (ICOME 2013), Mataram, Indonesia, 19–21 September 2013. doi:10.4028/www.scientific.net/AMM.493.480. 1202. Siswoyo, B.; Choiron, M.A.; Wardana, I.N.G.; Irawan, Y.S. Architectural System Design of Six Channels Compact Fuzzy Logic Controller for Arm Robot Joints Using FPGA Technology. In Proceedings of the 5th International Conference on Mechanical, Industrial, and Manufacturing Technologies (MIMT), Penang, Malaysia, 10–11 March 2014. doi:10.4028/www.scientific.net/AMM.541-542.1127. 1203. Werner, F.; Sitte, J.; Maire, F. Visual Topological Mapping and Localisation using Colour Histograms. In Proceedings of the 10th International Conference on Control, Automation, Robotics and Vision, Hanoi, Vietnam, 17–20 December 2008. doi:10.1109/ICARCV.2008.4795543. 1204. Jeppesen, B.P.; Roy, N.; Moro, L.; Baronti, F. An FPGA-based controller for collaborative robotics. In Proceedings of the 26th IEEE International Symposium on Industrial Electronics (ISIE), Edinburgh, UK, 18-21 June 2017. 1205. Cuperlier, N.; Guedjou, H.; De, M.F.; Miramond, B. Attention-based smart-camera for spatial cognition. In Proceedings of the 10th International Conference on Distributed Smart Cameras, ICDSC 2016, Paris, France, 12–15 September 2016. doi:10.1145/2967413.2967440. 1206. Nandayapa, M.; Mitsantisuk, C.; Ohishi, K. High performance velocity estimation for controllers with short processing time by FPGA. IEEJ J. Ind. Appl. 2012, 1, 55–61. doi:10.1541/ieejjia.1.55. 1207. Anderson, J.; Najm, F. Active leakage power optimization for FPGAs. IEEE Trans.-Comput.-Aided Des. Integr. Circuits Syst. 2006, 25, 423–437. doi:10.1109/TCAD.2005.853692. 1208. Sundar, P.B.M.; Vijayan, S. Power optimization In FPGA routing circuits. Life Sci. J. 2013, 10, 2431–2437. Computation 2019, xx, 5 90 of 115 1209. Sandoval, C. POWER CONSUMPTION OPTIMIZATION IN REED SOLOMON ENCODERS OVER FPGA. Lat. Am. Appl. Res. 2014, 44, 81–81. 1210. Pan, Y.; Ge, N.; Dong, Z. CRC Look-up Table Optimization for Single-Bit Error Correction. Tsinghua Sci. Technol. 2007, 12, 620–623. doi:10.1016/S1007-0214(07)70142-6. 1211. Prihozhy, A.; Bezati, E.; Ab Rahman, A.A.H.; Mattavelli, M. Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs. IEEE Trans.-Comput.-Aided Des. Integr. Circuits Syst. 2015, 34, 1613–1626. doi:10.1109/TCAD.2015.2427278. 1212. Guo, Q.; Wang, C.; Feng, X.; Zhou, X. Automatic Loop-based Pipeline Optimization on Reconfigurable Platform. In Proceedings of the 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom), Melbourne, Australia, 16–18 July 2013. doi:10.1109/TrustCom.2013.112. 1213. Rathod, A.; Thakker, R.A. FPGA Realization of Particle Swarm Optimization Algorithm using Floating Point Arithmetic. In Proceedings of the International Conference on High Performance Computing and Applications (ICHPCA), BHUBANESWAR, India, 22–24 December 2014. 1214. Kurek, M.; Becker, T.; Luk, W. Parametric Optimization of Reconfigurable Designs Using Machine Learning. In Proceedings of the 9th International Applied Reconfigurable Computing Symposium (ARC), Los Angeles, CA, USA, 25–27 March 2013. 1215. Yamada, T.; Maeda, Y.; Miyoshi, S.; Hikawa, H. Simultaneous perturbation particle swarm optimization and FPGA realization. In Proceedings of the SICE Annual Conference 2010, Taipei, Taiwan, 18–21 August 2010. 1216. Ma, Y.; Xia, L.; Lin, J.; Jing, J.; Liu, Z.; Yu, X. Hardware performance optimization and evaluation of SM3 hash algorithm on FPGA. In Proceedings of the 14th International Conference on Information and Communications Security, ICICS 2012, Hong Kong, China, 29–31 October 2012. doi:10.1007/978-3-642-34129-8_10. 1217. Fu, X.; Xiao, M.; Yuan, D.; Zou, D. Colored Petri-net based approach for modeling and optimization of FIFO stack. Yi Qi Yi Biao Xue Bao/Chin. J. Sci. Instrum. 2008, 29, 577–582. 1218. Kumm, M.; Hardieck, M.; Zipf, P. Optimization of Constant Matrix Multiplication with Low Power and High Throughput. IEEE Trans. Comput. 2017, 66, 2072–2080. doi:10.1109/TC.2017.2701365. 1219. Bhiwapurkar, N.; Mohan, N. Torque ripple optimization in switched reluctance motor using two-phase model and optimization search technique. In Proceedings of the International Symposium on Power Electronics, Electrical Drives, Automation and Motion, Taormina, Italy, 23–26 May 2006. doi:10.1109/SPEEDAM.2006.1649795. 1220. Blaho, J.; Korenek, J.; Pus, V. Memory optimization for packet classification algorithms. In Proceedings of the 2009 Symposium on Architecture for Networking and Communications Systems, ANCS’09, Princeton, NJ, USA, 19–20 October 2009. doi:10.1145/1882486.1882524. 1221. Cowdrey, K.W.G.; de lange, J.; Malekian, R.; Wanneburg, J.; Jose, A.C. Applying Queueing Theory for the Optimization of a Banking Model. J. Internet Technol. 2018, 19, 381–389. doi:10.3966/160792642018031902007. 1222. Caroff, T.; Sarno, C.; Hodot, R.; Brignone, M.; Simon, J. New optimization strategy of thermoelectric coolers applied to automotive and avionic applications. In Proceedings of the 12th European Conference on Thermoelectricity (ECT), Madrid, Spain, 24–26 September 2014. doi:10.1016/j.matpr.2015.05.095. 1223. Giordano, F.; Fox, W.; Horton, S.; Weir, M. A First Course in Mathematical Modeling; Cengage Learning: Boston, MA, USA, 2008. 1224. Cirstea, M.N.; Dinu, A. A VHDL holistic modeling approach and FPGA implementation of a digital sensorless induction motor control scheme. IEEE Trans. Ind. Electron. 2007, 54, 1853–1864. doi:10.1109/TIE.2007.898286. 1225. Tisan, A.; Cirstea, M.; Buchman, A.; Parera, A.; Oniga, S.; Ilea, D. Holistic Modeling, Design and Optimal Digital Control of a Combined Renewable Power System. In Proceedings of the IEEE International Symposium on Industrial Electronics (ISIE), Bari, Italy, 4–7 July 2010. 1226. Petrinec, K.; Cirstea, M.; Seare, K.; Marinescu, C. A novel FPGA fuel cell system controller design. In Proceedings of the 11th International Conference on Optimization of Electrical and Electronic Equipment, Brasov, Romania, 22–23 May 2008. 1227. Cirstea, M.; Parera-Ruiz, A. An FPGA Controller for a Combined Solar/Wind Power System. In Proceedings of the 12th International Conference on Optimization of Electrical and Electronic Equipment, Brasov,Romania, 20–21 May 2010. doi:10.1109/OPTIM.2010.5510437. Computation 2019, xx, 5 91 of 115 1228. Chen, C.H.; Chang, W.H.; Chen, D.; Tai, L.P.; Wang, C.C. Modeling of digitally-controlled voltage-mode DC-DC converters. In Proceedings of the 33rd Annual Conference of the IEEE-Industrial-Electronics-Society, Taipei, Taiwan, 5–8 November 2007. doi:10.1109/IECON.2007.4460043. 1229. Huang, Z.; Dinavahi, V. A Fast and Stable Method for Modeling Generalized Nonlinearities in Power Electronic Circuit Simulation and its Real-Time Implementation. IEEE Trans. Power Electron. 2018. doi:10.1109/TPEL.2018.2851570. 1230. Lopez-Colino, F.; Sanchez, A.; De, C.A.; Garrido, J. Modeling of power converters for debugging digital controllers through FPGA emulation. In Proceedings of the 2013 15th European Conference on Power Electronics and Applications, EPE 2013, Lille, France, 2–6 September 2013. doi:10.1109/EPE.2013.6631870. 1231. Ntoune, R.S.N.; Bahoura, M.; Park, C.W. FPGA-Implementation of Pipelined Neural Network for Power Amplifier Modeling. In Proceedings of the 10th IEEE International New Circuits and Systems Conference (NEWCAS), Montreal, QC, Canada, 17–20 June 2012. 1232. Tornello, L.D.; Scelba, G.; Cacciato, M.; Scarcella, G.; Palmieri, A.; Vanelli, E.; Pernaci, C.; Di Dio, R. FPGA-Based Real-Time Models of IGBT Power Converters. In Proceedings of the International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM), Amalfi, Italy, 20–22 June 2018. 1233. Papamichael, M.; Hoe, J.; Mutlu, O. FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations. In Proceedings of the 5th ACM/IEEE International Symposium on Networks-on-Chip, NOCS 2011, Pittsburgh, PA, USA,1–4 May 2011. doi:10.1145/1999946.1999969. 1234. Ost, L.; Almeida, G.; Mandelli, M.; Wachter, E.; Varyani, S.; Sassatelli, G.; Indrusiak, L.; Robert, M.; Moraes, F. Exploring heterogeneous NoC-based MPSoCs: From FPGA to high-level modeling. In Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2011 - Proceedings, Montpellier, France, 20–22 June 2011. doi:10.1109/ReCoSoC.2011.5981517. 1235. Zhang, C.; Li, L. Characterization and Design of Through-Silicon Via Arrays in Three-Dimensional ICs Based on Thermomechanical Modeling. IEEE Trans. Electron Devices 2011, 58, 279–287. doi:10.1109/TED.2010.2089987. 1236. Jin, J.; Song, N.; Li, L. Temperature drift modeling and real-time compensation of interferometric fiber optic gyroscope. Hangkong Xuebao/Acta Aeronaut. Et Astronaut. Sin. 2007, 28, 1449–1454. 1237. Dobinson, R.; Haas, S.; Korcyl, K.; LeVine, M.; Lokier, J.; Martin, B.; Meirosu, C.; Saka, F.; Vella, K. Testing and modeling Ethernet switches and networks for use in ATLAS high-level triggers. IEEE Trans. Nucl. Sci. 2001, 48, 607–612. doi:10.1109/23.940127. 1238. Wang, S.; Zhao, H.; Huang, S.; Hafid, A. Modeling FPGA-based IEEE 802.11 DCF. In Proceedings of the 2011 7th International Conference on Mobile Ad-hoc and Sensor Networks, MSN 2011, Beijing, China, 16–18 December 2011. doi:10.1109/MSN.2011.49. 1239. Arifin, S.; Cheung, P.Y.K. User attention based arousal content modeling; IEEE: 2, 2006; pp. 433–+. In Proceedings of the IEEE International Conference on Image Processing (ICIP 2006), Atlanta, GA, USA, 8–11 October 2006. doi:10.1109/ICIP.2006.312450. 1240. Mellit, A. Artificial intelligence technique for modelling and forecasting of meteorological data: A survey. Atmos. Turbul. Meteorol. Model. Aerodyn. 2010, pp. 293–327. 1241. Ciobanu, L.; Thirer, N. MODELING VECHICLES AND MOBILE ROBOTS. In Proceedings of the 47th AIAA Aerospace Sciences Meeting and Exhibit Including the New Horizons Forum and Aerospace Exposition, Orlando, FL, USA, 5–8 January 2009. doi:10.1109/EEEI.2008.4736697. 1242. Mie, S.; Okuyama, Y.; Saito, H. Simplified quadcopter simulation model for spike-based hardware PID controller using SystemC-AMS. In Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2018, Hanoi, Vietnam, 12–14 September 2018. doi:10.1109/MCSoC2018.2018.00016. 1243. Parera-Ruiz, A.; Cirstea, M.N.; Cirstea, S.E.; Dinu, A. Integrated Renewable Energy System Modelling with direct FPGA Controller Prototyping. In Proceedings of the 35th Annual Conference of the IEEE-Industrial-Electronics-Society, Porto, Portugal, 3–5 November 2009. 1244. Tekale, P.S.; Ayyagari, R.; Sudarsan, S.D.; Jetley, R.; Ramaswamy, S. Modeling and Analysis of FPGA based Power Management System for Renewables. In Proceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), Limassol, Cyprus, 12–15 September 2017. 1245. Nunez-Perez, J.C.; Sillas-Luna, J.A.; Cardenas Valdez, J.R.; Galaviz-Aguilar, J.A.; Tlelo Cuautle, E.; Vazquez-Lopez, C.E.; Trujillo-Reyes, L. FPGA Realization of RF-PA Models with Memory Effects based on Computation 2019, xx, 5 92 of 115 ANFIS. In Proceedings of the IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC), Ixtapa, Mexico, 9–11 November 2016. 1246. Salomon, D. Data Compression: The Complete Reference; Springer New York, 2006. 1247. Fowers, J.; Kim, J.Y.; Burger, D.; Hauck, S. A Scalable High-Bandwidth Architecture for Lossless Compression on FPGAs. In Proceedings of the 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Vancouver, Canada, 3–5 May 2015. doi:10.1109/FCCM.2015.46. 1248. Abd, E.G.M.; Salama, A.; Khalil, A. Design and implementation of FPGA- Based systolic array for LZ data compression. In Proceedings of the 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, LA, USA, 27–30 May 2007. 1249. Kim, J.Y.; Hauck, S.; Burger, D. A Scalable Multi-Engine Xpress9 Compressor with Asynchronous Data Transfer. In Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines ((FCCM), Boston, MA, USA, 11–13 May 2014. doi:10.1109/FCCM.2014.49. 1250. Gao, Y.; Ye, H.; Wang, J.; Lai, J. FPGA Bitstream Compression and Decompression based on LZ77 Algorithm and BMC Technique. In Proceedings of the 11th IEEE International Conference on ASIC (ASICON), Chengdu, China, 3–6 November 2015. 1251. Szecowka, P.M.; Mandrysz, T. Towards Hardware Implementation of bzip2 Data Compression Algorithm; IEEE: 4, 2009; pp. 337–340. In Proceedings of the 16th International Conference Mixed Design of Integrated Circuits and Systems, Lodz, Poland, 25–27 June 2009. 1252. Hernandez, M.; Alvarado-Nava, O.; Martinez, F. Huffman coding-based compression unit for embedded systems. In Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2010, Cancun, Mexico, 13–15 December 2010. doi:10.1109/ReConFig.2010.65. 1253. Soto Hernandez, M.A.; Alvarado-Nava, O.; Rodriguez-Martinez, E.; Zaragoza Martinez, F.J. Tree-less Huffman Coding Algorithm for Embedded Systems. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 9–11 December 2013. 1254. Zhang, J.; Pei, D.; Zhu, J. A hardware architecture of the real-time and lossless data compression based on LZW algorithm. In Proceedings of the 6th International Symposium on Test and Measurement (ISTM), Dalian, China, 1–4 June 2005. 1255. Wang, K.y.; Yao, Y.x.; Zhou, L. Research on Compiled-type Numerical Control System and Its Data Compression Technology. In Proceedings of the 3rd International Conference on Machine Design and Manufacturing Engineering (ICMDME), Jeju Island, Korea, 24–25 May 2014. doi:10.4028/www.scientific.net/AMM.607.768. 1256. Li, J.; Mao, H.; Zhang, W.; Lin, J.; Ma, Y. Research on realization of real-time and lossless hardware compression algorithm. In Proceedings of the 6th International Symposium on Test and Measurement (ISTM), Dalian, China, 1–4 June 2005. 1257. Kostarelos, F.; Charitopoulos, G.; Pnevmatikatos, D.N. Less is More: Increasing the Scope of Hardware Debugging with Compression. In Proceedings of the 4th Panhellenic Conference on Electronics and Telecommunications (PACET), Democritus Univ, Thrace Dept Elect & Comp Engn, Xanthi, Greece, 17–18 November 2017. 1258. Lee, S.M.; Jang, J.H.; Oh, J.H.; Kim, J.K.; Lee, S.E. Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression. IEICE Electron. Express 2017, 14. doi:10.1587/elex.14.20170399. 1259. Kobayashi, R.; Kise, K. A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism. IEICE Trans. Inf. Syst. 2017, E100D, 1003–1015. doi:10.1587/transinf.2016EDP7383. 1260. Jang, J.H.; Lee, S.M.; Gwon, O.S.; Lee, S.E. An FPGA Based Compression Accelerator for Forex Trading System. In Proceedings of the 13th International Conference on Information Technology - New Generations (ITNG), Las Vegas, NV, USA, 11–13 April 2016. doi:10.1007/978-3-319-32467-8_62. 1261. Lee, S.M.; Oh, J.H.; Jang, J.H.; Lee, S.M.; Kim, J.K.; Lee, S.E. Live Demonstration: An FPGA based Hardware Compression Accelerator for Hadoop System. In Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, Korea, 25–28 October 2016. 1262. Ruiz-Rosero, J.; Ramirez-Gonzalez, G.; Williams, J.M.; Liu, H.; Khanna, R.; Pisharody, G. Internet of Things: A Scientometric Review. Symmetry 2017, 9. doi:10.3390/sym9120301. 1263. Szymanski, T. Security and Privacy for a Green Internet of Things. IT Prof. 2017, 19, 34–41. doi:10.1109/MITP.2017.3680952. Computation 2019, xx, 5 93 of 115 1264. Tsague, H.D.; Twala, B. Practical Techniques for Securing the Internet of Things (IoT) Against Side Channel Attacks. Internet Things Big Data Anal. Towar.-Next-Gener. Intell. 2018, 30, 439–481. doi:10.1007/978-3-319-60435-0_18. 1265. Barbosa, G.; Endo, P.; Sadok, D. An internet of things security system based on grouping of smart cards managed by field programmable gate array. Comput. Electr. Eng. 2019, 74, 331–348. doi:10.1016/j.compeleceng.2019.02.013. 1266. Prasetyo, K.N.; Purwanto, Y.; Darlis, D. An implementation of data encryption for internet of things using blowfish algorithm on fpga. In Proceedings of the 2nd International Conference on Information and Communication Technology (ICoICT), Bandung, Indonesia, 28–30 May 2014. 1267. Khatib, K.; Ahmed, M.; Kamaleldin, A.; Abdelghany, M.; Mostafa, H. Dynamically Reconfigurable Power Efficient Security for Internet of Things Devices. In Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies (MOCAST), Aristotle Univ, Res Disseminat Ctr, Thessaloniki, Greece, 7–9 May 2018. 1268. Gookyi, D.; Ryoo, K. Design of cryptographic core for protecting low cost IoT devices. In Proceedings of the 13th International Conference on Future Information Technology, FutureTech 2018, Salerno, Italy, 23–25 April 2018. doi:10.1007/978-981-13-1328-8_53. 1269. Le, X.S.; Le Lann, J.C.; Lagadec, L.; Fabresse, L.; Bouraqadi, N.; Laval, J. CaRDIN: An Agile Environment for Edge Computing on Reconfigurable Sensor Networks. In Proceedings of the International Conference on Computational Science and Computational Intelligence (CSIC), Las Vegas, NV, USA, 15–17 December 2016. doi:10.1109/CSCI.2016.38. 1270. Danner, J.; Wills, L.; Ruiz, E.M.; Lerner, L.W. Rapid Precedent-Aware Pedestrian and Car Classification on Constrained IoT Platforms. In Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia), Pittsburgh, PA, USA, 6–7 October 2016. doi:10.1145/2993452.2993562. 1271. Damljanovic, A.; Lanza-Gutierrez, J. An embedded cascade SVM approach for face detection in the IoT edge layer. In Proceedings of the 44th Annual Conference of the IEEE Industrial Electronics Society, IECON 2018, Washington, DC, USA, 20–23 October 2018. doi:10.1109/IECON.2018.8591634. 1272. Tsai, W.C.; Zhu, S.X.; Lu, M.H.; Merzoug, J.; Yu, C.; Huang, I. An Implementation of IoT Gateway for Home Appliances Control over Cellular Network. In Proceedings of the 8th IEEE International Conference on Awareness Science and Technology (iCAST), Chaoyang Univ Technol, Taichung, Taiwan, 8–10 November 2017. 1273. Song, K.; Huang, Z.; Gao, H. Design of intelligent environmental gateway platform based on Zynq-7000. In Proceedings of the 2nd International Conference on Advances in Image Processing, ICAIP 2018, Chengdu, China, 16–18 June 2018. doi:10.1145/3239576.3239604. 1274. Tan, T.H.; Ooi, C.Y.; Marsono, M.N. hpFog: A FPGA-based Fog Computing Platform. In Proceedings of the 12th International Conference on Networking, Architecture, and Storage (NAS), Shenzhen, China, 7–9 August 2017. 1275. Laurent, J.; Benoit, P.; Dalmasso, L.; Gil, T. Computing in the Fog with Reconfigurable Gateways. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 27–30 May 2018. 1276. Dufour, C.; Belanger, J.; Lapointe, V. FPGA-based ultra-low latency HIL fault testing of a permanent magnet motor drive using RT-LAB-XSG. Simul.-Trans. Soc. Model. Simul. Int. 2008, 84, 161–171. doi:10.1177/0037549708091537. 1277. Mina, J.; Flores, Z.; Lopez, E.; Perez, A.; Calleja, J.H. Processor-in-the-Loop and Hardware-in-the-Loop Simulation of Electric Systems based in FPGA. In Proceedings of the 13th International Conference on Power Electronics (CIEP), Inst Tecnologico Super Irapuato, Guanajuato, Mexico, 20–23 June 2016. 1278. Aiello, G.; Cacciato, M.; Scarcella, G.; Scelba, G. Failure analysis of AC motor drives via FPGA-based hardware-in-the-loop simulations. Electr. Eng. 2017, 99, 1337–1347. doi:10.1007/s00202-017-0630-3. 1279. Paiz, C.; Pohl, C.; Porrmann, M. Hardware-in-the-loop simulations for FPGA-based digital control design. doi:10.1007/978-3-540-79142-3_27. 1280. Sanchez, A.; Todorovich, E.; de Castro, A. Exploring the Limits of Floating-Point Resolution for Hardware-In-the-Loop Implemented with FPGAs. Electronics 2018, 7. doi:10.3390/electronics7100219. 1281. Abourida, S.; Cense, S.; Dufour, C.; Belanger, J. Hardware-in-the-loop simulation of electric systems and power Electronics on FPGA using physical modeling. In Proceedings of the 2013 4th International Computation 2019, xx, 5 94 of 115 Conference on Power Engineering, Energy and Electrical Drives, POWERENG 2013, Istanbul, Turkey, 13–17 May 2013. doi:10.1109/PowerEng.2013.6635708. 1282. Sandre-Hernandez, O.; Rangel-Magdaleno, J.; Morales-Capora, R.; Bonilla-Huerta, E. HIL simulation of the DTC for a three-level inverter fed a PMSM with neutral-point balancing control based on FPGA. Electr. Eng. 2018, 100, 1441–1454. doi:10.1007/s00202-017-0597-0. 1283. Sajabi, C.; Chen, C.I.H.; Lin, D.M.; Tsui, J.B.Y. FPGA frequency domain based GPS coarse acquisition processor using FFT. In Proceedings of the 23rd IEEE Instrumentation and Measurement Technology Conference, Sorrento, Italy, 24–27 April 2006. doi:10.1109/IMTC.2006.328619. 1284. Yu, X.; Sun, Y.; Liu, J.; Miao, J. Design and realization of synchronization circuit for GPS software receiver based on FPGA. J. Syst. Eng. Electron. 2010, 21, 20–26. doi:10.3969/j.issn.1004-4132.2010.01.004. 1285. Marchan-Hemandez, J.F.; Ramos-Perez, I.; Bosch-Lluis, X.; Camps, A.; Prehn, R. FPGA-based implementation of a DDM-generator for GPS-reflectometry. In Proceedings of the IEEE International Geoscience and Remote Sensing Symposium (IGARSS), Denver, CO, USA, 31 July–4 August 2006. doi:10.1109/IGARSS.2006.305. 1286. Slanina, Z.; Kasik, V.; Musil, K. GPS Synchronisation for FPGA Devices. In Proceedings of the 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems (PDeS), Brno, Czech Republic, 23–25 May 2012. 1287. Yang, Y.B.; Yang, X.Y.; Zhou, J. Realize accurate timing with FPGA during GPS synch failure. Dianli Zidonghua Shebei / Electr. Power Autom. Equip. 2007, 27, 109–112. 1288. Kavya, G.; Bai, V. Design and implementation of global positioning system receiver in field programmable gate array with short message service. Journal of Computer Science 2013, 10, 91–98. doi:10.3844/jcssp.2014.91.98. 1289. Du, Y.; Li, J.; Wang, B.; Jiang, Q. Design of GPS data acquisition and processing system based on FPGA. In Proceedings of the 2nd International Conference on Information Science and Engineering, ICISE2010, Hangzhou, USA, 4–6 December 2010. doi:10.1109/ICISE.2010.5690913. 1290. Wang, E.S.; Zhang, S.F.; Hu, Q.; Jiang, Y.; Sun, X.W. GPS correlator research and FPGA implementation. Xitong Fangzhen Xuebao / J. Syst. Simul. 2008, 20, 3582–3585. 1291. Wang, Y.; Gao, Y.; Wang, M. The Implementation of Rapid Acquisition Algorithm for GPS Weak Signal by Using FPGA. In Proceedings of the 5th China Satellite Navigation Conference (CSNC), Nanjing, China, 21–23 May 2014. doi:10.1007/978-3-642-54737-9_17. 1292. Diaz, J.; Garcia, J.; Roncagliolo, P. An FPGA implementation of a data-bit asynchronous GPS/GLONASS correlator. In Proceedings of the 7th Argentine School of Micro-Nanoelectronics, Technology and Applications, EAMTA 2012, Cordoba, Spain, 4–12 August 2012. 1293. Hu, H.; Yuan, C.; Wu, C.; Gao, M.H. FPGA-based GPS correlator research and implementation. Xitong Fangzhen Xuebao / Journal of System Simulation 2011, 23, 1513–1517+1521. 1294. Kumar, B.P.; Paidimarry, C.S. Development and Analysis of C/A Code Generation of GPS Receiver in FPGA and DSP. In Proceedings of the Conference on Recent Advances in Engineering and Computational Sciences (RAECS), Chandigarh, India, 6–8 March 2014. 1295. Ming, P. FPGA-Based GPS Application System Design. In Proceedings of the 21st Chinese Control and Decision Conference, Guilin, China, 17–19 June 2009. doi:10.1109/CCDC.2009.5191575. 1296. Zeng, Y.; Yu, Y.; Liu, L. Realization of Baseband Signal Processing for Beidou/GPS Multi-Mode Receiver by FPGA. In Proceedings of the 9th IEEE International Conference on Communication Software and Networks (ICCSN), GuangZhou, China, 6–8 May 2017. 1297. Gao, Y.Y.; Li, Y.H.; Feng, Q.L.; Wang, Y.L. Research of intermediate frequency GPS signal simulator based on FPGA. In Proceedings of the 2012 International Conference on Computer Science and Service System, CSSS 2012, Nanjing, China, 11–13 August 2012. doi:10.1109/CSSS.2012.277. 1298. Guo, J.; Cai, X.; He, C. Design and implementation of the tightly-coupled SINS/GPS integrated navigation system based on FPGA for target missile. In Proceedings of the 2012 2nd International Conference on Machinery Electronics and Control Engineering, ICMECE 2012, Jinan, China, 29 –30 December 2012. doi:10.4028/www.scientific.net/AMM.313-314.287. 1299. Hong, K.J.; Choi, Y.; Jung, J.H.; Kang, J.; Hu, W.; Lim, H.K.; Huh, Y.; Kim, S.; Jung, J.W.; Kim, K.B.; Song, M.S.; Park, H.w. A prototype MR insertable brain PET using tileable GAPD arrays. Med Phys. 2013, 40. doi:10.1118/1.4793754. Computation 2019, xx, 5 95 of 115 1300. Moses, W.W.; Buckley, S.; Vu, C.; Peng, Q.; Pavlov, N.; Choong, W.S.; Wu, J.; Jackson, C. OpenPET: A Flexible Electronics System for Radiotracer Imaging. In Proceedings of the IEEE Nuclear Science Symposium Conference 2009, Orlando, FL, USA, 25–31 October 2009. doi:10.1109/NSSMIC.2009.5401797. 1301. Imrek, J.; Novak, D.; Hegyesi, G.; Kalinka, G.; Molnar, J.; Vegh, J.; Balkay, L.; Emri, M.; Molnar, G.; Tron, L.; Bagamery, I.; Bukki, T.; Rozsa, S.; Szabo, Z.; Kerek, A. Development of an FPGA-based data acquisition module for small animal PET. IEEE Trans. Nucl. Sci. 2006, 53, 2698–2703. doi:10.1109/TNS.2006.876004. 1302. Menninga, H.; Favi, C.; Fishburn, M.W.; Charbon, Edoardo, S. A Multi-Channel, 10ps Resolution, FPGA-Based TDC with 300MS/s Throughput for Open-Source PET Applications. In Proceedings of the IEEE Nuclear Science Symposium/Medical Imaging Conference (NSS/MIC)/18th International Workshop on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors, Valencia, Spain, 23–29 October 2011. 1303. Ko, G.; Yoon, H.; Kwon, S.; Hong, S.; Lee, D.; Lee, J. Development of FPGA-based coincidence units with veto function. Biomedical Engineering Letters 2011, 1, 27–31. doi:10.1007/s13534-011-0001-3. 1304. Haselman, M.; DeWitt, D.; McDougald, W.; Lewellen, T.; Miyaoka, R.; Hauck, S. FPGA-based front-End Electronics for positron emission tomography. In Proceedings of the 7th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA’09, Monterey, CA, USA, 22–24 February 2009. doi:10.1145/1508128.1508143. 1305. Martinez, J.; Toledoa, J.; Esteve, R.; Sebastia, A.; Mora, F.; Benlloch, J.; Fernandez, M.; Gimenez, M.; Gimenez, E.; Lerche, C.; Pavon, N.; Sanchez, F. Design of a coincidence processing board for a dual-head PET scanner for breast imaging. Nucl. Instruments Methods Phys. Res. Sect. -Accel. Spectrometers Detect. Assoc. Equip. 2005, 546, 28–32. doi:10.1016/j.nima.2005.03.018. 1306. Shimazoe, K.; Orita, T.; Nakamura, Y.; Takahashi, H. Time over threshold based multi-channel LuAG-APD PET detector. Nucl. Instruments Methods Phys. Res. Sect. -Accel. Spectrometers Detect. Assoc. Equip. 2013, 731, 109–113. doi:10.1016/j.nima.2013.05.141. 1307. Imrek, J.; Hegyesi, G.; Kalinka, G.; Molnar, J.; Novak, D.; Valastyan, I.; Vegh, J.; Balkay, L.; Emri, M.; Kis, S.; Tron, L.; Buekki, T.; Szabo, Z.; Kerek, A. Development of an Improved Detector Module for miniPET-II. In Proceedings of the 15th International Workshop on Room-Temperature Semiconductor X- and Gamma-Ray Detectors/ 2006 IEEE Nuclear Science Symposium, San Diego, CA, USA, 29 October–4 November 2006. 1308. Xi, D.; Zeng, C.; Liu, W.; Liu, X.; Wan, L.; Kim, H.; Wang, L.; Kao, C.M.; Xie, Q. A PET detector module using FPGA-only MVT digitizers; IEEE: 5, 2013. In Proceedings of the 60th IEEE Nuclear Science Symposium (NSS) / Medical Imaging Conference (MIC) / 20th International Workshop on Room-Temperature Semiconductor X-ray and Gamma-ray Detectors, Seoul, Korea, 27 October–2 November 2013. 1309. Xi, D.; Zeng, C.; Mei, X.; Wan, L.; Liang, X.; Liu, W.; Liu, X.; Li, B.; Kim, H.; Xiao, P.; Kao, C.M.; Xie, Q. A Digital PET System based on SiPMs and FPGA-only MVT Digitizers. In Proceedings of the IEEE Nuclear Science Symposium / Medical Imaging Conference (NSS/MIC), Seattle, WA, USA, 8–15 November 2014. 1310. Kim, K.B.; Choi, Y.; Jung, J.; Lee, S.; Choe, H.j.; Leem, H.T. Analog and digital signal processing method using multi-time-over-threshold and FPGA for PET. Med. Phys. 2018, 45, 4104–4111. doi:10.1002/mp.13101. 1311. Fontaine, R.; Belanger, F.; Viscogliosi, N.; Semmaoui, H.; Tetrault, M.A.; Michaud, J.B.; Pepin, C.; Cadorette, J.; Lecomte, R. The Hardware and Signal Processing Architecture of LabPET (TM), a Small Animal APD-Based Digital PET Scanner. IEEE Trans. Nucl. Sci. 2009, 56, 3–9. doi:10.1109/TNS.2008.2007485. 1312. Fontaine, R.; Tetrault, M.; Belanger, F.; Viscogliosi, N.; Himmich, R.; Michaud, J.; Robert, S.; Leroux, J.; Semmaoui, H.; Berard, P.; et al. Real time digital signal processing implementation for an APD-based PET scanner with phoswich detectors. IEEE Trans. Nucl. Sci. 2006, 53, 784–788. doi:10.1109/TNS.2006.875441. 1313. Njejimana, L.; Tetrault, M.A.; Arpin, L.; Burghgraeve, A.; Maille, P.; Lavoie, J.C.; Paulin, C.; Koua, K.C.; Bouziri, H.; Panier, S.; et al. Design of a Real-Time FPGA-Based Data Acquisition Architecture for the LabPET II: An APD-Based Scanner Dedicated to Small Animal PET Imaging. IEEE Trans. Nucl. Sci. 2013, 60, 3633–3638. doi:10.1109/TNS.2013.2250307. 1314. Fysikopoulos, E.; Georgiou, M.; Efthimiou, N.; David, S.; Loudos, G.; Matsopoulos, G. Fully Digital FPGA-Based Data Acquisition System for Dual Head PET Detectors. IEEE Trans. Nucl. Sci. 2014, 61, 2764–2770. doi:10.1109/TNS.2014.2354984. 1315. Geoffroy, C.; Michaud, J.B.; Tetrault, M.A.; Clerk-Lamalice, J.; Brunet, C.A.; Lecomte, R.; Fontaine, R. Real Time Artificial Neural Network FPGA Implementation for Triple Coincidences Recovery in PET. IEEE Trans. Nucl. Sci. 2015, 62, 824–831. doi:10.1109/TNS.2015.2432754. Computation 2019, xx, 5 96 of 115 1316. Yan, A.H.; Liu, Y.Q.; Sun, X.S.; Kang, X.W. An FPGA-based coincidence system for micro PET. Hedianzixue Yu Tance Jishu/Nucl. Electron. Detect. Technol. 2010, 30, 157–160+165. 1317. Streun, M.; Brandenburg, G.; Larue, H.; Parl, C.; Ziemons, K. The data acquisition system of ClearPET neuro - a small animal PET scanner. IEEE Trans. Nucl. Sci. 2006, 53, 700–703. doi:10.1109/TNS.2006.875051. 1318. Fontaine, R.; Belanger, F.; Cadorette, J.; Leroux, J.; Martin, J.; Michaud, J.; Pratte, J.; Robert, S.; Lecomte, R. Architecture of a dual-modality, high-resolution, fully digital positron emission tomography/computed tomography (PET/CT) scanner for small animal imaging. IEEE Trans. Nucl. Sci. 2005, 52, 691–696. doi:10.1109/TNS.2005.850484. 1319. Laymon, C.; Miyaoka, R.; Park, B.; Lewellen, T. Simplified FPGA-based data acquisition system for PET. IEEE Trans. Nucl. Sci. 2003, 50, 1483–1486. doi:10.1109/TNS.2003.817947. 1320. Douraghy, A.; Rannou, F.R.; Alexandrakis, G.; Silvennan, R.W.; Chatziioannou, A.F. FPGA Electronics for OPET: A dual-modality optical and positron emission tomograph. In Proceedings of the IEEE Nuclear Science Symposium/Medical Imaging Conference, Honolulu, HI, USA, 26 October–3 November 2007. doi:10.1109/NSSMIC.2007.4436752. 1321. Yonggang, W.; Junwei, D.; Zhonghui, Z.; Yang, Y.; Lijun, Z.; Bruyndonckx, P. FPGA Based Electronics for PET Detector Modules With Neural Network Position Estimators. IEEE Trans. Nucl. Sci. 2011, 58, 34–42. doi:10.1109/TNS.2010.2081685. 1322. Hu, W.; Choi, Y.; Hong, K.J.; Rang, J.; Jung, J.H.; Huh, Y.S.; Lim, H.K.; Kim, S.S.; Kim, B.T.; Chung, Y. Free-running ADC- and FPGA-based signal processing method for brain PET using GAPD arrays. Nucl. Instruments Methods Phys. Res. Sect. -Accel. Spectrometers Detect. Assoc. Equip. 2012, 664, 370–375. doi:10.1016/j.nima.2011.05.053. 1323. Arabul, E.; Rarity, J.; Dahnoun, N. FPGA based fast integrated real-time multi coincidence counter using a time-to-digital converter. In Proceedings of the 7th Mediterranean Conference on Embedded Computing, MECO 2018, Budva, Montenegro, 10–14 June 2018. doi:10.1109/MECO.2018.8406094. 1324. Salomon, R.; Joost, R. PCDA - A Massively Parallel, Scalable, Precise, FPGA-based Coincidence Detector Array. In Proceedings of the 12th IEEE International Conference on Control and Automation (ICCA), Kathmandu, Nepal, 1–3 June 2016. 1325. Oliver, T.; Schmidt, B.; Maskell, D. Hyper customized processors for bio-sequence database scanning on FPGAs. In Proceedings of the ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005, Monterey, CA, USA, 20–22 February 2005. 1326. Surendar, A.; Arun, M.; Basha, A. Micro sequence identification of bioinformatics data using pattern mining techniques in FPGA hardware implementation. Asian J. Inf. Technol. 2016, 15, 76–81. 1327. Caffarena, G.; Pedreira, C.; Carreras, C.; Bojanic, S.; Nieto-Taladriz, O. Fpga acceleration for DNA sequence alignment. J. Circuits Syst. Comput. 2007, 16, 245–266. doi:10.1142/S0218126607003575. 1328. Varma, B.S.C.; Paul, K.; Balakrishnan, M.; Lavenier, D. FAssem : FPGA based Acceleration of De Novo Genome Assembly. In Proceedings of the 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Seattle, WA, USA, 28–30 April 2013. doi:10.1109/FCCM.2013.25. 1329. Surendar, A. FPGA based parallel computation techniques for bioinformatics applications. Int. J. Res. Pharm. Sci. 2017, 8, 124–128. 1330. Fernandez, E.B.; Najjar, W.A.; Lonardi, S.; Villarreal, J. Multithreaded FPGA Acceleration of DNA Sequence Mapping; IEEE: 6, 2012. In Proceedings of the IEEE Conference on High Performance Extreme Computing (HPEC), Waltham, MA, USA, 10–12 September 2012. 1331. Pechan, I.; Feher, B. Molecular docking on FPGA and GPU platforms. In Proceedings of the 21st International Conference on Field Programmable Logic and Applications, FPL 2011, Chania, Greece, 5–7 September 2011. doi:10.1109/FPL.2011.93. 1332. Kaessens, J.C.; Wienbrandt, L.; Gonzalez-Dominguez, J.; Schmidt, B.; Schimmler, M. High-speed exhaustive 3-locus interaction epistasis analysis on FPGAs. J. Comput. Sci. 2015, 9, 131–136. doi:10.1016/j.jocs.2015.04.030. 1333. Rucci, E.; De Giusti, A.; Naiouf, M.; Garcia, C.; Botella, G.; Prieto-Matias, M. Smith-Waterman Protein Search with OpenCL on an FPGA. In Proceedings of the 13th IEEE International Symposium on Parallel and Distributed Processing with Applications, Helsinki, Finland, 22–22 August 2015. doi:10.1109/Trustcom.2015.634. Computation 2019, xx, 5 97 of 115 1334. Rucci, E.; Garcia, C.; Botella, G.; De Giusti, A.E.; Naiouf, M.; Prieto-Matias, M. OSWALD: OpenCL Smith-Waterman on Altera’s FPGA for Large Protein Databases. Int. J. High Perform. Comput. Appl. 2018, 32, 337–350. doi:10.1177/1094342016654215. 1335. Isa, M.N.M.; Benkrid, K.; Clayton, T. A Novel Efficient FPGA Architecture for HMMER Acceleration; IEEE: 6, 2012. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 5–7 December 2012. 1336. Banerjee, S.S.; el Hadedy, M.; Tan, C.Y.; Kalbarczyk, Z.T.; Lumetta, S.; Iyer, R.K. On Accelerating Pair-HMM Computations in Programmable Hardware. In Proceedings of the 27th International Conference on Field Programmable Logic and Applications (FPL), Gent, Belgium, 4–8 September 2017. 1337. Gundlach, S.; Kassens, J.; Wienbrandt, L. Genome-wide association interaction studies with MB-MDR and maxT multiple testing correction on FPGAs. In Proceedings of the International Conference on Computational Science, ICCS 2016, San Diego, California, USA, 6–8 June 2016. doi:10.1016/j.procs.2016.05.354. 1338. Pacheco Bautista, D.; Carreno Aguilera, R.; Cortes Perez, E.; Gonzalez Perez, M.; Medel, J.J.; Acevedo, M.A.; Yu, W. NONLINEAR FM INDEX APPLICATION FOR ALIGNMENT OF SHORT DNA SEQUENCES USING RE-PARAMETRIZATION OF ALGORITHMS. Fractals-Complex Geom. Patterns Scaling Nat. Soc. 2018, 26. doi:10.1142/S0218348X18500238. 1339. Brossard, E.; Richmond, D.; Green, J.; Ebeling, C.; Ruzzo, L.; Olson, C.; Hauck, S. A Model for Programming Data-Intensive Applications on FPGAs: A Genomics Case Study. In Proceedings of the Symposium on Application Accelerators in High Performance Computing (SAAHPC), Argonne, IL, USA, 10–11 July 2012. doi:10.1109/SAAHPC.2012.18. 1340. Reggiani, E.; D’Arnese, E.; Purgato, A.; Santambrogio, M.D. Pearson Correlation Coefficient acceleration for modeling and mapping of neural interconnections. In Proceedings of the 31st IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPS), Orlando, FL, USA, 29 May–2 June 2017. doi:10.1109/IPDPSW.2017.63. 1341. Banerjee, S.S.; El-Hadedy, M.; Lim, J.B.; Kalbarczyk, Z.T.; Chen, D.; Lumetta, S.S.; Iyer, R.K. ASAP: Accelerated Short-Read Alignment on Programmable Hardware. IEEE Trans. Comput. 2019, 68, 331–346. doi:10.1109/TC.2018.2875733. 1342. Saliman, N.; Sabri, N.; Al, J.S.; Abd, M.Z.; Halim, A.; Md, T.N. Performance evaluation of local DNA sequence alignment smith-waterman algorithm software version cell design on FPGA. Int. J. Simul. Syst. Sci. Technol. 2016, 17. doi:10.5013/IJSSST.a.17.32.04. 1343. Romero-Troncoso, R.J.; Saucedo-Gallaga, R.; Cabal-Yepez, E.; Garcia-Perez, A.; Osornio-Rios, R.A.; Alvarez-Salas, R.; Miranda-Vidales, H.; Huber, N. FPGA-Based Online Detection of Multiple Combined Faults in Induction Motors Through Information Entropy and Fuzzy Inference. IEEE Trans. Ind. Electron. 2011, 58, 5263–5270. doi:10.1109/TIE.2011.2123858. 1344. Chekired, F.; Larbes, C.; Rekioua, D.; Haddad, F. Implementation of a MPPT fuzzy controller for photovoltaic systems on FPGA circuit. In Proceedings of the Conference on Impact of Integrated Clean Energy on the Future of the Mediterranean Environment, Beirut, Lebanon, 14–16 April 2011. doi:10.1016/j.egypro.2011.05.062. 1345. Munoz, D.M.; Llanos, C.H.; Ayala-Rincon, M.; van Els, R.H. Distributed approach to group control of elevator systems using fuzzy logic and FPGA implementation of dispatching algorithms. Eng. Appl. Artif. Intell. 2008, 21, 1309–1320. doi:10.1016/j.engappai.2008.04.014. 1346. Tipsuwanporn, V.; Runghimmawan, T.; Intajag, S.; Krongratana, V. Fuzzy Logic PID controller based on FPGA for process control. In Proceedings of the IEEE International Symposium on Industrial Electronics, Ajaccio, France, 4–7 May 2004. 1347. Soares dos Santos, M.P.; Ferreira, J.A.F. Novel intelligent real-time position tracking system using FPGA and fuzzy logic. ISA Trans. 2014, 53, 402–414. doi:10.1016/j.isatra.2013.09.003. 1348. Pena, M.; Gomez, J.A.; Osorio, R.; Lopez, I.; Lomas, V.; Gomez, H.; Lefranc, G. Fuzzy Logic for Omnidirectional Mobile Platform Control Displacement using FPGA and Bluetooth Communication Devices. IEEE Lat. Am. Trans. 2015, 13, 1907–1914. doi:10.1109/TLA.2015.7164216. 1349. Govindasamy, K.; Neeli, S.; Wilamowski, B.M. Fuzzy system with increased accuracy suitable for FPGA implementaion. In Proceedings of the 12th International Conference on Intelligent Engineering Systems, Miami, FL, USA, 25–29 February 2008. Computation 2019, xx, 5 98 of 115 1350. Perez-Patricio, M.; Aguilar-Gonzalez, A.; Arias-Estrada, M.; Hernandez-De Leon, H.R.; Camas-Anzueto, J.L.; de Jesus Osuna-Coutino, J.A. An FPGA stereo matching unit based on fuzzy logic. Microprocess. Microsyst. 2016, 42, 87–99. doi:10.1016/j.micpro.2015.10.011. 1351. Tchendjou, G.T.; Simeu, E.; Alhakim, R. Fuzzy logic based objective image quality assessment with FPGA implementation. J. Syst. Archit. 2018, 82, 24–36. doi:10.1016/j.sysarc.2017.12.002. 1352. Rojas, M.; Ponce, P.; Molina, A. A fuzzy logic navigation controller implemented in hardware for an electric wheelchair. Int. J. Adv. Robot. Syst. 2018, 15. doi:10.1177/1729881418755768. 1353. Mehamel, S.; Slimani, K.; Bouzefrane, S.; Daoui, M. Energy-efficient hardware caching decision using fuzzy logic in mobile edge computing. In Proceedings of the 6th IEEE International Conference on Future Internet of Things and Cloud Workshops, W-FiCloud 2018, Barcelona, Spain, 6–8 August 2018. doi:10.1109/W-FiCloud.2018.00045. 1354. Magaz, B.; Bencheikh, M.L. An Efficient FPGA Implementation of The OS-CFAR Processor. In Proceedings of the International Radar Symposium, Wroclaw, Poland, 21–23 May 2008. 1355. Pfeffer, C.; Feger, R.; Schmid, C.; Wagner, C.; Stelzer, A. An IQ-modulator based heterodyne 77-GHz FMCW colocated MIMO radar system. In Proceedings of the 2012 IEEE MTT-S International Microwave Symposium, IMS 2012, Montreal, QC, Canada, 17–22 June 2012. doi:10.1109/MWSYM.2012.6258387. 1356. Yeary, M.; Kelley, R.; Meier, J.; Ong, S.; Palmer, R. Compact Digital Receiver Development for Radar Based Remote Sensing. In Proceedings of the 25th IEEE Instrumentation and Measurement Technology Conference, Victoria, BC, Canada, 12–15 May 2008. doi:10.1109/IMTC.2008.4547329. 1357. Stasiak, K.; Samczynski, P. FMCW Radar Implemented in SDR Architecture Using a USRP Device. In Proceedings of the Signal Processing Symposium (SPSympo), Jachranka Village, Poland, 12–14 September 2017. 1358. Parlak, M.; Matsuo, M.; Buckwalter, J.F. Analog Signal Processing for Pulse Compression Radar in 90-nm CMOS. IEEE Trans. Microw. Theory Tech. 2012, 60, 3810–3822. doi:10.1109/TMTT.2012.2222433. 1359. Lu, L.; Lei, J.; Zou, X.; Zhang, X. Design of A Low-Cost Airborne Radar Target Simulator Based on FPGA. In Proceedings of the 12th International Symposium on Integrated Circuits, Singapore, Singapore, 14–16 December 2009. 1360. Miller, L.A. The Role of FPGAs in the Push to Modern and Ubiquitous Arrays. Proc. IEEE 2016, 104, 576–585. doi:10.1109/JPROC.2016.2519286. 1361. Pallavi, N.; Anjaneyulu, P.; Reddy, P.B.; Mahendra, V.; Karthik, R. Design and Implementation of Linear Frequency Modulated waveform using DDS and FPGA. In Proceedings of the International conference of Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 20–22 April 2017. 1362. Zhang, C.; Yu, S.; Zhang, L.; Gong, Y. An FPGA-based pulse integration system to improve the SNR of radar echo. Int. J. Circuits Syst. Signal Process. 2019, 13, 114–119. 1363. Michael, T.; Reynolds, S.; Woolford, T. Designing a Generic, Software-Defined Multimode Radar Simulator For FPGAs Using Simulink (R) HDL Coder and Speedgoat Real-Time Hardware. In Proceedings of the International Conference on Radar (RADAR), Brisbane, Australia, 27–31 August 2018. 1364. Morales, D.P.; Garcia, A.; Castillo, E.; Carvajal, M.A.; Banqueri, J.; Palma, A.J. Flexible ECG acquisition system based on analog and digital reconfigurable devices. Sensors Actuators -Phys. 2011, 165, 261–270. doi:10.1016/j.sna.2010.10.008. 1365. Mishra, S.; Das, D.; Kumar, R.; Sumathi, P. A Power-Line Interference Canceler Based on Sliding DFT Phase Locking Scheme for ECG Signals. IEEE Trans. Instrum. Meas. 2015, 64, 132–142. doi:10.1109/TIM.2014.2335920. 1366. Ramos, R.; Manuel-Lazaro, A.; Del Rio, J.; Olivar, G. FPGA-based implementation of an adaptive canceller for 50/60-Hz interference in electrocardiography. IEEE Trans. Instrum. Meas. 2007, 56, 2633–2640. doi:10.1109/TIM.2007.904472. 1367. Yang, Y.; Huang, X.; Yu, X. Real-time ECG monitoring system based on FPGA. In Proceedings of the 33rd Annual Conference of the IEEE-Industrial-Electronics-Society, Taipei, Taiwan, 5–8 November 2007. doi:10.1109/IECON.2007.4459886. 1368. Chatterjee, H.K.; Gupta, R.; Mitra, M. Real time P and T wave detection from ECG using FPGA. In Proceedings of the 2nd International Conference on Computer, Communication, Control and Information Technology (C3IT), India, 25–26 February 2012. doi:10.1016/j.protcy.2012.05.138. Computation 2019, xx, 5 99 of 115 1369. Cvikl, M.; Zemva, A. FPGA-based System for ECG Beat Detection and Classification. In Proceedings of the 11th Mediterranean Conference on Medical and Biological Engineering and Computing (MEDICON 2007), Ljubljana, Slovenia, 26–30 June 2007. 1370. Chou, C.C.; Fang, W.C.; Huang, H.C. A Novel Wireless Biomedical Monitoring System with Dedicated FPGA-based ECG Processor. In Proceedings of the IEEE 16th International Symposium on Consumer Electronics (ISCE), Harrisburg, PA, USA, 4–6 June 2012. 1371. Eka, M.S.; Fajar, M.; Iqbal, M.T.; Jatmiko, W.; Agus, I.M. FNGLVQ FPGA Design for Sleep Stages Classification based on Electrocardiogram Signal. In Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics (SMC), Seoul, Korea, 14–17 October 2012. 1372. El, M.E.; Karim, M. Novel real-time FPGA-based QRS detector using adaptive threshold with the previous smallest peak of ECG signal. J. Theor. Appl. Inf. Technol. 2013, 50, 33–43. 1373. Aboutabikh, K.; Aboukerdah, N. Design and implementation of a multiband digital filter using FPGA to extract the ECG signal in the presence of different interference signals. Comput. Biol. Med. 2015, 62, 1–13. doi:10.1016/j.compbiomed.2015.03.034. 1374. Gu, X.; Zhu, Y.; Zhou, S.; Wang, C.; Qiu, M.; Wang, G. A Real-Time FPGA-Based Accelerator for ECG Analysis and Diagnosis Using Association-Rule Mining. ACM Trans. Embed. Comput. Syst. 2016, 15. doi:10.1145/2821508. 1375. Giorgio, A. A new FPGA-based medical device for the real time prevention of the risk of arrythmias. Int. J. Appl. Eng. Res. 2016, 11, 6013–6018. 1376. El Mimouni, E.H.; Karim, M.; El Kouache, M.; Amarouch, M.Y. An FPGA-Based System for Real-Time Electrocardiographic Detection of STEMI. In Proceedings of the 2nd International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), Monastir, Tunisia, 21–23 March 2016. 1377. Zhang, B.; Sieler, L.; Morere, Y.; Bolmont, B.; Bourhis, G. Dedicated wavelet QRS complex detection for FPGA implementation. In Proceedings of the 3rd International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), Fez, Morocco, 22–24 May 2017. 1378. Zhang, B.; Sieler, L.; Morere, Y.; Bolmont, B.; Bourhis, G. A Modified Algorithm for QRS Complex Detection for FPGA Implementation. Circuits Syst. Signal Process. 2018, 37, 3070–3092. doi:10.1007/s00034-017-0711-6. 1379. Chen, I.W.; Chuang, S.Y.; Wu, W.J.; Fang, W.C. An Efficient Hardware Architecture Design of EEMD Processor for Electrocardiography Signal. In Proceedings of the IEEE Biomedical Circuits and Systems Conference (BioCAS) - Advanced Systems for Enhancing Human Health, Cleveland, OH, USA, 17–19 October 2018. 1380. Lin, K.J.; Huang, H.H.; Lin, Y.Y. An FPGA Implementation of Lossless ECG Compressors Based on Multi-Stage Huffman Coding. In Proceedings of the IEEE 7th Global Conference on Consumer Electronics (GCCE), Nara, Japan, 9–12 October 2018. 1381. Su, W.; Liang, Y.; Li, M.; Li, Y. The research and FPGA implementation of ECG signal preprocessing. In Proceedings of the International Conference on Biomedical and Health Informatics, ICBHI 2015, Haikou, China, 8–10 October 2015. doi:10.1007/978-981-10-4505-9_35. 1382. Ustun, T.E.; Iftimia, N.V.; Ferguson, R.D.; Hammer, D.X. Real-time processing for Fourier domain optical coherence tomography using a field programmable gate array. Rev. Sci. Instruments 2008, 79. doi:10.1063/1.3005996. 1383. Kepa, K.; Coburn, D.; Dainty, J.C.; Morgan, F. High Speed Optical Wavefront Sensing with Low Cost FPGAs. Meas. Sci. Rev. 2008, 8, 87–93. doi:10.2478/v10048-008-0021-z. 1384. Rodriguez-Ramos, J.M.; Magdaleno Castello, E.; Dominguez Conde, C.; Rodriguez Valido, M.; Marichal-Hernandez, J.G. 2D-FFT implementation on FPGA for wavefront phase recovery from the CAFADIS camera. In Proceedings of the Conference on Adaptive Optics Systems, Marseille, France, 23–28 June 2008. doi:10.1117/12.789312. 1385. Rodriguez-Ramos, L.; Viera, T.; Herrera, G.; Gigante, J.; Gago, F.; Alonso, A. Testing FPGAs for real-time control of adaptive optics in giant telescopes. In Proceedings of the Advances in Adaptive Optics II, Orlando, FL, USA, 24–31 May 2006. doi:10.1117/12.669960. 1386. Mauch, S.; Reger, J.; Reinlein, C.; Appelfelder, M.; Goy, M.; Beckert, E.; Tunnermann, A. FPGA-accelerated adaptive optics wavefront control. In Proceedings of the MEMS Adaptive Optics VIII, San Francisco, CA, USA, 2 February 2014. doi:10.1117/12.2038910. Computation 2019, xx, 5 100 of 115 1387. Perret, D.; Laine, M.; Bernard, J.; Gratadour, D.; Sevin, A. Bridging FPGA and GPU technologies for AO real-time control; SPIE-INT SOC Opt. Eng.: 11, 2016; Vol. 9909. In Proceedings of the Conference on Adaptive Optics Systems V, Edinburgh, UK, 26 June–1 July 2016. doi:10.1117/12.2232858. 1388. Jia, J.L.; Zhao, J.Y.; Wang, J.L.; Wang, S.; Wang, L.; Wu, Q.L. Adaptive optical wave-front processing algorithm based on FPGA. Guangxue Jingmi Gongcheng/Opt. Precis. Eng. 2017, 25, 2580–2583. doi:10.3788/OPE.20172510.2580. 1389. Yang, H.; Xia, Y.; Zhang, H.; Li, M.; Rao, C. Efficient and low-latency pixel data transmission module for adaptive optics wavefront processor based on field-programmable gate array. Opt. Eng. 2015, 54. doi:10.1117/1.OE.54.6.063106. 1390. Patauner, C.; Biasi, R.; Andrighettoni, M.; Angerer, G.; Pescoller, D.; Porta, F.; Gratadour, D. FPGA based microserver for high performance real-time computing in Adaptive Optics. In Proceedings of the 5th Adaptive Optics for Extremely Large Telescopes, AO4ELT 2017, Canary Islands, Spain, 25–30 June 2017. 1391. Surendran, A.; Burse, M.P.; Ramaprakash, A.N.; Paul, J.; Das, H.K.; Parihar, P.S. Scalable platform for adaptive optics real-time control, part 1: concept, architecture, and validation. J. Astron. Telesc. Instrum. Syst. 2018, 4. doi:10.1117/1.JATIS.4.3.039001. 1392. Surendran, A.; Burse, M.P.; Ramaprakash, A.N.; Parihar, P.S. Scalable platform for adaptive optics real-time control, part 2: field programmable gate array implementation and performance. JJ. Astron. Telesc. Instrum. Syst. 2018, 4. doi:10.1117/1.JATIS.4.3.039002. 1393. Kong, F.; Polo, M.C.; Lambert, A. On-sky results and performance of low latency centroiding algorithms for adaptive optics implemented in FPGA. In Proceedings of the Conference on Unconventional and Indirect Imaging, Image Reconstruction, and Wavefront Sensing, San Diego, CA, USA, 22–23 August 2018. doi:10.1117/12.2320084. 1394. Chen, Y.P.; Chang, C.Y.; Chen, S.J. Rapid and highly integrated FPGA-based Shack-Hartmann wavefront sensor for adaptive optics system. In Proceedings of the Conference on Adaptive Optics and Wavefront Control for Biological Systems IV, San Francisco, CA, USA, 27–29 January 2018. doi:10.1117/12.2289095. 1395. Price, A.; Pyke, J.; Ashiri, D.; Cornall, T. Real time object detection for an unmanned aerial vehicle using an FPGA based vision system; IEEE: 2, 2006; pp. 2854–+. In Proceedings of the IEEE International Conference on Robotics and Automation (ICRA), Orlando, FL, USA, 15–19 May 2006. doi:10.1109/ROBOT.2006.1642134. 1396. Monterrosa, N.; Bran, C. Design and implementation of a motor control module based on PWM and FPGA for the development of a UAV flight controller. In Proceedings of the CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies (CHILECON), Santiago De Chile, Chile, 28–30 October 2015. 1397. Eizad, B.; Doshi, A.; Postula, A. FPGA based stability system for a small-scale quadrotor unmanned aerial vehicle. In Proceedings of the 8th FPGAworld Conference, FPGAworld 2011, Stockholm, Sweden, 12–15 September 2011. doi:10.1145/2157871.2157874. 1398. Wang, H.; Azaizia, D.; Lu, C.; Zhang, B.; Zhao, X.; Liu, Y. Hardware in the Loop Based 6DoF Test Platform for Multi-rotor UAV. In Proceedings of the 4th International Conference on Systems and Informatics (ICSAI), Hangzhou, China, 11–13 November 2017. 1399. Li, W.; Zhang, H.; Hildre, H.P.; Wang, J. An FPGA-based real-time UAV SAR raw signal simulator. IEICE Electron. Express 2014, 11. doi:10.1587/elex.11.20140168. 1400. Cadena, A.; Ponguillo, R.; Ochoa, D. Development of Guidance, Navigation and Control System Using FPGA Technology for an UAV Tricopter. In Proceedings of the 2nd International Conference on Mechatronics and Robotics Engineering (ICMRE), Nice, France, 18–22 February 2016. doi:10.1007/978-3-319-33581-0_28. 1401. Wang, H.; Zhang, B.; Zhao, X.; Li, C.; Lu, C. A Study on Low-Cost, High-Accuracy and Real-Time Stereo Vision Algorithms for UAV Power Line Inspection. In Proceedings of the 10th International Conference on Machine Vision (ICMV), Vienna, Austria, 13–15 November 2017. doi:10.1117/12.2309434. 1402. Ladig, R.; Leewiwatwong, S.; Shimonomura, K. FPGA-Based Fast Response Image Analysis for Orientational Control in Aerial Manipulation Tasks. J. Signal Process. Syst. Signal Image Video Technol. 2018, 90, 901–911. doi:10.1007/s11265-017-1286-y. 1403. Turqueti, M.; Saniie, J.; Oruklu, E. MEMS Acoustic Array Embedded in an FPGA Based Data Acquisition and Signal Processing System. In Proceedings of the 53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010), Seattle, WA, USA, 1–4 August 2010. doi:10.1109/MWSCAS.2010.5548866. Computation 2019, xx, 5 101 of 115 1404. Dai, G.; Li, M.; Su, W.; Shao, B. A novel single chip implementation of MEMS INS data acquisition and processing system using FPGA and its soft processors. In Proceedings of the 9th International Conference on Electronic Measurement and Instruments, ICEMI 2009, Beijing, China, 16–19 August 2009. doi:10.1109/ICEMI.2009.5274805. 1405. Wang, L.; Hao, Y.; Wei, Z.; Wang, F. Thermal calibration of MEMS inertial Sensors for an FPGA-based navigation system. In Proceedings of the 3rd International Conference on Intelligent Networks and Intelligent Systems, ICINIS 2010, Shenyang, China, 1–3 November 2010. doi:10.1109/ICINIS.2010.45. 1406. Guerard, J.; Delahaye, L.; Levy, R. Digital Electronics for inertial MEMS and space applications. In Proceedings of the 20th Symposium on Design, Test, Integration and Packaging of MEMS and MOEMS, DTIP 2018, Roma, Italy, 22–25 May 2018. doi:10.1109/DTIP.2018.8394236. 1407. Sarraf, E.H.; Kansal, A.; Sharma, M.; Cretu, E. FPGA-based Novel Adaptive Scheme Using PN Sequences for Self-Calibration and Self-Testing of MEMS-based Inertial Sensors. J. Electron.-Test.-Theory Appl. 2012, 28, 599–614. doi:10.1007/s10836-012-5336-x. 1408. Alves, F.S.; Dias, R.A.; Cabral, J.; Rocha, L.A.; Monteiro, J. FPGA Controlled MEMS Inclinometer. In Proceedings of the IEEE International Symposium on Industrial Electronics (ISIE), Taipei, Taiwan, 28–31 May 2013. 1409. Zereen, S.; Lal, S.; Khalid, M.A.S.; Chowdhury, S. An FPGA-based controller for a 77 GHz MEMS tri-mode automotive radar. Microprocess. Microsyst. 2018, 58, 34–40. doi:10.1016/j.micpro.2018.02.005. 1410. Zhao, W.; Cheng, Y.; Sun, D.; Tang, J.; Liu, Z.; Ou, B.; Zhang, W. Design of MEMS RIG with hemispherical resonator and its FPGA platform. Bandaoti Guangdian/Semicond. Optoelectron. 2017, 38, 40–44. doi:10.16818/j.issn1001-5868.2017.01.009. 1411. Ghassemi, F.; Possas, M.; Amendola, G.; Juillard, J. FPGA implementation of a low-cost method for tracking the resonance frequency and the quality factor of MEMS Sensors. In Proceedings of the 11th IEEE Sensors Conference, Taipei, Taiwan, 28–31 October 2012. 1412. Wrighton, M.; DeHon, A. Hardware-assisted simulated annealing with application for fast FPGA placement. In Proceedings of the ACM/SIGDA 11th ACM International Symposium on Field Programmable Gate Arrays, Monterey, CA, USA, 23–25 February 2003. 1413. Vorwerk, K.; Kennings, A.; Greene, J.W. Improving Simulated Annealing-Based FPGA Placement With Directed Moves. IEEE Trans.-Comput.-Aided Des. Integr. Circuits Syst. 2009, 28, 179–192. doi:10.1109/TCAD.2008.2009167. 1414. Eguro, K.; Hauck, S.; Sharma, A. Architecture-adaptive range limit windowing for simulated annealing FPGA placement. In Proceedings of the 42nd Design Automation Conference, Anaheim, CA, USA, 13–17 June 2005. 1415. He, G.; Xiong, N.; Yang, L.T.; Kim, T.h.; Hsu, C.H.; Li, Y.; Hu, T. Evolvable hardware design based on a novel simulated annealing in an embedded system. Concurr.-Comput.-Pract. Exp. 2012, 24, 354–370. doi:10.1002/cpe.1604. 1416. Regadio, A.; Sanchez-Prieto, S.; Tabero, J. Synthesis of optimal digital shapers with arbitrary noise using simulated annealing. Nucl. Instruments Methods Phys. Res. Sect. -Accel. Spectrometers Detect. Assoc. Equip. 2014, 738, 74–81. doi:10.1016/j.nima.2013.11.099. 1417. Lukowiak, M.; Cody, B. FPGA based accelerator for simulated annealing with greedy perturbations. In Proceedings of the 14th International Conference on Mixed Design of Integrated Circuits and Systems, Ciechocinek, Poland, 21–23 June 2007. 1418. Yuan, J.; Chen, J.; Wang, L.; Zhou, X.; Xia, Y.; Hu, J. ARBSA: Adaptive Range-Based Simulated Annealing for FPGA Placement. IEEE Trans. -Comput.-Aided Des. Integr. Circuits Syst. 2018. doi:10.1109/TCAD.2018.2878180. 1419. Hu, C.; Lu, P.; Yang, M.; Wang, J.; Lai, J. A SA-based parallel method for FPGA placement. IEICE Electron. Express 2018, 15. doi:10.1587/elex.15.20180943. 1420. Mou, H. Research on constant temperature control in vehicle based on the simulated annealing optimization PID algorithm of FPGA. Pap. Asia 2019, 2, 180–183. 1421. Bhuyan, A.; Choe, J.W.; Lee, B.C.; Wygant, I.O.; Nikoozadeh, A.; Oralkan, O.; Khuri-Yakub, B.T. Integrated Circuits for Volumetric Ultrasound Imaging With 2-D CMUT Arrays. IEEE Trans. Biomed. Circuits Syst. 2013, 7, 796–804. doi:10.1109/TBCAS.2014.2298197. Computation 2019, xx, 5 102 of 115 1422. Assef, A.A.; Maia, J.M.; Schneider, F.K.; Button, V.L.S.N.; Costa, E.T. A reconfigurable arbitrary waveform generator using PWM modulation for ultrasound research. Biomed. Eng. Online 2013, 12. doi:10.1186/1475-925X-12-24. 1423. Tekes, C.; Xu, T.; Carpenter, T.M.; Bette, S.; Schnakenberg, U.; Cowell, D.; Freear, S.; Kocaturk, O.; Lederman, R.J.; Degertekin, F.L. Real-Time Imaging System using a 12-MHz Forward-Looking Catheter with Single Chip CMUT-on-CMOS Array. In Proceedings of the IEEE International Ultrasonics Symposium (IUS), Taipei, Taiwan, 21–24 October 2015. doi:10.1109/ULTSYM.2015.0521. 1424. Bhuyan, A.; Chang, C.; Choe, J.W.; Lee, B.C.; Nikoozadeh, A.; Oralkan, O.; Khuri-Yakub, B.T. A 32x32 Integrated CMUT Array for Volumetric Ultrasound Imaging. In Proceedings of the IEEE International Ultrasonics Symposium (IUS), Prague, Czech Republic, 21–25 July 2013. doi:10.1109/ULTSYM.2013.0141. 1425. Ma, J.; Karadayi, K.; Ali, M.; Kim, Y. Ultrasound phase rotation beamforming on multi-core DSP. Ultrasonics 2014, 54, 99–105. doi:10.1016/j.ultras.2013.03.016. 1426. Birk, M.; Kretzek, E.; Figuli, P.; Weber, M.; Becker, J.; Ruiter, N.V. High-Speed Medical Imaging in 3D Ultrasound Computer Tomography. IEEE Trans. Parallel Distrib. Syst. 2016, 27, 455–467. doi:10.1109/TPDS.2015.2405508. 1427. Hassan, M.; Youssef, A.B.; Kadah, Y. Modular FPGA-based digital ultrasound beamforming. In Proceedings of the 2011 1st Middle East Conference on Biomedical Engineering, MECBME 2011, Sharjah, United Arab Emirates, 21–24 February 2011. doi:10.1109/MECBME.2011.5752083. 1428. Blahuta, J.; Cermak, P.; Soukup, T.; Martinu, J.; Vecerkova, P. An algorithm to echogenicity level identification on medical B-images and its applicability on FPGA platform. In Proceedings of the IEEE Seventh International Conference on Intelligent Computing and Information Systems (ICICIS), CAIRO, Egypt, 12–14 December 2015. 1429. Supriyanto, E.; Jiar, Y.K.; Muttakin, I.; Ariffin, I.; Yu, Y.S. A Novel FPGA Based Platform for Ultrasound Power Measurement. In Proceedings of the 2010 3rd International Conference on Biomedical Engineering and Informatics (BMEI 2010), Yantai Univ, Yantai, China, 16–18 October 2010. doi:10.1109/BMEI.2010.5639403. 1430. Isabel, A. A low cost pulsed wave Doppler ultrasound system on Field Programmable Gate Arrays for vascular studies. In Proceedings of the World Congress on Medical Physics and Biomedical Engineering, Toronto, Canada, 7–12 June 2015. doi:10.1007/978-3-319-19387-8_308. 1431. Yang, H.; Zhang, J.; Wu, M.; Yang, J.; Yu, Z. An ultrasonic wireless data feedthrough system based on field programmable gate array. In Proceedings of the 24th International Congress on Sound and Vibration, ICSV 2017, London, UK, 23–27 July 2017. 1432. Assef, A.; Ferreira, B.; Maia, J.; Costa, E. Modeling and FPGA-based implementation of an efficient and simple envelope detector using a Hilbert Transform FIR filter for ultrasound imaging applications. Res. Biomed. Eng. 2018, 34, 87–92. doi:10.1590/2446-4740.02417. 1433. Jain, A.K.; Pham, K.D.; Cui, J.; Fahmy, S.A.; Maskell, D.L. Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform. J. Signal Process. Syst. Signal Image Video Technol. 2014, 77, 61–76. doi:10.1007/s11265-014-0884-1. 1434. Agne, A.; Platzner, M.; Lubbers, E. Memory virtualization for multithreaded reconfigurable hardware. In Proceedings of the 21st International Conference on Field Programmable Logic and Applications, FPL 2011, Chania, Greece, 5–7 September 2011. doi:10.1109/FPL.2011.42. 1435. Vu, D.V.; Sandmann, T.; Baehr, S.; Sander, O.; Becker, J. Virtualization Support for FPGA-based Coprocessors Connected via PCI Express to an Intel Multicore Platform. In Proceedings of the 28th IEEE International Parallel & Distributed Processing Symposium Workshops (IPDPSW), Phoenix, AZ, USA, 19–23 May 2014. doi:10.1109/IPDPSW.2014.42. 1436. Yazdanshenas, S.; Betz, V. Interconnect Solutions for Virtualized Field-Programmable Gate Arrays. IEEE Access 2018, 6, 10497–10507. doi:10.1109/ACCESS.2018.2806618. 1437. Mbongue, J.M.; Hategekimana, F.; Kwadjo, D.T.; Andrews, D.; Bobda, C. FPGAVirt: A Novel Virtualization Framework for FPGAs in the Cloud. In Proceedings of the 11th IEEE International Conference on Cloud Computing (CLOUD) Part of the IEEE World Congress on Services, San Francisco, CA, USA, 2–7 July 2018. doi:10.1109/CLOUD.2018.00122. 1438. Mbongue, J.M.; Hategekimana, F.; Kwadjo, D.T.; Bobda, C. FPGA Virtualization in Cloud-based Infrastructures over Virtio. In Proceedings of the 36th IEEE International Conference on Computer Design (ICCD), Orlando, FL, USA, 7–10 October 2018. doi:10.1109/ICCD.2018.00044. Computation 2019, xx, 5 103 of 115 1439. Duan, C.; Pekhteryev, G.; Fang, J.; Nakache, Y.P.; Zhang, J.; Tajima, K.; Nishioka, Y.; Hirai, H. Transmitting Multiple HD Video Streams over UWB Links. In Proceedings of the 3rd IEEE Consumer Communications and Networking Conference, Las Vegas, NV, USA, 8–10 January 2006. 1440. Sherratt, R.; Cadenas, O.; Goswami, N. A low clock frequency FFT core implementation for multiband full-rate ultra-wideband (UWB) receivers. IEEE Trans. Consum. Electron. 2005, 51, 798–802. doi:10.1109/TCE.2005.1510486. 1441. Gharaee, H.; Nabavi, A. Baseband implementation of OTR-UWB receiver using FPGA. AEU-Int. J. Electron. Commun. 2010, 64, 258–266. doi:10.1016/j.aeue.2009.01.001. 1442. Fernandes, B.; Sarmento, H. FPGA implementation and testing of a 128 FFT for a MB-OFDM receiver. Analog. Integr. Circuits Signal Process. 2012, 70, 241–248. doi:10.1007/s10470-011-9787-2. 1443. Yang, X.; Xue, J.; Wang, L.; Zhang, T. Implementation of symbol timing synchronization for MB-OFDM UWB systems on FPGA. In Proceedings of the 2011 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2011, Xi’an, China, 14 –16 September 2011. doi:10.1109/ICSPCC.2011.6061742. 1444. Albrawy, M.F.; El-Deen, A.E.T.; El-Awady, R.M.; Abo-Elsoaud, M.E. Implementation of Elliptic Curve Crypto-System to Secure Digital Images over Ultra-Wideband Systems Using FPGA. In Proceedings of the 2nd International Conference on Advanced Intelligent Systems and Informatics (AISI), Cairo, Egypt, 24–26 October 2016. doi:10.1007/978-3-319-48308-5_82. 1445. Le, Q.N.; Jeon, J.W. Neural-Network-Based Low-Speed-Damping Controller for Stepper Motor With an FPGA. IEEE Trans. Ind. Electron. 2010, 57, 3167–3180. doi:10.1109/TIE.2009.2037650. 1446. Carrica, D.; Funes, M.; Gonzalez, S. Novel stepper motor controller based on FPGA hardware implementation. IEEE-Asme Trans. Mechatronics 2003, 8, 120–124. doi:10.1109/TMECH.2003.809160. 1447. Ngoc, Q.; Jae, W. An open-loop stepper motor driver based on FPGA. In Proceedings of the International Conference on Control, Automation and Systems, ICCAS 2007, Seoul, Korea, 17–20 October 2007. doi:10.1109/ICCAS.2007.4406542. 1448. Chen, T.C.; Su, Y.C. High Performance Algorithm Realization on FPGA for Stepper Motor Controller. In Proceedings of the Annual Conference of the SICE, Chofu, Japan, 20–22 August 2008. 1449. Anish, N.; Krishnan, D.; Moorthi, S.; Selvan, M. FPGA based microstepping scheme for stepper motor in space-based solar power systems. In Proceedings of the 2012 IEEE 7th International Conference on Industrial and Information Systems, ICIIS 2012, Chennai, India, 6–9 August 2012. doi:10.1109/ICIInfS.2012.6304771. 1450. Wang, B.J.; Liu, Q.X.; Zhou, L.; Li, X.Q.; Zhang, J.Q. FPGA-based multiple-axis stepper motor controller. Dianji Yu Kongzhi Xuebao/Electr. Mach. Control 2012, 16, 78–82+89. 1451. Thulasiraman, N.; Mohamed, H.; Cheng, Y. A reconfigurable wireless stepper motor controller based on FPGA implementation. In Proceedings of the 2010 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2010, Penang, Malaysia, 3–5 October 2010. doi:10.1109/ISIEA.2010.5679398. 1452. Zaferullah, K.Z.; Bansode, R.; Pethe, S.N.; Vidwans, M.; Dsouza, K. Speed Control of Stepper Motor for Collimator Jaws Positioning based on FPGA Implementation. In Proceedings of the International Conference on Circuits, Systems, Communication and Information Technology Applications (CSCITA), Mumbai, India, 4–5 April 2014. 1453. Wang, B.; Liu, Q.; Zhou, L.; Zhang, Y.; Li, X.; Zhang, J. Velocity profile algorithm realization on FPGA for stepper motor controller. In Proceedings of the 2011 2nd International Conference on Artificial Intelligence, Management Science and Electronic Commerce, AIMSEC 2011, Zhengzhou, China, 8–10 August 2011. doi:10.1109/AIMSEC.2011.6009864. 1454. Yu, J.; Kang, H.; Wang, Y.; Lu, G. A Control System of Three-axis Stepper Motor Based on the FPGA. In Proceedings of the International Conference on Mechatronic Sciences, Electric Engineering and Computer (MEC), Shenyang, China, 20–22 December 2013. 1455. Adhul, S., V.; Nandagopal, J.L.; Revathi, H. Control Electronics module for flow control valve using FPGA. In Proceedings of the IEEE International Conference on Circuit ,Power and Computing Technologies (ICCPCT), Kollam, India, 20–21 April 2017. 1456. Han, X.; Lei, L.; Yang, Y. Design of the stepper motor control system based on FPGA. In Proceedings of the 2014 International Conference on Energy Research and Power Engineering, ERPE 2014, Dalian, China, 17–18 May 2014. doi:10.4028/www.scientific.net/AMR.986-987.1077. Computation 2019, xx, 5 104 of 115 1457. Feng, Q.; Wang, L. FPGA-Based Acceleration and Deceleration Control for CNC Machine Tools. In Proceedings of the International Conference on Mechatronic Sciences, Electric Engineering and Computer (MEC), Shenyang, China, 20–22 December 2013. 1458. Lai, C.K.; Ciou, J.S.; Tsai, C.C. FPGA-based Stepper Motor Vector Control System Design. In Proceedings of the International Automatic Control Conference (CACS), Pingtung, Taiwan, 12–15 November 2017. 1459. Ricci, S.; Meacci, V. Simple Torque Control Method for Hybrid Stepper Motors Implemented in FPGA. Electronics 2018, 7. doi:10.3390/electronics7100242. 1460. Hong-Bin, W.; Zhe, Z.; Xu-Hui, C.; Yuan-Bin, W. Stepper motor SPWM subdivision control circuit design based on FPGA. In Proceedings of the 16th IEEE/ACIS International Conference on Computer and Information Science, ICIS 2017, Wuhan, China, 24–26 May 2017. doi:10.1109/ICIS.2017.7960118. 1461. Yuen, L.; Ehkan, P. Design and implementation of FPGA based bipolar stepper motor controller for linear slide application. J. Telecommun. Electron. Comput. Eng. 2018, 10, 85–88. 1462. Meacci, V.; Matera, R.; Russo, D.; Ricci, S. Torque-oriented stepper motor control in FPGA. In Proceedings of the 2018 New Generation of CAS, NGCAS 2018, Valletta, Malta, 20 –23 November 2018. doi:10.1109/NGCAS.2018.8572147. 1463. van Eck, N.J.; Waltman, L. Software survey: VOSviewer, a computer program for bibliometric mapping. Scientometrics 2010, 84, 523–538. doi:10.1007/s11192-009-0146-3. 1464. Yu, H.; Kim, M.; Choi, E.; Jeon, T.; Lee, S. Design and prototype development of MIMO-OFDM for next generation wireless LAN. IEEE Trans. Consum. Electron. 2005, 51, 1134–1142. doi:10.1109/TCE.2005.1561835. 1465. Park, J.S.; Ogunfunmi, T. FPGA implementation of the MIMO-OFDM Physical Layer using single FFT multiplexing. In Proceedings of the International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS 2010), Paris, France, 30 May–2 June 2010. 1466. Pisek, E.; Abu-Surra, S.; Mott, J.; Henige, T.; Sharma, R. High Throughput Millimeter-Wave MIMO Beamforming System for Short Range Communication. In Proceedings of the IEEE 11th Consumer Communications and Networking Conference (CCNC), Las Vegas, NV, USA, 10–13 January 2014. 1467. Kalaivani, D.; Karthikeyen, S. VLSI Implementation of Area-Efficient and Low Power OFDM Transmitter and Receiver. Indian J. Sci. Technol. 2015, 8. doi:10.17485/ijst/2015/v8i18/63062. 1468. Cho, I.; Shen, C.C.; Tachwali, Y.; Hsu, C.J.; Bhattacharyya, S.S. CONFIGURABLE, RESOURCE-OPTIMIZED FFT ARCHITECTURE FOR OFDM COMMUNICATION. In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Vancouver, BC, Canada, 26–31 May 2013. 1469. Suleiman, I. FPGA implementation of low power 64-point radix-4 FFT processor for OFDM system. In Proceedings of the 2005 1st International Conference on Computers, Communications and Signal Processing with Special Track on Biomedical Engineering, CCSP 2005, Kuala Lumpur, Malaysia, 14–16 November 2005. doi:10.1109/CCSP.2005.4977206. 1470. Chefi, A.; Soudani, A.; Sicard, G. Hardware compression scheme based on low complexity arithmetic encoding for low power image transmission over WSNs. AEU-Int. J. Electron. Commun. 2014, 68, 193–200. doi:10.1016/j.aeue.2013.08.006. 1471. Glaser, J.; Damm, M.; Haase, J.; Grimm, C. TR-FSM: Transition-Based Reconfigurable Finite State Machine. ACM Trans. Reconfigurable Technol. Syst. 2011, 4. doi:10.1145/2000832.2000835. 1472. Kumar, C.R.; Ibrahim, A. VLSI design of energy efficient computational centric smart objects for IoT. In Proceedings of the 15th Learning and Technology Conference (L&T), Jeddah, Saudi Arabia, 25–26 February 2018. 1473. Li, S.; Luo, J.R.; Wu, Y.C.; Li, G.M.; Wang, F.; Wang, Y. Continuous and Real-Time Data Acquisition Embedded System for EAST. IEEE Trans. Nucl. Sci. 2010, 57, 696–699. doi:10.1109/TNS.2010.2041251. 1474. Naylor, G.A. An FPGA based control unit for synchronization of laser Thomson scattering measurements to plasma events on MAST. Fusion Eng. Des. 2010, 85, 280–285. doi:10.1016/j.fusengdes.2010.04.042. 1475. Pereira, R.C.; Fernandes, A.M.; Neto, A.C.; Sousa, J.; Batista, A.J.; Carvalho, B.B.; Correia, C.M.B.A.; Varandas, C.A.F. ATCA Fast Data Acquisition and Processing System for JET Gamma-Ray Cameras Upgrade Diagnostic. IEEE Trans. Nucl. Sci. 2010, 57, 683–687. doi:10.1109/TNS.2009.2035913. 1476. Rosas Velasquez, D.; Tomanguilla Collazos, V.; Machuca Mines, J. A Low-Cost Hardware-In-The-Loop Real Time Simulation of Control Systems. In Proceedings of the IEEE 24th International Conference on Electronics, Electrical Engineering and Computing (INTERCON), Cusco, Peru, 15–18 August 2017. Computation 2019, xx, 5 105 of 115 1477. Mou, X.; Zhang, G.; Hu, R. A design of real-time scene-based nonuniformity correction system. In Proceedings of the MIPPR 2009 - Multispectral Image Acquisition and Processing: 6th International Symposium on Multispectral Image Processing and Pattern Recognition, Yichang, China, 30 October–1 November 2009. doi:10.1117/12.833899. 1478. Chen, A.T.Y.; Biglari-Abhari, M.; Wang, K.I.K.; Bouzerdoum, A.; Tivive, F.H.C. Hardware/Software Co-design for a Gender Recognition Embedded System. In Proceedings of the 29th International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems (IEA/AIE), Morioka, Japan, 2–4 August 2016. doi:10.1007/978-3-319-42007-3_47. 1479. Chen, A.T.Y.; Biglari-Abhari, M.; Wang, K.I.K.; Bouzerdoum, A.; Tivive, F.H.C. Convolutional neural network acceleration with hardware/software co-design. Appl. Intell. 2018, 48, 1288–1301. doi:10.1007/s10489-017-1007-z. 1480. Tyson, E.J.; Buckley, J.; Franklin, M.A.; Chamberlain, R.D. Acceleration of atmospheric Cherenkov telescope signal processing to real-time speed with the Auto-Pipe design system. Nucl. Instruments Methods Phys. Res. Sect. -Accel. Spectrometers Detect. Assoc. Equip. 2008, 595, 474–479. doi:10.1016/j.nima.2008.06.047. 1481. Zhao, F.; Zhang, L.; Zhang, Z.Y.; Lu, H.Z. A hardware acceleration based algorithm for real-time binary image connected-component labeling. Dianzi Yu Xinxi Xuebao/J. Electron. Inf. Technol. 2011, 33, 1069–1075. doi:10.3724/SP.J.1146.2010.00793. 1482. Purde, A.; Meixner, A.; Schweizer, H.; Zeh, T.; Koch, A. Pixel shader based real-time image processing for surface metrology. In Proceedings of the Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference, IMTC/04, Como, Italy, 18–20 May 2004. doi:10.1109/IMTC.2004.1351259. 1483. Feng, W.; Lin, Y.; He, D.; Song, L.; Zhao, M. Dual-channel image real-time processing system based on FPGA. Chin. J. Sens. Actuators 2010, 23, 1118–1122. doi:10.3969/j.issn.1004-1699.2010.08.015. 1484. AlAli, M.I.; Mhaidat, K.M.; Aljarrah, I.A. Implementing Image Processing Algorithms in FPGA Hardware. In Proceedings of the IEEE Jordan Conference on Applied Electrical Engineering and Computing Technologies (AEECT), Univ Jordan, Fac Engn & Technol, Amman, Jordan, 3–5 December 2013. 1485. Mertes, J.; Marranghello, N.; Pereira, A. Real-time module for digital image processing developed on a FPGA. In Proceedings of the 12th IFAC Conference on Programmable Devices and Embedded Systems, PDeS 2013, Velke Karlovice, Czech Republic, 25–27 September 2013. doi:10.3182/20130925-3-CZ-3023.00072. 1486. Farhat, W.; Faiedh, H.; Souani, C.; Besbes, K. Real-time embedded system for traffic sign recognition based on ZedBoard. J. -Real-Time Image Process. 2017, pp. 1–11. doi:10.1007/s11554-017-0689-0. 1487. Schumacher, F.; Greiner, T. Two stage Real-Time Stereo Correspondence Algorithm and FPGA Architecture using a Modified Generalized Hough Transform. In Proceedings of the 21st International Conference on Systems, Signals and Image Processing (IWSSIP), Dubrovnik, Croatia, 12–14 May 2014. 1488. Lopez-Ongil, C.; Garcia-Valderas, M.; Portela-Garcia, M.; Entrena, L. Autonomous fault emulation: A new FPGA-based acceleration system for hardness evaluation. IEEE Trans. Nucl. Sci. 2007, 54, 252–261. doi:10.1109/TNS.2006.889115. 1489. Velazco, R.; Foucard, G.; Peronnard, P. Combining Results of Accelerated Radiation Tests and Fault Injections to Predict the Error Rate of an Application Implemented in SRAM-Based FPGAs. IEEE Trans. Nucl. Sci. 2010, 57, 3500–3505. doi:10.1109/TNS.2010.2087355. 1490. Velazco, R.; Foucard, G.; Pancher, F.; Mansour, W.; Marques-Costa, G.; Sohier, D.; Bui, A. Robustness with respect to SEUs of a self-converging algorithm. In Proceedings of the 12th IEEE Latin-American Test Workshop, LATW 2011, Porto de Galinhas, Brazil, 27–30 March 2011. doi:10.1109/LATW.2011.5985916. 1491. Villata, I.; Bidarte, U.; Kretzschmar, U.; Astarloa, A.; Lazaro, J. Fast and accurate SEU-tolerance characterization method for Zynq SoCs. Institute of Electrical and Electronics Engineers Inc., 2014. In Proceedings of the 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 2–4 September 2014. doi:10.1109/FPL.2014.6927416. 1492. Montenegro, S.; Haririan, E. A Fault-Tolerant Middleware Switch for Space Applications. In Proceedings of the 3rd IEEE International Conference on Space Mission Challenges for Information Technology, Pasadena, CA, USA, 19–23 July 2009. doi:10.1109/SMC-IT.2009.46. 1493. Costinett, D.; Rodriguez, M.; Maksimovic, D. Simple Digital Pulse Width Modulator with 60 Picoseconds Resolution Using a Low-cost FPGA. In Proceedings of the 15th International Power Electronics and Motion Control Conference and Exposition (EPE-PEMC ECCE Europe), Novi Sad, Serbia, 4–6 September 2012. Computation 2019, xx, 5 106 of 115 1494. Milivojevic, N.; Krishnamurthy, M.; Gurkaynak, Y.; Sathyan, A.; Lee, Y.J.; Emadi, A. Stability Analysis of FPGA-Based Control of Brushless DC Motors and Generators Using Digital PWM Technique. IEEE Trans. Ind. Electron. 2012, 59, 343–351. doi:10.1109/TIE.2011.2146220. 1495. Jamro, M.; Rzonca, D.; Sadolewski, J.; Stec, A.; Swider, Z.; Trybus, B.; Trybus, L. CPDev Engineering Environment for Modeling, Implementation, Testing, and Visualization of Control Software. In Proceedings of the International Conference on Automation, Warsaw, Poland, 26–28 March 2014. doi:10.1007/978-3-319-05353-0_9. 1496. Buttari, A.; Dongarra, J.; Kurzak, J.; Luszczek, P.; Tomov, S. Using mixed precision for sparse matrix computations to enhance the performance while achieving 64-bit accuracy. ACM Trans. Math. Softw. 2008, 34. doi:10.1145/1377596.1377597. 1497. Curreri, J.; Koehler, S.; George, A.D.; Holland, B.; Garcia, R. Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing. ACM Trans. Math. Softw. 2010, 3. doi:10.1145/1661438.1661443. 1498. Kao, C.C. Performance-Oriented Partitioning for Task Scheduling of Parallel Reconfigurable Architectures. IEEE Trans. Parallel Distrib. Syst. 2015, 26, 858–867. doi:10.1109/TPDS.2014.2312924. 1499. Kung, Y.S.; Tsai, M.H. FPGA-based speed control IC for PMSM drive with adaptive fuzzy control. IEEE Trans. Power Electron. 2007, 22, 2476–2486. doi:10.1109/TPEL.2007.909185. 1500. Huang, C.H.; Wang, W.J.; Chiu, C.H. Design and Implementation of Fuzzy Control on a Two-Wheel Inverted Pendulum. IEEE Trans. Ind. Electron. 2011, 58, 2988–3001. doi:10.1109/TIE.2010.2069076. 1501. Sanchez-Solano, S.; Cabrera, A.J.; Baturone, I.; Moreno-Velo, F.J.; Brox, M. FPGA implementation of embedded fuzzy controllers for robotic applications. IEEE Trans. Ind. Electron. 2007, 54, 1937–1945. doi:10.1109/TIE.2007.898292. 1502. Kim, D. An implementation of fuzzy logic controller on the reconfigurable FPGA system. IEEE Trans. Ind. Electron. 2000, 47, 703–715. doi:10.1109/41.847911. 1503. Chan, Y.; Moallem, M.; Wang, W. Efficient implementation of PID control algorithm using FPGA technology. In Proceedings of the 43rd IEEE Conference on Decision and Control, Nassau, Bahamas, 14–17 December 2004. doi:10.1109/CDC.2004.1429572. 1504. Chen, Y.; Wu, Q. Design and implementation of PID controller based on FPGA and genetic algorithm. In Proceedings of the 2011 International Conference on Electronics and Optoelectronics, ICEOE 2011, Dalian, China, 29–31 July 2011. doi:10.1109/ICEOE.2011.6013491. 1505. Yang, N.; Li, D.; Zhang, J.; Xi, Y. Model predictive controller design and implementation on FPGA with application to motor servo system. Control. Eng. Pract. 2012, 20, 1229–1235. doi:10.1016/j.conengprac.2012.06.012. 1506. Hsu, C.F.; Lee, B.K. FPGA-based adaptive PID control of a DC motor driver via sliding-mode approach. Expert Syst. Appl. 2011, 38, 11866–11872. doi:10.1016/j.eswa.2011.02.185. 1507. Wlas, M.; Krzeminski, Z.; Guzinski, J.; Abu-Rub, H.; Toliyat, H. Artificial-neural-network-based sensorless nonlinear control of induction motors. IEEE Trans. Energy Convers. 2005, 20, 520–528. doi:10.1109/TEC.2005.847984. 1508. Teja, A.V.R.; Verma, V.; Chakraborty, C. A New Formulation of Reactive-Power-Based Model Reference Adaptive System for Sensorless Induction Motor Drive. IEEE Trans. Ind. Electron. 2015, 62, 6797–6808. doi:10.1109/TIE.2015.2432105. 1509. Chen, H.C.; Liao, J.Y. Design and Implementation of Sensorless Capacitor Voltage Balancing Control for Three-Level Boosting PFC. IEEE Trans. Power Electron. 2014, 29, 3808–3817. doi:10.1109/TPEL.2013.2279718. 1510. Vyncke, T.; Thielemans, S.; Dierickx, T.; Dewitte, R.; Jacxsens, M.; Melkebeek, J. Design choices for the prediction and optimization stage of finite-set model based predictive control. In Proceedings of the 2011 1st Workshop on Predictive Control of Electrical Drives and Power Electronics, PRECEDE 2011, Munich, Germany, 14 –15 October 2011. doi:10.1109/PRECEDE.2011.6078687. 1511. Ouhrouche, M. Speed Sensorless Stator Flux Oriented Control of an Induction Motor Drive. In Proceedings of the IEEE International Conference on Industrial Technology, Churchill, Australia, 10–13 February 2009. 1512. Narjess, S.; Ramzi, T.; Faouzi, M. Implementation of sensorless control of an induction motor on FPGA using Xilinx system generator. J. Theor. Appl. Inf. Technol. 2016, 92, 322–334. 1513. Jezernik, K.; Korelic, J.; Horvat, R. PMSM Sliding Mode FPGA-Based Control for Torque Ripple Reduction. IEEE Trans. Power Electron. 2013, 28, 3549–3556. doi:10.1109/TPEL.2012.2222675. Computation 2019, xx, 5 107 of 115 1514. Morales-Caporal, R.; Bonilla-Huerta, E.; Hernandez, C.; Arjona, M.A.; Pacas, M. Transducerless Acquisition of the Rotor Position for Predictive Torque Controlled PM Synchronous Machines Based on a DSP-FPGA Digital System. IEEE Trans. Ind. Informatics 2013, 9, 799–807. doi:10.1109/TII.2012.2225633. 1515. Lin, C.M.; Hsu, C.F.; Yeh, R.G. Adaptive fuzzy sliding-mode control system design for brushless DC motors. Int. J. Innov. Comput. Inf. Control 2013, 9, 1259–1270. 1516. Hsu, C.F.; Hsu, C.Y.; Lin, C.M.; Chung, C.M. FPGA-implemented adaptive RCMAC design for BLDC motors. In Proceedings of the 12th WSEAS International Conference on SYSTEMS, Heraklion, Greece, 22–24 July 2008. 1517. Rajan, A.; Vasantharathna, S. Experimental investigation on fuzzy-based dynamic PWM controller using FPGA for harmonics and torque ripple minimisation in BLDC motor drive. International Journal of Information and Communication Technology 2015, 7, 366–384. doi:10.1504/IJICT.2015.070298. 1518. Iqbal, A.; Alammari, R.; Mosa, M.; Abu-Rub, H. Finite Set Model Predictive Current Control with Reduced and Constant Common Mode Voltage for a Five-phase Voltage Source Inverter. In Proceedings of the IEEE 23rd International Symposium on Industrial Electronics (ISIE), Istanbul, Turkey, 1–4 June 2014. 1519. Wang, J.; Binder, A. Current Slope Calculation in FPGA for Sensorless Control Technique and Associated Slope Based Predictive Precise Current Control; IEEE: 8, 2013. In Proceedings of the IEEE International Symposium on Sensorless Control for Electrical Drives and Predictive Control of Electrical Drives and Power Electronics (SLED/PRECEDE), Munich, Germany, 17–19 October 2013. 1520. Zhu, W.H.; Lamarche, T.; Dupuis, E.; Jameux, D.; Barnard, P.; Liu, G. Precision Control of Modular Robot Manipulators: The VDC Approach With Embedded FPGA. IEEE Trans. Robot. 2013, 29, 1162–1179. doi:10.1109/TRO.2013.2265631. 1521. Sahoo, S.; Prakash, S.; Mishra, S. Power Quality Improvement of Grid-Connected DC Microgrids Using Repetitive Learning-Based PLL Under Abnormal Grid Conditions. IEEE Trans. Ind. Appl. 2018, 54, 82–90. doi:10.1109/TIA.2017.2756866. 1522. Hwu, K.; Tau, Y. A forward converter having an FPGA-based PID controller with parameters on-line tuned. In Proceedings of the Sixth International Conference on Power Electronics and Drive Systems, PEDS 2005, Kualu Lumpur, Malaysia, 28 November–1 December 2005. 1523. Martin Sanchez, P.; Machado, O.; Bueno Pena, E.J.; Rodriguez, F.J.; Javier Meca, F. FPGA-Based Implementation of a Predictive Current Controller for Power Converters. IEEE Trans. Ind. Informatics 2013, 9, 1312–1321. doi:10.1109/TII.2012.2232300. 1524. Meinl, F.; Stolz, M.; Kunert, M.; Blume, H. An Experimental High Performance Radar System for Highly Automated Driving. In Proceedings of the IEEE MTT-S International Conference on Microwaves for Intelligent Mobility (ICMIM), Nagoya, Japan, 19–21 March 2017. 1525. Correia, M.; Batista, A.; Combo, A.; Cruz, N.; Carvalho, P.; Correia, C.; Sousa, J.; Varandas, C. A low-cost galvanic isolated fast PCI transient recorder with signal processing capabilities. Fusion Eng. Des. 2004, 71, 159–165. doi:10.1016/j.fusengdes.2004.04.028. 1526. Zhang, F.; Wu, Q.Z.; Ren, G.Q. A real-time capture and transport system for high-resolution measure image. In Proceedings of the 2010 International Conference on Intelligent Computation Technology and Automation, ICICTA 2010, Changsha, China, 11 –12 May 2010. doi:10.1109/ICICTA.2010.87. 1527. Wang, H.; Weng, Z.; Li, Y. Design of high-speed image acquisition system based on FPGA. In Proceedings of the 30th Chinese Control and Decision Conference, CCDC 2018, Shenyang, China, 9–11 June 2018. doi:10.1109/CCDC.2018.8407580. 1528. Cao, X.; Zhang, J.; Yao, W.; Ju, M. High-speed and portable data acquisition system based on FPGA. In Proceedings of the 5th International Conference on Intelligent Networks and Intelligent Systems, ICINIS 2012, Tianjin, China, 1–3 November 2012. doi:10.1109/ICINIS.2012.26. 1529. Sreevalsa, U.; Jyothilekshmi, P.; Pradeepkumar, P. FPGA based data acquisition and control system for Doppler SODAR receiver. Int. J. Appl. Eng. Res. 2015, 10, 638–641. 1530. Xu, Z.; Zhang, X.; Chen, Y. A high-speed image acquisition system for USB2.0. 2012, pp. 1867–1872. In Proceedings of the 2012 7th IEEE Conference on Industrial Electronics and Applications, ICIEA 2012, Singapore, Singapore, 18–20 July 2012. doi:10.1109/ICIEA.2012.6361032. 1531. Xu, Z.; Zhu, L.; Shan, J.F.; Tang, Y.Y.; Tang, J. A New High-Speed Data Acquisition System. J. Fusion Energy 2015, 34, 642–645. doi:10.1007/s10894-015-9845-3. Computation 2019, xx, 5 108 of 115 1532. Dubois, J.; Ginhac, D.; Paindavoine, M.; Heyrman, B. A 10 000 fps CMOS sensor with massively parallel image processing. IEEE J.-Solid-State Circuits 2008, 43, 706–717. doi:10.1109/JSSC.2007.916618. 1533. Qu, H.S.; Zhang, Y.; Jin, G. Improvement of performance for CMOS area image Sensors by TDI algorithm in digital domain. Guangxue Jingmi Gongcheng/Opt. Precis. Eng. 2010, 18, 1896–1903. doi:10.3788/OPE.20101808.1896. 1534. Yan, B.; Sun, Y.; Ding, F.; Yuan, H. Design of CMOS Image Acquisition System Based on FPGA. In Proceedings of the 6th IEEE Conference on Industrial Electronics and Applications (ICIEA), Beijing, China, 21–23 June 2011. 1535. Abbas, S.; Praba, R.; Thiruvengadam, S. PCFICH channel design for LTE using FPGA. In Proceedings of the International Conference on Recent Trends in Information Technology, ICRTIT 2011, Chennai, India, 3–5 June 2011. doi:10.1109/ICRTIT.2011.5972414. 1536. Yang, X.; Huang, Z.; Han, B.; Zhang, S.; Wen, C.K.; Gao, F.; Jin, S. RaPro: A Novel 5G Rapid Prototyping System Architecture. IEEE Wirel. Commun. Lett. 2017, 6, 362–365. doi:10.1109/LWC.2017.2692780. 1537. Timoshenko, A.G.; Bakhtin, A.A.; Osipenko, N.K.; Volkova, E.A. 5G Communication Systems Signal Processing PAPR Reduction Technique. In Proceedings of the Systems of Signal Synchronization, Generating and Processing in Telecommunications (SYNCHROINFO), Belarusian State Acad Commun, Minsk, Belarus, 4–5 July 2018. 1538. Song, H.; Lockwood, J. Efficient packet classification for network intrusion detection using FPGA. In Proceedings of the ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005, Monterey, CA, USA, 20 –22 February 2005. 1539. Kennedy, A.; Wang, X.; Liu, Z.; Liu, B. Low power architecture for high speed packet classification. In Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS ’08, San Jose, CA, USA, 6–7 November 2008. doi:10.1145/1477942.1477967. 1540. Ganegedara, T.; Jiang, W.; Prasanna, V.K. A Scalable and Modular Architecture for High-Performance Packet Classification. IEEE Trans. Parallel Distrib. Syst. 2014, 25, 1135–1144. doi:10.1109/TPDS.2013.261. 1541. Maheshwarappa, M.R.; Bridges, C.P. Software Defined Radios for Small Satellites; IEEE: 8, 2014; pp. 172–179. In Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Univ Leicester, Leicester, UK, 14–17 July 2014. 1542. Lotze, J.; Fahmy, S.; Noguera, J.; Doyle, L.; Esser, R. An FPGA-based cognitive radio framework. In Proceedings of the IET Irish Signals and Systems Conference, ISSC 2008, Galway, Ireland, 18–19 June 2008. doi:10.1049/cp:20080652. 1543. Dai, M.; Cheng, G.; Wang, Y. Detecting network topology and packet trajectory with SDN-enabled FPGA Platform. In Proceedings of the 11th International Conference on Future Internet Technologies, CFI 2016, Nanjing, China, 15–17 June 2016. doi:10.1145/2935663.2935670. 1544. Kalyaev, A.; Melnik, E. FPGA-based approach for organization of SDN switch. In Proceedings of the 9th International Conference of Information and Communiation Technologies (AICT), Rostov-on-Don, Russia, 14–16 October 2015. 1545. Papamichael, M.K.; Hoe, J.C. CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of FPGAs. In Proceedings of the 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, USA, 22–24 February 2012. 1546. Morgan, F.; Cawley, S.; Mc, G.B.; Pande, S.; Mc, D.L.; Glackin, B.; Maher, J.; Harkin, J. Exploring the evolution of NoC-based spiking Neural Netw. on FPGAs. In Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT’09, Sydney, 9–11 December 2009. doi:10.1109/FPT.2009.5377663. 1547. Wang, C.; Zhang, J.; Zhou, X.; Feng, X.; Wang, A. A flexible high speed star network based on peer to peer links on FPGA. In Proceedings of the 9th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2011, Busan, Korea, 26 –28 May 2011. doi:10.1109/ISPA.2011.40. 1548. Ahmad, R.; Sidek, O.; Mohd, S.K.K. Development of Bit-to-Chip Block for Zigbee Transmitter on FPGA. In Proceedings of the 2nd International Conference on Computer and Electrical Engineering, Dubai, United Arab Emirates , 28–30 December 2009. doi:10.1109/ICCEE.2009.110. 1549. Goy, C.; De, L.A.G.L.M.; Bolognini, P. ZigBee-based wireless transmissions interface incorporated to an FPGA embedded system. Int. J. Biomed. Eng. Technol. 2012, 10, 19–29. doi:10.1504/IJBET.2012.049322. 1550. Espinoza-Rhoton, A.; Gonzalez-Perez, L.F.; Ponce, J.L.; Borrayo-S, H.; C-Yllescas, L.; Parra-Michel, R.; Aboushady, H. An FPGA-based all-digital 802.11b & 802.15.4 receiver for the Software Defined Radio Computation 2019, xx, 5 109 of 115 Paradigm. In Proceedings of the 2014 International Conference on Reconfigurable Computing and FAGAs, Natl I Astrophysics Optics Elect (INAOE), Cancun, Mexico, 8–10 December 2014. 1551. Upadhyaya, B.; Misra, I.; Sanyal, S. Novel design of address generator for WiMAX multimode interleaver using FPGA based finite state machine. In Proceedings of the 2010 13th International Conference on Computer and Information Technology, ICCIT 2010, Dhaka, Bangladesh, 23–25 December 2010. doi:10.1109/ICCITECHN.2010.5723846. 1552. Rupanagudi, S.R.; Bhat, V.G.; Hemalatha, S.G.; Bhavana, N.; Archana, M.; Chandrika, B.V.; Ashwini, R.; Torvi, K.G.; Darshan, S.R.; Abhilash, B.G.; Anil, K.S.; Swamy, V.K.M. Design of a Low Power Digital Down Converter for 802.16m-4G WiMAX on FPGA. In Proceedings of the 3rd International Conference on Advances in Computing, Communications and Informatics (ICACCI), New Delhi, India, 24–27 September 2014. 1553. Lima, F.; Carro, L.; Reis, R. Designing fault tolerant systems into SRAM-based FPGAs. In Proceedings of the 40th Design Automation Conference, ANAHEIM, CA, USA, 2–6 June 2003. 1554. Ghazanfari, A.; Mohamed, Y.A.R.I. A Resilient Framework for Fault-Tolerant Operation of Modular Multilevel Converters. IEEE Trans. Ind. Electron. 2016, 63, 2669–2678. doi:10.1109/TIE.2016.2516968. 1555. Legat, U.; Biasizzo, A.; Novak, F. SEU Recovery Mechanism for SRAM-Based FPGAs. IEEE Trans. Nucl. Sci. 2012, 59, 2562–2571. doi:10.1109/TNS.2012.2211617. 1556. Bolchini, C.; Quarta, D.; Santambrogio, M.D. SEU Mitigation for SRAM-Based FPGAs through Dynamic Partial Reconfiguration. In Proceedings of the 17th Great Lakes Symposium on VLSI, Stresa, Italy, 11–13 March 2007. 1557. Suzuki, D.; Saeki, M.; Ichikawa, T. Random switching logic: A new countermeasure against DPA and second-order DPA at the logic level. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 2007, E90A, 160–168. doi:10.1093/ietfec/e90-a.1.160. 1558. Lumbiarres-Lopez, R.; Lopez-Garcia, M.; Canto-Navarro, E. Hardware Architecture Implemented on FPGA for Protecting Cryptographic Keys against Side-Channel Attacks. IEEE Trans. Dependable Secur. Comput. 2018, 15, 898–905. doi:10.1109/TDSC.2016.2610966. 1559. Narasimhan, S.; Du, D.; Subhra, C.R.; Paul, S.; Wolff, F.; Papachristou, C.; Roy, K.; Bhunia, S. Multiple-parameter side-channel analysis: A non-invasive hardware Trojan detection approach. In Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010, Anaheim, CA, USA, 13 –14 June 2010. doi:10.1109/HST.2010.5513122. 1560. Du, D.; Narasimhan, S.; Chakraborty, R.S.; Bhunia, S. Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection. In Proceedings of the 12th International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2010), Santa Barbara, CA, USA, 17–20 August 2010. 1561. Soell, O.; Korak, T.; Muehlberghuber, M.; Hutter, M. EM-Based Detection of Hardware Trojans on FPGAs. In Proceedings of the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), Arlington, VA, USA, 6–7 May 2014. 1562. Chen, Q.; Csaba, G.; Lugli, P.; Schlichtmann, U.; Ruhrmair, U. The bistable ring PUF: A new architecture for strong physical unclonable functions. In Proceedings of the 2011 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2011, San Diego, CA, USA, 5–6 June 2011. doi:10.1109/HST.2011.5955011. 1563. Zhang, J.L.; Qu, G.; Lv, Y.Q.; Zhou, Q. A Survey on Silicon PUFs and Recent Advances in Ring Oscillator PUFs. J. Comput. Sci. Technol. 2014, 29, 664–678. doi:10.1007/s11390-014-1458-1. 1564. Pratt, B.; Caffrey, M.; Graham, P.; Morgan, K.; Wirthlin, M. Improving FPGA design robustness with partial TMR. In Proceedings of the 44th Annual IEEE International Reliability Physics Symposium, San Jose, CA, USA, 26–30 March 2006. doi:10.1109/RELPHY.2006.251221. 1565. Ichinomiya, Y.; Tanoue, S.; Amagasaki, M.; Iida, M.; Kuga, M.; Sueyoshi, T. Improving the Robustness of a Softcore Processor against SEUs by using TMR and Partial Reconfiguration. In Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Charlotte, NC, USA, 2–4 May 2010. doi:10.1109/FCCM.2010.16. 1566. Ashraf, R.; Mouri, O.; Jadaa, R.; DeMara, R. Design-for-diversity for improved fault-tolerance of TMR systems on FPGAs. In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, 30 November –2 December 2011. doi:10.1109/ReConFig.2011.26. Computation 2019, xx, 5 110 of 115 1567. Hayes, C.; Luo, Y. DPICO: A high speed deep packet inspection engine using compact finite automata. In Proceedings of the 3rd ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS 2007, Orlando, FL, USA, 3 –4 December 2007. doi:10.1145/1323548.1323579. 1568. Fu, W.; Xin, X.; Guo, P.; Zhou, Z. A Practical Intrusion Detection System for Internet of Vehicles. China Commun. 2016, 13, 263–275. doi:10.1109/CC.2016.7733050. 1569. Wilson, L.N.; Radle, B.; Granieri, M.N. ATS Redundant design in support of system & mission sustainability. In Proceedings of the 48th Annual AUTOTESTCON Conference, Schaumburg, IL, USA, 16–19 September 2013. 1570. Siegle, F.; Vladimirova, T.; Ilstad, J.; Emam, O. Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications. ACM Comput. Surv. 2015, 47. doi:10.1145/2671181. 1571. Cheng, L.; Li, G.; Zhu, H.; Yang, L. LDPC Encoder Design and FPGA Implementation in Deep Space Communication. In Proceedings of the International Conference on Logistics Engineering, Management and Computer Science (LEMCS), Shenyang, China, 24–26 May 2014. 1572. Durai, S.; Parthasarathy, R. Medical data transmission through PLCC with QFT-PUF encoder for data authentication. Biomed.-Res.-India 2017, 28, S51–S58. 1573. Alkady, G.I.; Amer, H.H.; Daoud, R.M. Remotely Configurable Fault-Tolerant FPGA-based Pacemaker. In Proceedings of the 12th International Conference on Computer Engineering and Systems (ICCES), Cairo, Egypt, 19–20 December 2017. 1574. Rahimunnisa, K.; Karthigaikumar, P.; Rasheed, S.; Jayakumar, J.; SureshKumar, S. FPGA implementation of AES algorithm for high throughput using folded parallel architecture. Secur. Commun. Netw. 2014, 7, 2225–2236. doi:10.1002/sec.651. 1575. Rahimunnisa, K.; Karthigaikumar, P.; Christy, N.; Kumar, S.; Jayakumar, J. PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC. Open Comput. Sci. 2013, 3, 173–186. doi:10.2478/s13537-013-0112-2. 1576. Soltani, A.; Sharifian, S. An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA. Microprocess. Microsyst. 2015, 39, 480–493. doi:10.1016/j.micpro.2015.07.005. 1577. Yang, X.; Dai, Z.; Zhang, Y. Research and design of reconfigurable computing targeted at block cipher processing. Jisuanji Yanjiu Yu Fazhan/Comput. Res. Dev. 2009, 46, 962–967. 1578. Wei, L.; Xiaoyang, Z.; Longmei, N.; Tao, C.; Zibin, D. A Reconfigurable Block Cryptographic Processor Based on VLIW Architecture. China Commun. 2016, 13, 91–99. 1579. Li, R.; Dou, Y.; Zhou, J.; Lei, G. A high-throughput reconfigurable Viterbi decoder. In Proceedings of the 2011 International Conference on Wireless Communications and Signal Processing, WCSP 2011, Nanjing, China, 9–11 November 2011. doi:10.1109/WCSP.2011.6096781. 1580. Patel, P.; Parikh, C. Low power implementation of AES (Rijndael) algorithm. In Proceedings of the 22nd International Conference on Computers and Their Applications 2007, CATA 2007, Honolulu, HI, USA, 28–30 March 2007. 1581. Sakthivel, R.; Vanitha, M.; Kittur, H. Low power high throughput reconfigurable stream cipher hardware VLSI architectures. Int. J. Inf. Comput. Secur. 2014, 6, 1–11. doi:10.1504/IJICS.2014.059785. 1582. Ruiz-Llata, M.; Yebenes-Calvino, M. FPGA Implementation of Support Vector Machines for 3D Object Identification. In Proceedings of the 19th International Conference on Artificial Neural Netw. (ICANN 2009), Limmassol, Cyprus, 14–17 September 2009. 1583. Cho, J.; Benson, B.; Cheamanukul, S.; Kastner, R. Increased Performance of FPGA-Based Color Classification System. In Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Charlotte, NC, USA, 2–4 May 2010. doi:10.1109/FCCM.2010.50. 1584. Manikandan, J.; Venkataramani, B. System-on-programmable-chip implementation of diminishing learning based pattern recognition system. Int. J. Mach. Learn. Cybern. 2013, 4, 347–363. doi:10.1007/s13042-012-0102-z. 1585. Zhou, Y.; Chen, Z.; Huang, X. A System-On-Chip FPGA Design for Real-Time Traffic Signal Recognition System. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, Canada, 22–25 May 2016. 1586. Afifi, S.; GholamHosseini, H.; Sinha, R. A system on chip for melanoma detection using FPGA-based SVM classifier. Microprocess. Microsyst. 2019, 65, 57–68. doi:10.1016/j.micpro.2018.12.005. Computation 2019, xx, 5 111 of 115 1587. Afifi, S.; GholamHosseini, H.; Sinha, R. Dynamic hardware system for cascade SVM classification of melanoma. Neural Comput. Appl. 2018. doi:10.1007/s00521-018-3656-1. 1588. Pan, S.T.; Lan, M.L. An efficient hybrid learning algorithm for neural network-based speech recognition systems on FPGA chip. Neural Comput. Appl. 2014, 24, 1879–1885. doi:10.1007/s00521-013-1428-5. 1589. Sansaloni, T.; Perez-Pascual, A.; Torres, V.; Almenar, V.; Toledo, J.F.; Valls, J. FFT spectrum Analyzer project for teaching digital signal processing with FPGA devices. IEEE Trans. Educ. 2007, 50, 229–235. doi:10.1109/TE.2007.900025. 1590. Humphries, B.; Zhang, H.; Sheng, J.; Landaverde, R.; Herbordt, M.C. 3D FFTs on a Single FPGA. In Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines ((FCCM), Boston, MA, USA, 11–13 May 2014. doi:10.1109/FCCM.2014.28. 1591. Wang, B.; Zhang, Q.; Ao, T.; Huang, M. Design of pipelined FFT processor based on FPGA. In Proceedings of the 2010 International Conference on Computer Modeling and Simulation, ICCMS 2010, Sanya, China, 22–24 January 2010. doi:10.1109/ICCMS.2010.112. 1592. Alexandru, I.; Grama, A.; Viman, L.; Pitica, D. FFT Radix2 Core Implemented on FPGA with DSP48 Slices. In Proceedings of the 2018 IEEE 24th International Symposium for Design and Technology in Electronic Packaging, SIITME 2018, Iasi, Romania, 25–28 October 2018. doi:10.1109/SIITME.2018.8599234. 1593. Bruno, J.S.; Almenar, V.; Valls, J. FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems. Microprocess. Microsyst. 2019, 64, 195–204. doi:10.1016/j.micpro.2018.12.002. 1594. Huang, S.; Yang, T.; Huang, J. FPGA realization of wavelet transform for detection of electric power system disturbances. IEEE Trans. Power Deliv. 2002, 17, 388–394. doi:10.1109/61.997905. shuhua 1595. Panigrahy, P.S.; Konar, P.; Chattopadhyay, P. Broken Bar Fault Detection using Fused DWT-FFT in FPGA Platform. In Proceedings of the 3rd International Conference Control and Embedded Systems (ICPCES), Motilal Nehru Natl I Tech, Allahabad, India, 26–28 December 2014. 1596. Ong, J.J.; Ijemaru, G.; Ang, L.M.; Seng, K.P.; Kong, J.H.; Wong, Y.W. A low-complexity DWT module and CRS minimal instruction set computer architecture for wireless visual sensor networks. Int. J. Hoc Ubiquitous Comput. 2019, 30, 73–90. doi:10.1504/IJAHUC.2019.097628. 1597. Naik, P.; Guhilot, H.; Tigadi, A.; Ganesh, P. Reconfigured VLSI architecture for discrete wavelet transform. In Proceedings of the International Conference on Soft Computing and Signal Processing, ICSCSP 2018, Hyderabad, India, 22–23 June 2018. doi:10.1007/978-981-13-3393-4_72. 1598. Song, J.; An, Q.; Liu, S. A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays. IEEE Trans. Nucl. Sci. 2006, 53, 236–241. doi:10.1109/TNS.2006.869820. 1599. Wu, J.; Shi, Z. The 10-ps Wave Union TDC: Improving FPGA TDC Resolution beyond Its Cell Delay. In Proceedings of the IEEE Nuclear Science Symposium/Medical Imaging Conference, Dresden, Germany, 19–25 October 2008. 1600. Bayer, E.; Traxler, M. A High-Resolution (< 10 ps RMS) 48-Channel Time-to-Digital Converter (TDC) Implemented in a Field Programmable Gate Array (FPGA). IEEE Trans. Nucl. Sci. 2011, 58, 1547–1552. doi:10.1109/TNS.2011.2141684. 1601. Chen, Y.H. Run-time calibration scheme for the implementation of a robust field-programmable gate array-based time-to-digital converter. Int. J. Circuit Theory Appl. 2019, 47, 19–31. doi:10.1002/cta.2571. 1602. Lusardi, N.; Garzetti, F.; Geraci, A. The role of sub-interpolation for Delay-Line Time-to-Digital Converters in FPGA devices. Nucl. Instruments Methods Phys. Res. Sect. -Accel. Spectrometers Detect. Assoc. Equip. 2019, 916, 204–214. doi:10.1016/j.nima.2018.11.100. 1603. Huang, J.; Parris, M.; Lee, J.; Demara, R.F. Scalable FPGA-based Architecture for DCT Computation Using Dynamic Partial Reconfiguration. ACM Trans. Embed. Comput. Syst. 2009, 9. doi:10.1145/1596532.1596541. 1604. Zhao, B.J.; Shi, C.C.; Bi, L.; An, J.B.; Mao, E.K. Implementation of real-time 2D-DCT with FPGA and DSP. Tien Tzu Hsueh Pao/Acta Electron. Sin. 2003, 31, 1317–1319. 1605. Dong, X.; Li, J.; Liu, J.; Wu, J. A Novel FPGA Approach to DCT Based on the First-order Moments. In Proceedings of the 3rd International Conference on Instrumentation & Measurement, Computer, Communication and Control (IMCCC), Harbin Inst Technol, Shenyang, China, 21–23 September 2013. doi:10.1109/IMCCC.2013.201. 1606. Szadkowski, Z.; Fraenkel, E.D.; van den Berg, A.M. FPGA/NIOS Implementation of an Adaptive FIR Filter Using Linear Prediction to Reduce Narrow-Band RFI for Radio Detection of Cosmic Rays. IEEE Trans. Nucl. Sci. 2013, 60, 3483–3490. doi:10.1109/TNS.2013.2264726. Computation 2019, xx, 5 112 of 115 1607. Figuli, S.P.D.; Becker, J. An Efficient High-Throughput Generic QAM Transmitter with Scalable Spiral FIR Filter. J. Circuits Syst. Comput. 2019, 28. doi:10.1142/S0218126619500154. 1608. Sova, V.; Brablc, M.; Grepl, R. FPGA Implementation of Multiplierless Low-Pass FIR Differentiator. In Proceedings of the 18th International Conference on Mechatronics - Mechatronika, ME 2018, Brno, Czech Republic, 5–7 December 2018. 1609. Ramchandani, V.; Pamarthi, K.; Chowdhury, S. Comparative study of maximum power point tracking using linear kalman filter & unscented kalman filter for solar photovoltaic array on field programmable gate array. Int. J. Smart Sens. Intell. Syst. 2012, 5, 701–716. doi:10.21307/ijssis-2017-503. 1610. Wang, C.; Burnham-Fay, E.D.; Ellis, J.D. Real-time FPGA-based Kalman filter for constant and non-constant velocity periodic error correction. Precis. Eng. J. Int. Soc. Precis. Eng. Nanotechnol. 2017, 48, 133–143. doi:10.1016/j.precisioneng.2016.11.013. 1611. Fonseca, J.V.; Oliveira, R.C.L.; Abreu, J.A.P.; Ferreira, E.; Machado, M. Kalman Filter Embedded in FPGA to Improve Tracking Performance in Ballistic Rockets. In Proceedings of the UKSim-AMSS 15th International Conference on Computer Modelling and Simulation (UKSim), Emmanuel Coll, Cambridge, UK, 10–12 April 2013. doi:10.1109/UKSim.2013.149. 1612. Lee, T.; Lee, J.; Cho, S. FPGA implementation of a 3x3 window median filter based on a new efficient bit-serial sorting algorithm. In Proceedings of the 7th Korea/Russia International Symposium on Science and Technology (KORUS 2003), Ulsan, Korea, 28 June–6 July 2003. 1613. Lu, Y.; Jiang, L.; Dai, M.; Li, S. Sort optimization algorithm of median filtering based on FPGA. In Proceedings of the 2010 International Conference on Machine Vision and Human-Machine Interface, MVHI 2010, Kaifeng, China, 24–25 April 2010. doi:10.1109/MVHI.2010.145. 1614. Cai, G.; Liang, C.; Yang, J.; Li, H. Design and Implementation of LMS Adaptive Filter Algorithm Based on FPGA. In Proceedings of the 2nd International Symposium on Instrumentation and Measurement, Sensor Network and Automation (IMSNA), Toronto, ON, Canada, 23–24 December 2013. 1615. Nekouei, F.; Talebi, N.Z.; Kavian, Y.S.; Mahani, A. FPGA Implementation of LMS Self Correcting Adaptive Filter (SCAF) and Hardware Analysis. In Proceedings of the 8th International Symposium on Communication Systems, Networks & Digital Signal Processing (CSNDSP), Poznan, Poland, 18–20 July 2012. 1616. Sanchez, G.; Diaz, C.; Avalos, J.G.; Garcia, L.; Vazquez, A.; Toscano, K.; Sanchez, J.C.; Perez, H. A highly scalable parallel spike-based digital neuromorphic architecture for high-order fir filters using LMS adaptive algorithm. Neurocomputing 2019, 330, 425–436. doi:10.1016/j.neucom.2018.10.029. 1617. Zhang, L.; Zhang, K.; Chang, T.S.; Lafruit, G.; Kuzmanov, G.; Verkest, D. Real-Time High-Definition Stereo Matching on FPGA. In Proceedings of the 19th Annual ACM International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, 27 February–1 March 2011. 1618. Zicari, P.; Perri, S.; Corsonello, P.; Cocorullo, G. Low-cost FPGA stereo vision system for real time disparity maps calculation. Microprocess. Microsyst. 2012, 36, 281–288. doi:10.1016/j.micpro.2012.02.014. 1619. Perri, S.; Frustaci, F.; Spagnolo, F.; Corsonello, P. Design of Real-Time FPGA-based Embedded System for Stereo Vision. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 27–30 May 2018. 1620. Hsu, Y.P.; Miao, H.C.; Tsai, C.C. FPGA implementation of a real-time image tracking system. In Proceedings of the SICE Annual Conference 2010, Taipei, Taiwan, 18–21 August 2010. 1621. Chen, W.; Ma, Y.; Chai, Z.; Chen, M.; He, D. An FPGA-based real-time moving object tracking approach. In Proceedings of the 17th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2017, Helsinki, Finland, 21 –23 August 2017. doi:10.1007/978-3-319-65482-9_5. 1622. Mohanty, S.P. A secure digital camera architecture for integrated real-time digital rights management. J. Syst. Archit. 2009, 55, 468–480. doi:10.1016/j.sysarc.2009.09.005. 1623. Joshi, A.; Darji, A.; Mishra, V. Design and implementation of real-time image watermarking. In Proceedings of the 2011 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2011, Xi’an, China, 14 –16 September 2011. doi:10.1109/ICSPCC.2011.6061762. 1624. Xiao, J.; Li, S.; Sun, B. A Real-Time System for Lane Detection Based on FPGA and DSP. Sens. Imaging 2016, 17. doi:10.1007/s11220-016-0133-8. Computation 2019, xx, 5 113 of 115 1625. Khongprasongsiri, C.; Kumhom, P.; Suwansantisuk, W.; Chotikawanid, T.; Chumpol, S.; Ikura, M. A Hardware Implementation for Real-Time Lane Detection using High-Level Synthesis. In Proceedings of the International Workshop on Advanced Image Technology (IWAIT), Chiang Mai, Thailand, 7–9 January 2018. 1626. Zha, D.; Jin, X.; Xiang, T. A real-time global stereo-matching on FPGA. Microprocess. Microsyst. 2016, 47, 419–428. doi:10.1016/j.micpro.2016.08.005. 1627. Gehrig, S.; Schneider, N.; Franke, U. Exploiting traffic scene disparity statistics for stereo vision. In Proceedings of the 2014 IEEE Conference on Computer Vision and Pattern Recognition Workshops, CVPRW 2014, Columbus, OH, USA, 23–28 June 2014. doi:10.1109/CVPRW.2014.105. 1628. Jin, J.; Kim, D.; Song, J.H.; Nguyen, V.D.; Jeon, J.W. Hardware Architecture Design for Vehicle Detection Using a Stereo Camera. In Proceedings of the 11th International Conference on Control, Automation and Systems (ICCAS)/Robot World Conference, Korea, 26–29 October 2011. 1629. Moni, R.; Bako, L.; Hajdu, S.; Morgan, F.; Brassai, S.T. Embedded real-time implementation of a computational efficient optical flow extraction method for intelligent robot control applications.. In Proceedings of the 24th Irish Conference on Artificial Intelligence and Cognitive Science, AICS 2016, Dublin, Ireland, 20–21 September 2016. 1630. Czyszczon, T.; Czernikowski, R.; Shaaban, M.; Hsu, K. Real-time implementation of JPEG encoder/decoder. In Proceedings of the Conference on Input/Output and Imaging Technologies, Taipei, Taiwan, 9–11 July 1998. doi:10.1117/12.311097. 1631. Hamzaoglu, I.; Tasdizen, O.; Sahin, E. An Efficient H.264 Intra Frame Coder System. IEEE Trans. Consum. Electron. 2008, 54, 1903–1911. doi:10.1109/TCE.2008.4711252. 1632. Kalali, E.; Adibelli, Y.; Hamzaoglu, I. A high performance and low energy intra prediction hardware for HEVC video decoding. In Proceedings of the 6th Annual Conference on Design and Architectures for Signal and Image Processing, DASIP 2012, Karlsruhe, Germany, 23–25 October 2012. 1633. Amish, F.; Bourennane, E.B. Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction. J. Syst. Archit. 2016, 64, 133–147. doi:10.1016/j.sysarc.2015.10.002. 1634. Osorio, R.R.; Bruguera, J.D. High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard. J. Signal Process. Syst. Signal Image Video Technol. 2013, 72, 119–132. doi:10.1007/s11265-012-0718-y. 1635. Sateesh, S.; Sakthivel, R.; Nirosha, K.; Kittur, H. An optimized architecture to perform image compression and encryption simultaneously using modified DCT algorithm. In Proceedings of the 2011 - International Conference on Signal Processing, Communication, Computing and Networking Technologies, ICSCCN-2011, Thuckalay, India, 21–22 July 2011. doi:10.1109/ICSCCN.2011.6024591. 1636. Mukherjee, R.; Chakrabarti, I.; Sengupta, S. Fpga based architectural implementation of context-based adaptive variable length coding (CAVLC) for H.264/AVC. In Proceedings of the IET International Conference on Information Science and Control Engineering 2012, ICISCE 2012, Shenzhen, China, 7 –9 December 2012. doi:10.1049/cp.2012.2417. 1637. Chu, X.; Wu, S.; Chang, F.; He, W. Efficient implementation of the CAVLC Entropy encoder based on FPGA. Xi’an Dianzi Keji Daxue Xuebao/J. Xidian Univ. 2012, 39, 100–105. doi:10.3969/j.issn.1001-2400.2012.03.016. 1638. Guo, H.; Fu, Y.q. An improved CAVLC Entropy encoder of H.264/AVC and FPGA implementation. In Proceedings of the International Conference on Advanced Materials and Computer Science, Chengdu, China, 1–2 May 2011. doi:10.4028/www.scientific.net/KEM.474-476.241. 1639. Babionitakis, K.; Doumenis, G.; Georgakarakos, G.; Lentaris, G.; Nakos, K.; Reisis, D.; Sifnaios, I.; Vlassopoulos, N. A real-time H.264/AVC VLSI encoder architecture. J.-Real-Time Image Process. 2008, 3, 43–59. doi:10.1007/s11554-007-0054-9. 1640. Urban, F.; Poullaouec, R.; Nezan, J.F.; Deforges, O. A Flexible Heterogeneous Hardware/Software Solution for Real-Time HD H.264 Motion Estimation. IEEE Trans. Circuits Syst. Video Technol. 2008, 18, 1781–1785. doi:10.1109/TCSVT.2008.2004927. 1641. Cabarat, P.L.; Hamidouche, W.; Deforges, O. Real-time and parallel shvc hybrid codec avc to hevc decoder. In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), New Orleans, LA, USA, 5–9 March 2017. 1642. Kalali, E.; Adibelli, Y.; Hamzaoglu, I. A low energy intra prediction hardware for high efficiency video coding. J. Real-Time Image Process. 2018, 15, 221–234. doi:10.1007/s11554-014-0471-5. Computation 2019, xx, 5 114 of 115 1643. Neshatpour, K.; Malik, M.; Homayoun, H. Accelerating machine learning kernel in hadoop using FPGAs. In Proceedings of the 15th IEEE/ACM International Symposium on Cluster, Cloud, and Grid Computing, CCGrid 2015, Shenzhen, China, 4–7 May 2015. doi:10.1109/CCGrid.2015.165. 1644. Kachris, C.; Stamelos, I.; Koromilas, E.; Soudris, D. Seamless FPGA deployment over spark in cloud computing: A use case on machine learning hardware acceleration. In Proceedings of the 14th International Symposium on Applied Reconfigurable Computing, ARC 2018, Santorini, Greece, 2–4 May 2018. doi:10.1007/978-3-319-78890-6_54. 1645. Valls, J.; Kuhlmann, M.; Parhi, K. Evaluation of CORDIC algorithms for FPGA design. J. Vlsi Signal Process. Syst. Signal Image Video Technol. 2002, 32, 207–222. doi:10.1023/A:1020205217934. 1646. Liu, Y.; Fan, L.; Ma, T. A Modified CORDIC FPGA Implementation for Wave Generation. Circuits Syst. Signal Process. 2014, 33, 321–329. doi:10.1007/s00034-013-9638-8. 1647. Renardy, A.P.; Ahmadi, N.; Fadila, A.A.; Shidqi, N.; Adiono, T. FPGA Implementation of CORDIC Algorithms for Sine and Cosine Generator. In Proceedings of the 5th International Conference on Electrical Engineering and Informatics, Legian-Bali, Indonesia, 10–11 August 2015. 1648. Underwood, K. FPGAs vs. CPUs: Trends in peak floating-point performance. 2004, Vol. 12, pp. 171–180. In Proceedings of the ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays - FPGA 2004, Monterey, CA, USA, 22–24 February 2004. 1649. Ho, C.H.; Yu, C.W.; Leong, P.; Luk, W.; Wilton, S.J.E. Floating-Point FPGA: Architecture and Modeling. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2009, 17, 1709–1718. doi:10.1109/TVLSI.2008.2006616. 1650. Meher, P.K.; Chandrasekaran, S.; Amira, A. FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic. IEEE Trans. Signal Process. 2008, 56, 3009–3017. doi:10.1109/TSP.2007.914926. 1651. Xie, J.; He, J.; Tan, G. FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures. Microelectron. J. 2010, 41, 365–370. doi:10.1016/j.mejo.2010.04.006. 1652. Koutroulis, E.; Dollas, A.; Kalaitzakis, K. High-frequency pulse width modulation implementation using FPGA and CPLD ICs. J. Syst. Archit. 2006, 52, 332–344. doi:10.1016/j.sysarc.2005.09.001. 1653. de Oliveira, F.H.; de Freitas, I.S.; Cardoso, R.d.B.; Gomes, Z.M. Carrier-based pwm technique applied to single-phase asymmetric npc inverters with three levels on input and seven on output, using fpga. In Proceedings of the 14th Brazilian Power Electronics Conference (COBEP), Juiz de Fora, Brazil, 19–22 November 2017. 1654. Sutter, G.; Todorovich, E.; Lopez-Buedo, S.; Boemo, E. Low-power FSMs in FPGA: Encoding alternatives. In Proceedings of the 12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002, Seville, Spain, 11–13 September 2002. 1655. Liang, W.; Sun, X.; Ruan, Z.; Long, J. The design and FPGA implementation of FSM-based intellectual property watermark algorithm at behavioral level. Inf. Technol. J. 2011, 10, 870–876. doi:10.3923/itj.2011.870.876. 1656. Kasik, V.; Jahan, I.S.; Kurecka, A. FPGA Based Digital Logic Emulator for Educational Purposes. In Proceedings of the International Conference on Software and Computer Applications (ICSCA 2011), Kathmandu, Nepal, 1–2 July 2011. 1657. Cordone, R.; Redaelli, F.; Redaelli, M.A.; Santambrogio, M.D.; Sciuto, D. Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs. IEEE Trans. Comput-Aided Des. Integr. Circuits Syst. 2009, 28, 662–675. doi:10.1109/TCAD.2009.2015739. 1658. Yuan, M.; Gu, Z.; He, X.; Liu, X.; Jiang, L. Hardware/Software Partitioning and Pipelined Scheduling on Runtime Reconfigurable FPGAs. ACM Trans. Des. Autom. Electron. Syst. 2010, 15. doi:10.1145/1698759.1698763. 1659. Jing, C.; Zhu, Y.; Li, M. Energy-efficient scheduling on multi-FPGA reconfigurable systems. Microprocess. Microsyst. 2013, 37, 590–600. doi:10.1016/j.micpro.2013.05.001. 1660. Choudhary, P.S.; Ali, M.S. FPGA-Based Adaptive Task Scheduler for Real Time Embedded Systems. In Proceedings of the 3rd IEEE International Conference on Research in Intelligent and Computing in Engineering (RICE), Univ Don Bosco, San Salvador, El Salvador, 22–24 August 2018. 1661. Kumm, M.; Klingbeil, H.; Zipf, P. An FPGA-Based Linear All-Digital Phase-Locked Loop. IEEE Trans. Circuits Syst. -Regul. Pap. 2010, 57, 2487–2497. doi:10.1109/TCSI.2010.2046237. Computation 2019, xx, 5 115 of 115 1662. Deak, N.; Gyorfi, T.; Marton, K.; Vacariu, L.; Cret, O. Highly Efficient True Random Number Generator in FPGA Devices Using Phase-Locked Loops. In Proceedings of the 20th International Conference on System Controls and Computer Science 2015, Univ Politehnica Bucharest, Bucharest, Romania, 27–29 May 2015. 1663. Merli, D.; Stumpf, F.; Eckert, C. Improving the quality of Ring Oscillator PUFs on FPGAs. In Proceedings of the 5th Workshop on Embedded Systems Security, WESS ’10, Scottsdale, AZ, USA, 24 October 2010. doi:10.1145/1873548.1873557. 1664. Li, F.; Lin, Y.; He, L. FPGA power reduction using configurable dual-Vdd. In Proceedings of the 41st Design Automation Conference, San Diego, CA, USA, 7–11 June 2004. 1665. Pandit, S.; Sikka, P. DESIGN AND IMPLEMENTATION OF POWER OPTIMIZED DUAL CORE AND SINGLE CORE DLX PROCESSOR ON FPGA. In Proceedings of the 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), IISC, Bengaluru, India, 10–12 July 2018. 1666. Sun, Y.; Li, L.; Luo, H. Design of FPGA-based Multimedia Node for WSN; IEEE: 5, 2011. In Proceedings of the 7th International Conference on Wireless Communications, Networking and Mobile Computing (WiCOM), Wuhan, China, 23–25 September 2011. 1667. Patil, V.S.; Mane, Y.B.; Deshpande, S. FPGA Based Power Saving Technique for Sensor Node in Wireless Sensor Network (WSN). Comput. Intell. Sens. Netw. 2019, 776, 385–404. doi:10.1007/978-3-662-57277-1_16. 1668. Linares-Barranco, A.; Liu, H.; Rios-Navarro, A.; Gomez-Rodriguez, F.; Moeys, D.P.; Delbruck, T. Approaching Retinal Ganglion Cell Modeling and FPGA Implementation for Robotics. Entropy 2018, 20. doi:10.3390/e20060475. 1669. Cerezo, J.; Morales, E.; Plaza, J. Control system in open-source FPGA for a self-balancing robot. Electronics (Switzerland) 2019, 8. doi:10.3390/electronics8020198. 1670. Grossi, G.; Pedersini, F. FPGA implementation of a stochastic neural network for monotonic pseudo-Boolean optimization. Neural Netw. 2008, 21, 872–879. doi:10.1016/j.neunet.2008.06.018. 1671. Ruiz, A.P.; Cirstea, M.; Koczara, W.; Teodorescu, R. A novel integrated renewable energy system modelling approach, allowing fast FPGA controller prototyping. In Proceedings of the 11th International Conference on Optimization of Electrical and Electronic Equipment, Brasov, Romania, 22–23 May 2008. 1672. Johnson, A.P.; Chakraborty, R.S.; Mukhopadhyay, D. A PUF-Enabled Secure Architecture for FPGA-Based IoT Applications. IEEE Trans.-Multi-Scale Comput. Syst. 2015, 1, 110–122. doi:10.1109/TMSCS.2015.2494014. 1673. Nunez, J.; Jones, S. Gbit/s lossless data compression hardware. EEE Trans. Very Large Scale Integr. (VLSI) Syst. 2003, 11, 499–510. doi:10.1109/TVLSI.2003.812288. 1674. Hemnath, P.; Prabhu, V. Compression of fpga bitstreams using improved rle algorithm. In Proceedings of the International Conference on Information Communication and Embedded Systems (ICICES), Chennai, India, 21–22 February 2013. 1675. Hameed, M.; Shakor, H.; Razak, I. Low power text compression for Huffman coding using Altera FPGA with power management controller. In Proceedings of the 1st International Scientific Conference of Engineering Sciences - 3rd Scientific Conference of Engineering Science, ISCES 2018, Diyala, Iraq, 10–11 January 2018. doi:10.1109/ISCES.2018.8340521. c 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).