Dates are inconsistent

Dates are inconsistent

258 results sorted by ID

2026/1615 (PDF) Last updated: 2026-08-05
KORD: Breaking the Key-Generation Bottleneck in Dealerless Function Secret Sharing via Protocol–Hardware Co-Design
Yijing Peng, Lin Liu, Yujie Xue, Shaojing Fu, Shaoqing Li, Yaohua Wang, Rongmao Chen, Yang Guo
Cryptographic protocols

Function secret sharing (FSS) has become a core primitive in privacy‑preserving computation. However, each FSS invocation requires a fresh pair of function keys, typically produced by a trusted dealer—a dependency that expands the system's trust boundary and hinders practical deployment. Existing dealerless protocols eliminate this dependency, but incur substantial communication and a number of interaction rounds that grows linearly with the input bit‑width, making key generation a major...

2026/1576 (PDF) Last updated: 2026-08-05
A Systematic Literature Review on Optimising CRYSTALS-Dilithium (ML-DSA) Performance for IoT Devices via Lightweight Hashing
Ceasar Njuguna Ngunu, Edward Ombui
Implementation

Background: The migration to post-quantum cryptography confronts resource-constrained Internet of Things (IoT) devices with a material performance cost. CRYSTALS-Dilithium, standardised as the Module-Lattice-Based Digital Signature Algorithm (ML-DSA) in FIPS 204, fixes the Keccak-based SHAKE functions as its only symmetric primitives, and profiling on embedded platforms identifies hashing as the largest single contributor to the scheme’s software cost. This review synthesises the performance...

2026/1485 (PDF) Last updated: 2026-07-20
From PQC to HHE: Reusing a Co-Design Platform for Side-Channel-Protected PASTA
Ahmet Malal, Tolun Tosun, Oğuz Yayla, Erkay Savas
Implementation

Hybrid homomorphic encryption (HHE) lets a constrained client send compact symmetric ciphertexts while a server transciphers them into homomorphic ciphertexts, making HE-friendly ciphers such as PASTA a practical choice. Efficient and side-channel-secure execution of PASTA on embedded devices, however, remains challenging, since existing hardware relies on dedicated cipher cores and provides no side-channel protection. We present a hardware/software co-design of PASTA on RISQrypt, an...

2026/1483 (PDF) Last updated: 2026-07-20
MQ on my Hardware: Performance Analysis of MQOM on FPGA
Stelios Manasidis, Quinten Norga, Suparna Kundu, Ingrid Verbauwhede
Implementation

Recent algorithmic advancements in the Multi-Party Computation-in-the-Head (MPCitH) paradigm have resulted in more efficient post-quantum digital signature schemes. MQOM is a MPCitH-based digital signature scheme and candidate in the ongoing NIST Post-Quantum Cryptography (PQC) standardization effort, offering performance competitive with lattice- and multivariate-based schemes in software. In this work, we develop a dedicated hardware accelerator for MQOM and analyze the impact of recent...

2026/1469 (PDF) Last updated: 2026-07-23
MULTILINEAR POLYNOMIALS VIA TREE-BASED CIRCUIT AND THE SUMCHECK PROTOCOL
ALI MKHIDA, Adil Iguider
Cryptographic protocols

The Sumcheck protocol is a cornerstone of modern proof systems, yet its prover remains a performance bottleneck. Even in the multilinear case, the repeated construction of round polynomials leads to significant overhead, limiting scalability in practice. We take a different approach: instead of modifying the protocol, we rethink the representation of multilinear polynomials. We show that any multilinear polynomial admits a simple and structured binary-tree circuit representation, where...

2026/1466 (PDF) Last updated: 2026-07-17
Scalable High-Throughput FPGA Architecture for SMAC Message Authentication Code
Ahmet MALAL, Hakan Güler, Bahadır Aydoğan, Oğuz Yayla
Implementation

SMAC is a recently proposed by Wang et al.~stand-alone Message Authentication Code (MAC) constructed from repeated applications of the AES round function and featuring an aggregation mode, SMAC-1$\times n$, for scalable parallel processing. Although originally designed for high-throughput CPU implementations leveraging AES-NI instructions, its structural properties suggest strong compatibility with hardware parallelism. However, no systematic FPGA-oriented architectural study of SMAC has...

2026/1458 (PDF) Last updated: 2026-07-17
A High-Speed Hardware Accelerator for QR-UOV Signature Scheme
Renma Sugai, Hiroshi Amagasa, Rei Ueno, Naofumi Homma
Implementation

This paper proposes a high-speed hardware accelerator for QR-UOV, a multivariate scheme, that executes all three operations: key generation, signature generation, and signature verification. QR-UOV utilizes a quotient polynomial ring structure to reduce the public-key size of the original UOV scheme; however, this introduces functional requirements distinct from other multivariate schemes, such as polynomial-matrix operations over $\mathbb{F}_{q^\ell}$, coefficient expansion for the...

2026/1451 (PDF) Last updated: 2026-07-16
Lightweight Hardware Accelerator for the UOV Signature Scheme with Oil Space Blinding
Florian Krieger, Maciej Czuprynko, Sujoy Sinha Roy
Implementation

In reaction to the emerging quantum threat, the National Institute of Standards and Technology (NIST) seeks post-quantum secure digital signature schemes. NIST's ongoing competition recently advanced to the third round, in which the Unbalanced Oil and Vinegar scheme (UOV) is a promising candidate due to UOV's conservative design, small signatures, and performant signing and verification. While these benefits make UOV attractive, the implementation aspects for compact hardware acceleration of...

2026/1441 (PDF) Last updated: 2026-07-15
RainHash2.0: Hardware- and Arithmetization-friendly Hash Function
Jiamin Cui, Lorenzo Grassi, Katharina Koschatko, Florian Krieger, Shibam Mukherjee, Christian Rechberger, Sujoy Sinha Roy, Markus Schofnegger, Verena Schröppel
Secret-key cryptography

Zero-knowledge (ZK) proof systems have developed rapidly in recent years, with hash functions as one of their central building blocks. Since these often dominate the prover cost, circuit-friendly hash function design has become an active research area. Most hash proposals target prime fields, although recent protocols such as Binius and VOLE-based ZK operate natively over binary extension fields \(\mathbb{F}_{2^n}\). These binary field protocols reduce the cost of proving widely used binary...

2026/1423 (PDF) Last updated: 2026-07-12
CMALU: Compact Fault-Tolerant Modular Arithmetic Logic Unit for Post-Quantum Cryptography
YoungBeom Kim, Malik Imran, Zain Ul Abideen, Ciara Rafferty, Ayesha Khalid, Máire O’Neill, Seog Chung Seo
Implementation

The rise of quantum computing threatens widely deployed public-key cryptosystems, driving the adoption of post-quantum cryptography (PQC) algorithms that rely heavily on modular arithmetic. Existing hardware accelerators of the PQC algorithms for resource-constrained Internet-of-Things (IoT) devices remain limited and lack integrated fault detection mechanisms. In this work, we present CMALU, a Compact, fault-tolerant Modular Arithmetic Logic Unit supporting six operations on a single...

2026/1324 (PDF) Last updated: 2026-06-26
Efficient Parallelization of Large-Scale Modular Multiplication via Low-Latency LogJumps
Selim Kırbıyık, Maciej Czuprynko, Florian Krieger, Florian Hirner, Sujoy Sinha Roy
Implementation

Elliptic-Curve Cryptography (ECC) found in Zero-Knowledge Proofs (ZKPs) protects assets worth more than a billion dollars on privacy-preserving blockchain networks. There, the transaction rate is mostly limited by the computational cost of Multi-Scalar Multiplications (MSMs). Thus, hardware acceleration of these operations, for instance, using FPGAs, is of interest. Current accelerators leverage the Pippenger algorithm to compute the MSMs. Due to data dependencies, the algorithm’s...

2026/1279 (PDF) Last updated: 2026-06-18
BootNet: Homomorphic CNN Inference with Convolution and ReLU Fused in Bootstrapping
Zhaomin Yang, Chao Niu, Cheng Hong, Tao Wei
Applications

Fully homomorphic encryption (FHE) enables privacy-preserving neural network inference but suffers from high overhead from homomorphic convolutions, polynomial activation approximations, and CKKS bootstrapping. This paper presents BootNet, a unified framework that fuses all three operations into a single bootstrapping invocation per CNN layer, achieving convolution, ReLU, and noise refresh simultaneously. Prior works are able to fuse convolution into bootstrapping using CinS encoding...

2026/1274 (PDF) Last updated: 2026-06-17
Design and Performance Evaluation of Post-Quantum Authentication for Embedded Systems: A Case Study on PIV
Emmanuelle Dottax, Rina Zeitoun
Applications

As the transition to post-quantum cryptography accelerates, security protocols must evolve to resist quantum threats while remaining practical, particularly on constrained devices where memory, bandwidth, and performance are limited. We consider the NIST Personal Identity Verification (PIV) system, where smart cards rely on digital signatures for authentication. Since post-quantum signatures introduce substantial computational and memory overhead, whereas post-quantum Key Encapsulation...

2026/1250 (PDF) Last updated: 2026-06-16
TensorZKP: Repurposing GPU Tensor Cores for High-Performance Zero-Knowledge Proofs
Tao Lu, Jipeng Zhang, Yanpei Guo, Xuanming Liu, Wenjie Qu, Zonghui Wang, Wenzhi Chen, Jiaheng Zhang
Implementation

GPU Tensor Cores, specialized hardware units designed to accelerate matrix multiplication, have served as the primary engine behind the AI revolution. Given the exponential performance gains they have delivered, aligning cryptographic implementations with this hardware evolution is critical. This is particularly acute for zero-knowledge proofs (ZKPs), a cryptographic primitive that currently grapples with high proof generation costs. Existing GPU implementations for ZKPs rely exclusively on...

2026/1181 (PDF) Last updated: 2026-06-10
AICE: An Arithmetic-Oriented Stream Cipher for Heterogeneous Computing
Bishwajit Chakraborty, Jiahui Gao, Kai Hu, Tao Huang, Zhongfeng Niu, Phuong Pham, Shuzhou Sun, Meiqin Wang, Shuang Wu, Wenhan Xu, Guang Zeng, Chenxu Zhao
Secret-key cryptography

Heterogeneous computing platforms increasingly rely on high-throughput data paths spanning CPUs and accelerators, yet most high-speed software ciphers are optimized primarily for CPU-centric execution models. We present AICE, an arithmetic-oriented stream cipher over \(\mathbb{Z}/2^{16}\mathbb{Z}\) with a 37-word (592-bit) internal state, a nonlinear feedback combining modular addition, multiplication, bitwise OR, and rotation, a 370-round initialization with post-initialization key...

2026/1115 (PDF) Last updated: 2026-05-31
The Fact of the MATTER: Efficient Hardware Accelerators for Wide-Block Memory Encryption
Shubham Namdeo Shende, Utsav Banerjee
Implementation

Tweakable block ciphers are important cryptographic primitives for secure memory encryption and partial mitigation of bit flip attacks. Rapid advancements in data-intensive applications such as artificial intelligence and machine learning have motivated the development of new memory technologies with very large data bus widths requiring wide-block memory encryption and its efficient implementation. Recently, the MATTER family of wide-block tweakable ciphers has been proposed for memory...

2026/1082 (PDF) Last updated: 2026-05-28
Compact Yet Fast: An Efficient d-Order Masked Implementation of Ascon
Mattia Mirigaldi, Maurizio Martina, Guido Masera
Implementation

In this work, we present a generic side-channel protected design of Ascon that achieves high efficiency by dynamically reconfiguring the hardware countermeasures during message processing. The resultant implementation is protected and capable of meeting stringent performance requirements whilst minimising resource overhead. The experimental results obtained demonstrate that the implementation meets the required security and achieves superior throughput-to-area ratio across all protection...

2026/1078 (PDF) Last updated: 2026-05-28
Post-Quantum HAWK Signature Acceleration with RISC-V-Based Hardware-Software Co-Design
Rishabh Shrivastava, Utsav Banerjee
Implementation

Advances in quantum computing technology have motivated the development of post-quantum cryptography (PQC) algorithms. HAWK is a new post-quantum digital signature scheme and the only lattice-based candidate selected for Round 3 of the "Additional Digital Signatures" phase of the NIST PQC Standardization process. HAWK offers compact key and signature sizes compared to NIST standard ML-DSA (Dilithium), and its simple design avoids the use of floating-point arithmetic unlike NIST standard...

2026/935 (PDF) Last updated: 2026-06-03
SoK: Private LLM Inference using Approximate Homomorphic Encryption
Ahmad Al Badawi, Andreea Alexandru, Yuriy Polyakov, Vinod Vaikuntanathan
Applications

Although recent surveys on privacy-enhancing technologies concluded that FHE cannot feasibly evaluate non-linear activation functions in modern ML architectures, 20 CKKS-based frameworks have since demonstrated end-to-end private inference of LLMs with up to 8B parameters. However, as the field grows rapidly, the literature has become fragmented. Frameworks differ in ciphertext packing layouts, model fidelity, software and hardware stacks, and reported metrics, which hinder direct comparison...

2026/841 (PDF) Last updated: 2026-04-29
HAKE: Efficient Hardware Accelerator for Key Generation of Post-Quantum Signature Scheme PERK
Brendan Funk, Tianyou Bao, Loïc Bidoux, Jiafeng Xie
Implementation

The rapid progress in quantum computing has sparked a new wave of cryptosystem innovation, namely, the development of cryptographic schemes that are resistant to quantum attacks, known as Post-Quantum Cryptography (PQC). Notably, the National Institute of Standards and Technology (NIST) has already initiated the PQC standardization process with several algorithms selected. Meanwhile, an additional round of digital signature scheme competition is on-going. Following the standardization...

2026/837 (PDF) Last updated: 2026-04-28
Trident: Efficient FPGA Acceleration of XMSS Tree in Post-Quantum Signature Scheme SLH-DSA
Tianyou Bao, Joshua Ennis, Kirill Morozov, Jiafeng Xie
Implementation

The emergence of quantum computing poses significant threats to conventional cryptographic systems, necessitating the efficient hardware acceleration of Post-Quantum Cryptography (PQC), especially on the Field-Programmable Gate Array (FPGA) platforms. SPHINCS$^+$, recently standardized by NIST (National Institute of Standards and Technology) as SLH-DSA (Stateless Hash-Based Digital Signature Algorithm), represents the only hash-based digital signature scheme. Its practical deployment,...

2026/807 (PDF) Last updated: 2026-05-07
When Data Movement Becomes the Bottleneck in Modern Workloads: Compute-in-Transit as an Architectural Model
Flavio Bergamaschi
Implementation

In modern computing workloads, performance is increasingly constrained not by computation, but by the cost of moving data. This shift reflects both the scale and structure of contemporary applications, in which large data sets are subjected to repeated transformations across memory hierarchies, interconnects and distributed systems. A similar pattern appears across domains including fully homomorphic encryption, post-quantum cryptography and artificial intelligence: intermediate...

2026/764 (PDF) Last updated: 2026-04-18
CEDAR: A Compact and Efficient Decoder Architecture for RS-RM Code in HQC
Yazheng Tu, Tianyou Bao, Jiafeng Xie
Implementation

The rapid development of quantum computing has driven a new wave of cryptographic innovation: Post-Quantum Cryptography (PQC), a class of algorithms that resist quantum attacks. In particular, the National Institute of Standards and Technology (NIST) has initiated the PQC standardization process, selecting five algorithms. Notably, HQC (the newest selection) is a code-based PQC scheme that has not been widely studied in the literature, especially with respect to its hardware acceleration....

2026/763 (PDF) Last updated: 2026-04-18
LEAH: Lightweight and Efficient Hardware Accelerator for Code-based PQC Scheme HQC
Yazheng Tu, Jiafeng Xie
Implementation

The advent of quantum computing poses a significant threat to modern cryptography. To address this challenge, the National Institute of Standards and Technology (NIST) has initiated the Post-Quantum Cryptography (PQC) standardization process, with several algorithms being selected for standardization, including the recent code-based scheme HQC (Hamming Quasi-Cyclic). Meanwhile, a good number of research works in the field have switched to efficient hardware acceleration for PQC schemes....

2026/691 (PDF) Last updated: 2026-04-08
PipeSC: A Resource-efficient and Pipelined Hardware Accelerator for Sumcheck Protocol
Kaixuan Wang, Yifan Yanggong, Xiaoyu Yang, Chenti Baixiao, Lei Wang
Implementation

Zero-knowledge Succinct Non-interactive Arguments of Knowledge (zk-SNARKs) are cryptographic protocols that allow a prover to convince verifiers of the correctness of a statement without revealing any additional information. Recent zk-SNARK constructions have shifted from univariate to multivariate polynomial-based designs, reducing the proving complexity from quasilinear to linear by avoiding costly univariate polynomial interpolation. This shift, however, makes the sumcheck protocol—a...

2026/686 (PDF) Last updated: 2026-04-08
Secure MSM Outsourcing Computation for Zero-knowledge Proof Generation
Wujie Xiong, Arefeh Rahaei, Sangwon Shin, Xinxin Fan, Taeweon Suh, Veronika Kuchta, Sica Francesco, Weidong Shi, Lei Xu
Cryptographic protocols

Zero-knowledge proof (ZKP) schemes enable a prover to convince a verifier of the validity of a statement without revealing the underlying secret. These schemes have found extensive applications in secure communications, privacy-preserving transactions and blockchain technologies. However, the computational cost of proof generation remains a major obstacle to practical deployment. Although various acceleration techniques have been proposed, they often rely on specialized hardware that may not...

2026/556 (PDF) Last updated: 2026-06-16
TP-NTT: Batch NTT Hardware with Application to Relinearization
Emre Koçer, Tolun Tosun, Beren Aydoğan, Erkay Savaş, Furkan Turan, Ingrid Verbauwhede
Implementation

Fully Homomorphic Encryption (FHE) enables arbitrary computation on encrypted data without decryption, providing strong privacy guarantees for secure cloud computing, encrypted analytics, and privacy-preserving machine learning. However, practical deployment of FHE remains limited by the high computational cost of polynomial arithmetic over large modular rings. In particular, Number Theoretic Transform (NTT)–based polynomial multiplication dominates the execution time of modern lattice-based...

2026/521 (PDF) Last updated: 2026-03-14
UniMSM: An Efficient and Flexible Hardware Accelerator for Multi-Scalar Multiplication
Kaixuan Wang, Yifan Yanggong, Chenti Baixiao, Xiaoyu Yang, Lei Wang
Implementation

Multi-scalar multiplication (MSM) is a central kernel in cryptographic systems, which evaluates large linear combinations of elliptic-curve points. Practical MSMs couple millions of terms with hundreds-of-bit modular arithmetic, while Pippenger’s bucket flow introduces irregular memory updates that can severely degrade utilization under deep pipelines. In this paper, we present UniMSM, an efficient and flexible hardware accelerator for MSM across practical problem sizes and diverse...

2026/515 (PDF) Last updated: 2026-03-13
Privacy at your Fingertips: Enabling Rapid Client-Side Operations in Fully Homomorphic Encryption
Aikata Aikata, Florian Krieger, Sujoy Sinha Roy
Public-key cryptography

Fully Homomorphic Encryption (FHE) allows users to offload large computations to servers without revealing the underlying data. Due to this unique feature, it is applicable to a variety of domains, including privacy-preserving Machine Learning. However, all FHE schemes have two problems- slow encryption/decryption and substantial ciphertext expansion. Thus, despite its significant potential, the practical implementation of FHE faces considerable challenges due to massive computation and...

2026/499 (PDF) Last updated: 2026-03-11
Accelerating FAEST Signatures on ARM: NEON SIMD AES and Parallel VOLE Optimization
Seung-Won Lee, Ha-Gyeong Kim, Min-Ho Song, Si-Woo Eum, Hwa-Jeong Seo
Implementation

FAEST is a post-quantum digital signature candidate whose performance is dominated by repeated AES-CTR-based PRG calls in the VOLE-in-the-Head phase, yet its reference implementation provides no FAEST-specialized ARM NEON acceleration path. We present an ARM-oriented optimization that accelerates this bottleneck using general-purpose NEON SIMD instructions without relying on ARMv8 Crypto Extensions. The proposed implementation combines a register-resident 256-byte S-box with TBL/TBX-based...

2026/478 (PDF) Last updated: 2026-03-09
A Hardware/Software Co-Optimization of HQC Using Tightly-Coupled Accelerators on a 32-bit Ibex Core
Seog Chung Seo, YoungBeom Kim
Implementation

We present Hardware/Software co-optimization of Hamming Quasi-Cyclic (HQC) enabled by tightly coupled accelerators implemented on a 32-bit Ibex RISC-V core. On the hardware side, we propose a unified multiplier capable of efficiently performing carryless multiplication for both polynomial multiplication over F_2[X]/(X^{n}−1) and multiplication over F_2^{8}. We also design a Keccak permutation accelerator to support efficient randomness sampling. On the software side, we identify the optimal...

2026/460 (PDF) Last updated: 2026-03-05
A Resource-Efficient Hardware Accelerator for Large-Size NTT via Algorithm–Architecture Co-Design
Kaixuan Wang, Yifan Yanggong, Xiaoyu Yang, Chenti Baixiao, Lei Wang
Implementation

Large-size Number Theoretic Transforms (NTTs) are key operations in modern Zero-Knowledge Proofs (ZKPs), where the NTT size often reaches millions of points and the arithmetic is over wide prime fields. To handle such NTTs on hardware, prior designs commonly rely on the decomposition algorithm, which makes large-size NTTs feasible by streaming sub-NTTs through limited on-chip buffers. However, in practical implementations, decomposition alone is insufficient to ensure high efficiency. Since...

2026/456 (PDF) Last updated: 2026-03-08
Libra: Pattern-Scheduling Co-Optimization for Cross-Scheme FHE Code Generation over GPGPU
Song Bian, Yintai Sun, Zian Zhao, Haowen Pan, Mingzhe Zhang, Zhenyu Guan
Applications

We propose Libra, a compiler framework that automates efficient code generation for cross-scheme fully homomorphic encryption (FHE) on highly parallel computing architectures. While it is known that leveraging multiple FHE schemes in a single application can improve the overall efficiency, the exact mapping of cross-scheme FHE operators onto high-performance architectures, such as general-purpose graphic processing units (GPGPUs), remains challenging. To address such challenge, Libra...

2026/393 (PDF) Last updated: 2026-06-11
VROOM: Accelerating (Almost All) Number-Theoretic Cryptography Using Vectorization and the Residue Number System
Simon Langowski, Kaiwen He, Srinivas Devadas
Implementation

Modular arithmetic with a large prime modulus is a dominant computational cost in number-theoretic cryptography. Modular operations are especially challenging to parallelize efficiently on CPUs using vector instructions; standard CPU implementations rely on costly carry operations and permutation instructions to align with the multiplication datapath, negating the benefits of vectorization. We develop vectorized algorithms for modular addition and multiplication, and present a new,...

2026/362 (PDF) Last updated: 2026-07-30
Janus-FHE: Reducing Microarchitectural Leakage in GPU-Based Homomorphic Encryption
Kashfia Farheen, Nektarios Georgios Tsoutsos
Implementation

Homomorphic Encryption (HE) enables secure cloud computing through computations on encrypted data, but the physical execution of HE workloads on shared GPUs can still expose relevant metadata through microarchitectural behavior. Implementation-level irregularities in key switching, rounding, and modular correction may create observable hardware footprints even when cryptographic confidentiality remains intact. We present a case study of BFV relinearization in a state-of-the-art GPU HE...

2026/312 (PDF) Last updated: 2026-05-06
RISQrypt: Fast, Secure and Agile Hardware-Software Co-Design for Post-Quantum Cryptography
Tolun Tosun, Atıl Utku Ay, Quinten Norga, Suparna Kundu, Melik Yazıcı, Erkay Savaş, Ingrid Verbauwhede
Implementation

In this paper, we present RISQrypt, the first unified architecture in the literature that implements Kyber (ML-KEM) and Dilithium (ML-DSA), standardized lattice-based Post-Quantum Cryptography (PQC) algorithms, with masking. RISQrypt is a hardware–software co-design framework that integrates dedicated cryptographic accelerators to speed up polynomial arithmetic, hashing, and mask-conversion operations, the latter being one of the primary bottlenecks in masked implementations of lattice-based...

2026/256 (PDF) Last updated: 2026-02-13
Adams Bridge Accelerator: Bridging the Post-Quantum Transition
Mojtaba Bisheh-Niasar, Emre Karabulut, Kiran Upadhyayula, Michael Norris, Bharat Pillilli
Implementation

Quantum computing threatens widely deployed public-key cryptosystems, driving the urgent adoption of post-quantum cryptography (PQC) in cloud and hardware-accelerated security infrastructures. This paper presents Adams Bridge, an industry-grade hardware accelerator for lattice-based PQC that integrates ML-KEM and ML-DSA within a unified architecture to maximize hardware reuse and silicon efficiency. The design features a staged, pipelined datapath that exploits multi-level parallelism to...

2026/206 (PDF) Last updated: 2026-04-27
MPSpeed: Implementing and Optimizing MPC-in-the-Head Digital Signatures in Hardware
Stelios Manasidis, Quinten Norga, Suparna Kundu, Ingrid Verbauwhede
Implementation

The Multi-Party Computation (MPC)-in-the-Head (MPCitH) framework enables the construction of post-quantum Digital Signature Algorithms (DSAs), offering competitive public key sizes. However, this comes at a cost of high computational complexity, resulting in high signature generation and verification times. In this work, we propose a compact and efficient hardware accelerator for Mirath, an MPCitH-based DSA and candidate in the ongoing NIST PQC standardization effort. We propose a series...

2026/093 (PDF) Last updated: 2026-01-20
Optimized Implementation of ML-KEM on ARMv9-A with SVE2 and SME
Hanyu Wei, Wenqian Li, Shiyu Shen, Hao Yang, Yunlei Zhao
Implementation

As quantum computing continues to advance, traditional public-key cryptosystems face increasing vulnerability, necessitating a global transition toward post-quantum cryptography (PQC). A primary challenge for both cryptographers and system architects is the efficient integration of PQC into high-performance computing platforms. ARM, a dominant processor architecture, has recently introduced ARMv9-A to accelerate modern workloads such as artificial intelligence and cloud computing. Leveraging...

2026/014 (PDF) Last updated: 2026-01-05
Accelerating HQC with Additive FFT
Ming-Shing Chen, Chun-Ming Chiu, Chun-Tao Peng, Bo-Yin Yang
Implementation

This paper presents an accelerated implementation of the Hamming Quasi-Cyclic (HQC) key encapsulation mechanism by leveraging additive Fast Fourier Transform (FFT) for polynomial multiplication (polymuls). A common challenge when applying FFT-based polymuls to HQC are the polynomial degrees fractionally greater than powers of two, making standard FFT polymuls inefficient for those parameters. We introduce a novel combination of additive FFT with the Chinese Remainder Theorem (CRT) to...

2025/2277 (PDF) Last updated: 2025-12-18
Quantum Resource Analysis of Low-Round Keccak/SHA-3 Preimage Attack: From Classical 2^ 57.8 to Quantum 2 ^28.9 using Qiskit Modeling
Ramin Rezvani Gilkolaei, Reza Ebrahimi

This paper presents a hardware-conscious analysis of the quantum acceleration of the classical 3-round Keccak-256 preimage attack using Grover’s Algorithm. While the theo- retical quantum speed-up from T cl ≈ 2 ^57.8 (classical) to T qu ≈ 2 ^28.9 (quantum) is mathe- matically sound, the practical implementation overhead is so extreme that attacks remain wholly infeasible in both resource and runtime dimensions. Using Qiskit-based circuit synthesis, we derive that a 3-round Keccak...

2025/2269 (PDF) Last updated: 2026-04-09
Accelerating FrodoKEM in Hardware
Sanjay Deshpande, Patrick Longa, Jakub Szefer
Implementation

FrodoKEM, a conservative post-quantum key encapsulation mechanism based on the plain Learning with Errors (LWE) problem, has been recommended for use by several government cybersecurity agencies and is currently undergoing standardization by the International Organization for Standardization (ISO). Despite its robust security guarantees, FrodoKEM's performance remains one of the main challenges to its widespread adoption. This work addresses this concern by presenting a fully...

2025/2241 (PDF) Last updated: 2025-12-12
LEAF: Lightweight and Efficient Hardware Accelerator for Signature Verification of FALCON
Samuel Coulon, Jinjun Xiong, Jiafeng Xie
Implementation

Along with the National Institute of Standards and Technology (NIST) post-quantum cryptography (PQC) stan- dardization process, efficient hardware acceleration for PQC has become a priority. Among the NIST-selected PQC digital signature schemes, FALCON shows great promise due to its compact key sizes and efficient Signature Verification procedure. However, FALCON is regarded as highly computationally com- plex, and as a result, few works for hardware acceleration of FALCON can be...

2025/2238 Last updated: 2026-05-09
arya-STARK: Aggregation-Robust Yet Authentic Training via STARK Proofs
Abdoul Ahad FALL
Cryptographic protocols

We present arya-STARK, a unified post-quantum secure framework that enables Aggregation-Robust Yet Authentic training in Federated Learning through transparent zk-STARK proofs. Current federated learning deployments remain vulnerable to malicious or Byzantine clients capable of submitting statistically valid yet adversarial gradients, while also relying on quantum-fragile primitives for authentication. arya-STARK bridges these gaps by combining (i) transparent, hash-based zk-STARK proofs to...

2025/2193 (PDF) Last updated: 2025-12-03
aLEAKator: HDL Mixed-Domain Simulation for Masked Hardware & Software Formal Verification
Noé Amiot, Quentin Meunier, Karine Heydemann, Emmanuelle Encrenaz
Implementation

Verifying the security of masked hardware and software implementations, under advanced leakage models, remains a significant challenge, especially when accounting for glitches, transitions and CPU micro-architectural specifics. Existing verification approaches are either restricted to small hardware gadgets, small programs on CPUs such as Sboxes, limited leakage models, or require hardware-specific prior knowledge. In this work, we present aLEAKator, an open-source framework for the...

2025/2183 (PDF) Last updated: 2025-12-02
Hardware Implementation of Stealthy and Lightweight Backdoor for CRYSTALS-Kyber
Suraj Mandal, Prasanna Ravi, M Dhilipkumar, Debapriya Basu Roy, Anupam Chattopadhyay
Attacks and cryptanalysis

The threat of practical quantum attacks has catapulted viable alternatives like Post-Quantum Cryptography (PQC) into prominence. The adoption and integration of standardized PQC primitives across the entire digital stack are promoted by various standardization bodies, governments, and major corporate houses. A serious challenge in quantum migration is to ensure that there is no hidden backdoor in the PQC implementations of a hybrid cryptosystem (support for both pre-quantum and post-quantum...

2025/2171 (PDF) Last updated: 2025-11-29
Efficient GHASH and POLYVAL Implementation Using Polynomial Multiplication: Optimized 64-bit Decomposition with Bit-Reversal Elimination
Mamone Tarsha Kurdi, Niels Möller
Cryptographic protocols

We present an optimized implementation of the GHASH and POLYVAL authentication algorithms used in AES-GCM and AES-GCM-SIV that eliminates the computational overhead of bit-reversal operations. Our approach computes these universal hash functions directly in bit-reversed representation, matching the native format used by carry-less multiplication instructions available on modern processors. The algorithm exploits 64-bit polynomial primitives and parallel execution on superscalar...

2025/2165 (PDF) Last updated: 2025-11-28
Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension
Songqiao Cui, Geng Luo, Junhan Bao, Josep Balasch, Ingrid Verbauwhede
Implementation

Inner product masking is a well-studied masking countermeasure against side-channel attacks. IPM-FD further extends the IPM scheme with fault detection capabilities. However, implementing IPM-FD in software especially on embedded devices results in high computational overhead. Therefore, in this work we perform a detailed analysis of all building blocks for IPM-FD scheme and propose a Masked Processing Unit to accelerate all operations, for example multiplication and IPM-FD specific...

2025/2157 (PDF) Last updated: 2025-11-27
Taming the Stack: Proof-Preserving Blockwise FrodoKEM on RISC-V Devices with Hardware Acceleration
Frank Hartmann
Implementation

FrodoKEM provides conservative post-quantum security through unstructured lattices, yet its deployment on embedded systems is historically constrained by high memory requirements. While state-of-the-art implementations mitigate this by generating the public matrix on-the-fly, they remain bottlenecked by the sequential generation of secret matrices, which enforces a rigid trade-off between stack usage and recomputation overhead. To address this, we propose a blockwise secret generation...

2025/2143 (PDF) Last updated: 2026-07-13
New Post-Quantum IBE leveraging maturity, efficiency and security of standard schemes
Julien CAM
Public-key cryptography

Many Identity-Based Encryption (IBE) schemes rely on the hardness of the Discrete Logarithm Problem, making them vulnerable to quantum attacks. In recent years, lattice-based cryptography has emerged as a source of Post-Quantum cryptosystems, for example with Kyber, Dilithium and Falcon chosen by NIST to be standardized as ML-KEM, ML-DSA and FN-DSA. Some IBEs have also been proposed over lattices, but they can still be considered as interesting theoretical constructions, the community's...

2025/2003 (PDF) Last updated: 2025-10-27
A Sparse Polynomial Multiplier for HQC Integrating Parallelism and Power-Based Side-Channel Countermeasures
Jaeho Jeon, Suseong Lee, Myeongjun Kim, Eunyoung Seo, Myunghyun Cho, Seonggyeom Kim, Bo Gyeong Kang, Young-Sik Kim
Implementation

The Hamming Quasi-Cyclic (HQC) scheme has recently been standardized as a post-quantum key encapsulation mechanism (KEM), emphasizing the importance of efficient and secure hardware realizations on embedded platforms. However, HQC relies heavily on sparse–dense polynomial multiplications, where conventional shift-and-add architectures remain both performance- and security-critical. In FPGA implementations, these multiplications dominate execution time—occupying 59.5%, 56.1%, and 58.3% of the...

2025/1934 (PDF) Last updated: 2025-10-16
HORCRUX - A Lightweight PQC-RISC-V eXtension Architecture
Alessandra Dolmeta, Valeria Piscopo, Guido Masera, Maurizio Martina, Michael Hutter
Implementation

This work presents a RISC-V extension for Post-Quantum Cryptography (PQC) called HORCRUX, which provides a unified Instruction-Set Extension (ISE) supporting all NIST-approved PQC algorithms. HORCRUX addresses the current fragmentation in hardware support, where existing extensions typically focus on individual algorithms or limited subsets of PQC schemes, and targets the common kernels shared across ML-KEM, ML-DSA, SLH-DSA, and HQC. To address the primary computational bottlenecks of all...

2025/1763 (PDF) Last updated: 2025-09-26
A High Throughput Kyber NTT
Jonas Bertels, Ingrid Verbauwhede
Implementation

NIST recently selected Kyber as a standard for key encapsulation and decapsulation. As such, servers will soon need dedicated hardware for these encapsulation protocols. The computationally critical operation of Kyber is its Number Theoretic Transform, which is commonly accelerated by dedicated hardware such as FPGAs. This work presents an extremely high-throughput design for the Kyber NTT. By utilizing the LUT-based modular multiplication technique used by us in CHES 2025, its area delay...

2025/1754 (PDF) Last updated: 2025-09-25
Machine Learning and Side-Channel Attacks on Post-Quantum Cryptography
Abiodun Olaluwe, Nouf Nur Nabilah, Sheikh Tareq, Akshay Raghavendra Kulkarni, Annamalai Annamalai
Attacks and cryptanalysis

The transition to post-quantum cryptography (PQC) is accelerating due to the potential of quantum computing to compromise classical public-key cryptosystems. While standardized schemes such as CRYSTALS-Kyber, CRYSTALS-Dilithium, and SPHINCS+ offer strong theoretical security, practical deployments remain susceptible to physical-layer vulnerabilities, notably side-channel attacks (SCAs). SCAs exploit unintentional leakages in hardware and software implementations—such as power traces,...

2025/1728 (PDF) Last updated: 2025-09-22
Precision Strike: Targeted Misclassification of Accelerated CNNs with a Single Clock Glitch
Arsalan Ali Malik, Furkan Aydin, Aydin Aysu
Attacks and cryptanalysis

Fault injection attacks (FIAs) present a significant threat to the integrity of deep neural networks (DNNs), particularly in hardware-accelerated deployments on field-programmable gate arrays (FPGAs). These attacks intentionally introduce faults into the system, leading the DNN to generate incorrect outputs. This work presents the first successful targeted misclassification attack against a convolutional neural network (CNN) implemented on FPGA hardware, achieved by injecting a single clock...

2025/1599 (PDF) Last updated: 2026-04-27
AVX2 Implementation of QR-UOV for Modern x86 Processors
Hiroshi Amagasa, Rei Ueno, Naofumi Homma
Implementation

QR-UOV is a multivariate signature scheme selected as one of the candidates in the second round of the NIST PQC Additional Digital Signatures process. This paper presents software acceleration methods for QR-UOV optimized for modern x86 architectures. QR-UOV operates over small odd prime-power extension fields such as $\mathrm{GF}(31^3)$ and $\mathrm{GF}(127^3)$ unlike other multivariate cryptosystem candidates. This property allows direct utilization of hardware multipliers for field...

2025/1490 (PDF) Last updated: 2026-04-24
Accelerating FALCON: Speed Records for FALCON's SamplerZ on Xilinx FPGAs
Sharath Pendyala, Rahul Magesh, Elif Bilge Kavun, Aydin Aysu
Implementation

FALCON is a NIST-selected post-quantum digital signature scheme whose performance bottleneck lies in the SamplerZ subroutine for discrete Gaussian sampling. We present a throughput-optimized, custom hardware implementation of SamplerZ that introduces several architectural and algorithmic innovations to significantly accelerate signature generation. Our design incorporates a datapath-aware floating-point arithmetic pipeline that strategically balances latency and resource utilization. Our...

2025/1407 (PDF) Last updated: 2025-08-02
A Flexible Hardware Design Tool for Fast Fourier and Number-Theoretic Transformation Architectures
Florian Krieger, Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy
Implementation

Fully Homomorphic Encryption (FHE) and Post-Quantum Cryptography (PQC) involve polynomial multiplications, which are a common performance bottleneck. To resolve this bottleneck, polynomial multiplications are often accelerated in hardware using the Number-Theoretic Transformation (NTT) or the Fast Fourier Transformation (FFT). In particular, NTT operates over modular rings while FFT operates over complex numbers. NTT and FFT are widely deployed in applications with diverse parameter sets,...

2025/1312 (PDF) Last updated: 2025-07-17
Can FrodoKEM Run in a Millisecond? FPGA Says Yes!
Gökçe Düzyol, Muhammed Said Gündoğan, Atakan Arslan
Implementation

FrodoKEM is a post-quantum key encapsulation mechanism based on plain Learning With Errors (LWE). In contrast to module-lattice-based schemes, it relies on an unstructured variant of the LWE problem, providing more conservative and better-understood security guarantees. As a result, FrodoKEM has been recommended by European cybersecurity agencies such as BSI and ANSSI, and has also been proposed in international standardization efforts, including ISO and the IETF Internet-Draft...

2025/1162 Last updated: 2025-07-01
SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
Dipayan Saha, Shams Tarek, Hasan Al Shaikh, Khan Thamid Hasan, Pavan Sai Nalluri, Md. Ajoad Hasan, Nashmin Alam, Jingbo Zhou, Sujan Kumar Saha, Mark Tehranipoor, Farimah Farahmandi
Applications

Ensuring the security of complex system-on-chips (SoCs) designs is a critical imperative, yet traditional verification techniques struggle to keep pace due to significant challenges in automation, scalability, comprehensiveness, and adaptability. The advent of large language models (LLMs), with their remarkable capabilities in natural language understanding, code generation, and advanced reasoning, presents a new paradigm for tackling these issues. Moving beyond monolithic models, an agentic...

2025/1161 (PDF) Last updated: 2026-08-03
High-Performance FPGA Accelerator for the Post-quantum Signature Scheme CROSS
Patrick Karl, Francesco Antognazza, Alessandro Barenghi, Gerardo Pelosi, Georg Sigl
Implementation

In October 2024, the National Institute of Standards and Technology announced the second round candidates of its standardization effort for additional post-quantum signatures. One of these candidates is CROSS, a code-based scheme relying on the restricted syndrome decoding problem. In this work, we present the first hardware design of CROSS, delineating efficient implementation strategies for the critical components of the cryptographic scheme. Our architecture parallelizes rejection...

2025/1144 (PDF) Last updated: 2026-01-27
Parasol Compiler: Pushing the Boundaries of FHE Program Efficiency
Rick Weber, Ryan Orendorff, Ghada Almashaqbeh, Ravital Solomon
Applications

Fully Homomorphic Encryption (FHE) is a key technology to enable privacy-preserving computation. While optimized FHE implementations already exist, the inner workings of FHE are technically complex. This makes it challenging, especially for non-experts, to develop highly-efficient FHE programs that can exploit the advanced hardware of today. Although several compilers have emerged to help in this process, due to design choices, they are limited in terms of application support and the...

2025/1130 (PDF) Last updated: 2026-01-14
An Open-Source Framework for Efficient Side-Channel Analysis on Cryptographic Implementations
Takuya Kojima, Masaki Morita, Hideki Takase, Hiroshi Nakamura
Implementation

Side-channel attacks are increasingly recognized as a significant threat to hardware roots of trust. As a result, cryptographic module designers must ensure that their modules are resilient to such attacks before deployment. However, efficient evaluation of side-channel vulnerabilities in cryptographic implementations remains challenging. This paper introduces an open-source framework integrating FPGA designs, power measurement tools, and high-performance side-channel analysis libraries to...

2025/1068 (PDF) Last updated: 2025-06-06
Efficient Modular Multiplication Using Vector Instructions on Commodity Hardware
Simon Langowski, Srini Devadas
Foundations

Modular arithmetic is the computational backbone of many cryptographic and scientific algorithms. In particular, modular multiplication in a large prime field is computationally expensive and dictates the runtime of many algorithms. While it is relatively easy to utilize vectorization to accelerate batches of independent modular multiplications, our goal is to reduce the latency of a $\textit{single}$ modular multiplication under a generic prime using vectorization, while maintaining...

2025/1013 (PDF) Last updated: 2025-06-01
Silentium: Implementation of a Pseudorandom Correlation Generator for Beaver Triples
Vincent Rieder
Implementation

Secure Multi-Party Computation is a privacy-enhancing technology that allows several parties to securely compute on distributed private data. In the line of the well established SPDZ protocol, the by far most expensive task is the generation of Beaver triples in the so called offline phase. Silentium is our implementation of an actively secure offline phase in the form of a Pseudorandom Correlation Generator for Beaver triples (Bt-PCG, Boyle et al. CRYPTO 2020), which, as any PCG, is...

2025/812 (PDF) Last updated: 2025-05-12
Post-Quantum Cryptography in eMRTDs: Evaluating PAKE and PKI for Travel Documents
Nouri Alnahawi, Melissa Azouaoui, Joppe W. Bos, Gareth T. Davies, SeoJeong Moon, Christine van Vredendaal, Alexander Wiesmaier
Implementation

Passports, identity cards and travel visas are examples of machine readable travel documents (MRTDs) or eMRTDs for their electronic variants. The security of the data exchanged between these documents and a reader is secured with a standardized password authenticated key exchange (PAKE) protocol known as PACE. A new world-wide protocol migration is expected with the arrival of post-quantum cryptography (PQC) standards. In this paper, we focus on the impact of this migration on constrained...