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The CEO of SK Hynix rang the Nasdaq bell, then told the room the memory shortage will outlast 2030. That's one line from an episode of Silicon Bridge worth going back to. Art and Ashish on the squeeze, and on the three counteroffensives being funded against it. The warning SK Hynix debuted on the Nasdaq at $26.5 billion. In the same breath, CEO Kwak No-jung said 2027 will be the worst year in history for global memory supply. This is not a 2021-style logistics jam. It is a hard cap on what can physically be built. HBM demand from NVIDIA and AMD is pulling premium capacity away from standard DRAM, and by 2027 analysts expect roughly half of global DRAM output to be locked into multi-year contracts. Micron's Sanjay Mehrotra said the quiet part too: no clear line of sight on when supply catches demand. When the two largest memory makers both say they cannot build fabs fast enough, mid-size buyers are bidding for leftovers. Micron's answer $250 billion in US investment through 2035, up $50 billion from the prior commitment. First foundation concrete poured at Clay, New York, a full quarter ahead of schedule, which in this industry is the headline. Clay is projected to be the largest semiconductor site in US history: roughly $100 billion, up to four fabs, around 50,000 jobs, more than 90,000 nationwide across New York, Idaho and Virginia. The target is 40% of Micron's global DRAM output made in the US. Timelines matter here. Clay produces in 2030. Idaho's first fab starts wafers mid-2027, the second in late 2028. 2027 stays tight regardless. Bosch, Roseville Up to $225 million in CHIPS Act funding against up to $2 billion converting a 40-year-old California fab into a silicon carbide site. Bosch bought the asset in 2023 and retrained the existing workforce rather than building greenfield, which is why sample production has already started and 200mm commercial production lands later this year. Commerce estimates the site could eventually account for more than 40% of US silicon carbide capacity. Bosch's third-generation SiC delivers up to 20% higher performance in a smaller die. Europe's €659 million Germany got Commission approval for state aid across four first-of-a-kind facilities: €353 million to Element 3-5 for SiC epi wafers, €214 million to Vishay Siliconix for power MOSFETs at Itzehoe, plus KLA and KETEK for metrology and equipment. The uncomfortable part is the politics. These are jointly funded by Germany's federal and regional budgets. Subsidy-poor member states cannot match that, and the fear inside the EU is a single market splitting into tech hubs and left-behind regions. The pattern across all three: government backing is no longer optional if you want a seat at the table. Which do you think breaks first, memory supply or memory pricing? #Semiconductors #MemoryChips #CHIPSAct #SiliconCarbide #DRAM Micron Technology Bosch SEMI Episode in the comments.

Rapidus is trying to stand up a 2nm foundry by 2027. To get there, it has handed a large part of its design flow to an AI agent. This week on Silicon Bridge, Art and Ashish cover a week where the industry was firing on every cylinder. Cadence and Rapidus Cadence's InnoStack AI Super Agent is being integrated with Rapidus' RAADS agentic design solution. Not point-tool machine learning: the agent oversees the SoC workflow from architectural exploration through final signoff. Rapidus expects up to 50% lower design turnaround time. DAC 2026, Long Beach The 63rd Design Automation Conference ran July 26 to 29. AI, chiplets and cloud dominated. Marvell presented on verification for stacked 3D chiplet designs and automated 3Dblox generation for thermal analysis, which tracks with thermal and IR in 3D SOICs being the current bottleneck for physical design teams. The session worth arguing about: "Build vs Buy: Who Owns the Intelligence Behind Tomorrow's Chips?" South Korea June 2026 exports crossed $100 billion in a single month for the first time. Semiconductors were over 46% of total exports by May, after March chip exports surged more than 150% year-on-year to nearly $33 billion. The same number is the risk. When one sector is close to half your export economy, a downturn is not a dip. Intel's High NA EUV milestone Intel is running 0.55 NA EXE scanners in high-volume manufacturing on 18A in Oregon, printing selected layers of Panther Lake. First company to ship high-volume logic made with the technology. The more interesting decision is dual-qualification. Intel kept the 0.33 NA tools in the flow and qualified layers so wafers stay interchangeable between both. Q2 revenue Intel: $16.1 billion, up 25% year-over-year, its strongest growth in over 15 years. Data Center and AI grew 59%. TSMC: NT$442.68 billion in June alone, up 67.9%, with first-half 2026 up more than 35%. Washington Ashish was on Capitol Hill last week. SEMI is pushing to preserve and strengthen the Section 48D Advanced Manufacturing Investment Credit, the incentive behind billions in new fab construction. The decisions being made now determine where chips get built for the next decade. He also visited the Udvar-Hazy Center in Virginia, where the through-line for the episode showed up: mid-20th century defense requirements forced the silicon chip into existence. Missile guidance first, everything else after. Article coming on EEHerald soon. One question for the design engineers here. Which is the harder problem right now, the agent that designs the chip or the accountability model for when it gets it wrong? Episode link in the comments. #Semiconductors #EDA #DAC2026 #AgenticAI #EUV Cadence Rapidus Corporation SEMI DAC, The Chips to Systems Conference

IBM says it has crossed below 1nm. Applied Materials is quietly running a two-headed engine across Singapore and India. And IISc's CeNSE has a plan for the lab-to-fab gap nobody talks about. All three, plus nine more from the month, in the first edition of EEH Digest. Subscribe. it's free, and it's written by engineers who cover this beat full time.

Qualcomm and Samsung are elevating the device experience by unifying AI across smartphones, wearables, and smart glasses! Their latest partnership brings Qualcomm's Snapdragon chips to key Samsung devices, enhancing everything from the Galaxy Z Fold8 to Galaxy Watch9. With the introduction of Snapdragon 8 Elite Gen 5 and Snapdragon Wear Elite, users can expect powerful performance, smarter AI features, and seamless connectivity among devices. This collaboration aims to create a context-aware ecosystem where your phone, watch, and eyewear can adapt in real-time to your needs. Curious about how this groundbreaking partnership will reshape the future of user experience? Dive into the details of this exciting expansion!  https://lnkd.in/diFbMY5J #semiconductors #mobiletech #AI

Mitsubishi Electric is taking a bold step into the future of aerospace with a $10 million investment in Array Labs, a startup pioneering satellite-mounted radar technology. This collaboration aims to enhance satellite-based information services, particularly for national security and air traffic management. Array Labs' cutting-edge approach combines multiple satellites for better detection and real-time tracking of airborne objects like aircraft and drones, transcending the limitations of traditional ground-based systems. With plans to launch a radar satellite constellation between 2027 and 2028, they seek to validate and commercialize advanced space-based capabilities. Discover how this partnership could reshape the landscape of satellite surveillance and airspace security. https://lnkd.in/dnCD7c8J #satellites #radar #security #aerospace #technology

For decades, the semiconductor industry has dealt with rising design complexity by simply adding more resources. But what if artificial intelligence could take on entire engineering tasks? At DAC 2026, Cadence and NVIDIA are introducing the industry's first Silicon-to-System Agentic AI Engineering Platform, moving toward a future where AI agents can reason through design problems and automate significant design workflows. This innovative platform leverages NVIDIA's Nemotron 3 Ultra model, currently a leader in agentic RTL coding, allowing AI to not only generate hardware description code but also evaluate designs and iterate on its own work. Cadence's AI Super Agents are set to cut chip verification time from weeks to under a day, transforming how engineering teams operate. Curious about how this technology can reshape your workflow? Dive into the full article to learn more about this groundbreaking development. https://lnkd.in/dffDwuMC #semiconductors #AI #engineering #ChipDesign #electronics

Accelerating RF and mixed-signal silicon design! Keysight Technologies has certified its RFPro electromagnetic (EM) design software for Intel Foundry’s advanced Intel 14A and Intel 18A-P manufacturing process nodes. By validating EM simulations before tape-out, the certified EDA solution eliminates costly redesigns for complex AI, HPC, and mobile chips utilizing new RibbonFET 2 and PowerDirect architectures. As Keysight SVP Niels Fache and Intel's Shawn Han highlighted, this strategic collaboration enables engineering teams to innovate early and achieve predictable, first-pass silicon success! Read more: https://lnkd.in/deXHJkqK #Semiconductors #EDA #IntelFoundry #Keysight #RF #ChipDesign #TechNews #Silicon

Supercharging silicon design with agentic AI! At DAC 2026, Synopsys Inc showcased breakthrough advances in advanced chip design and multiphysics-aware simulation. Highlighting major ecosystem collaborations, Synopsys unveiled long-running autonomous AI agents with NVIDIA via AgentEngineer, introduced autonomous EDA workflows with AMD and Microsoft on Microsoft Discovery, and certified AI-powered flows on Intel’s 14A process technology. Synopsys also joined the new Open Secure AI Alliance. Specialized teams of AI agents are now officially transforming EDA from initial specs to finished silicon! Read more: https://lnkd.in/d4H8MGgv #Semiconductors #EDA #AI #Synopsys #NVIDIA #Microsoft #AMD #ChipDesign #TechNews

Self-verifying AI agents for chip design! Siemens has expanded its strategic partnership with NVIDIA to bring self-checking agentic AI to electronic design automation (EDA). Integrating Siemens' Fuse EDA AI Agent system with NVIDIA's NeMo Gym, OpenShell, and Nemotron reasoning models allows autonomous agents to continuously validate complex engineering decisions against physics-grounded tools. In library characterization, turnaround times dropped over 10x while token costs shrank 5-10x. As Amit Gupta noted, pairing industrial AI with accelerated computing ensures faster, highly trusted silicon convergence! Read more: https://lnkd.in/dbM9ykX6 #Semiconductors #EDA #AI #Siemens #NVIDIA #ChipDesign #TechNews

Securing the future of U.S. semiconductor manufacturing! Industry leaders from SEMI met with lawmakers in Washington to push for a multi-year extension of the Section 48D Advanced Manufacturing Investment Credit before its year-end deadline. The 35% tax credit has driven billions in CHIPS Act investments across 28 states. President Joe Stockunas emphasized that extending this incentive and expanding it to materials, gases, and design is critical to maintaining competitiveness against aggressive global rivals. Long-term policy certainty is essential for domestic chip investment! Read more: https://lnkd.in/d9ah8UxR #Semiconductors #CHIPSAct #SEMI #TaxIncentives #SupplyChain #USManufacturing #TechNews #GlobalTech