Papers by Andreas Baenisch
Yield Analysation and Optimization Methods for Active CMOS Pixels
arXiv (Cornell University), Feb 26, 2015
A concept for a novel CMOS image sensor suited for analog image pre-processing is presented in th... more A concept for a novel CMOS image sensor suited for analog image pre-processing is presented in this paper. As an example, an image restoration algorithm for reducing image noise is applied as image pre-processing in the analog domain. To supply low-latency data input for analog image preprocessing, the proposed concept for a CMOS image sensor offers a new sensor signal acquisition method in 2D. In comparison to image pre-processing in the digital domain, the proposed analog image pre-processing promises an improved image quality. Furthermore, the image noise at the stage of analog sensor signal acquisition can be used to select the most effective restoration algorithm applied to the analog circuit due to image processing prior to the A/D converter.
Herstellungsverfahren von Feldeffekttransistoren in integrierten Halbleiterschaltungen
Implementation of a high-speed flash ADC for high-performance pipeline ADCs in an 180nm CMOS process
2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2015
Pipeline Analog to Digital Converters (ADC) use a sub-ADC in each pipeline stage. They require a ... more Pipeline Analog to Digital Converters (ADC) use a sub-ADC in each pipeline stage. They require a much higher sampling rate and less accuracy. For that reason Flash ADCs are predestined for sub-ADCs. In this paper a differential Flash ADC is presented for a targeted pipeline ADC with 16 Bit, 200 MS/s and a 1.5 Bit resolution per stage. The overall accuracy of the Flash ADC is 30mV and a typical propagation delay of around 400 ps is achieved. This corresponds to a sampling rate of 2.5 GS/s. In addition, a new numerical method for an effective simulation of the propagation delay and offset is presented.
A method for storage of data, method of reading data, apparatus for compressing data, and means for decompressing data
A method for storing data on a mass storage device by a computer system, which computer system su... more A method for storing data on a mass storage device by a computer system, which computer system supplies constructed the mass memory for storing the rules of a file system data, which mass memory is of the random access type, in which the data in data blocks (1, 2, 3) are organized, wherein the data blocks are provided for the rack according to the rules of a file system of a computer system, the data supplied on the mass storage, wherein the data blocks organization information items (21, 31, 22, 32, 23, 33) at the beginning and are arranged at the end of a data block, included for managing data blocks and the useful information to be stored, said contiguous useful information regions (11, 12, 13) via a plurality, then by means of their organization information with each of concatenated data blocks distributed may be, wherein the contiguous payload information of one or more data blocks from the Organisationsinformatio n is separated and is collected continuously (10) and in a subse...
Yield Analysation and Optimization Methods for Active CMOS Pixels
Production method of field effect transistors in integrated semiconductor circuits
The invention relates to a method for producing a field effect transistor, which is inside a semi... more The invention relates to a method for producing a field effect transistor, which is inside a semiconductor integrated circuit. At least two extending between a source region respectively (S) and a drain region (D) extending gate regions (G1, G2) in the thickness direction of a substrate (SUB) one above the other arranged so that the space requirement of the usual larger field effect transistors is reduced in semiconductor integrated circuits.
Arrangement with an electronic circuit board and at least one semiconductor device and method
Assembly (50) with an electronic circuit board (20) and at least one semiconductor chip (30), whe... more Assembly (50) with an electronic circuit board (20) and at least one semiconductor chip (30), wherein the semiconductor device (30) and the electronic circuit board (20) each having a plurality of electrical contact terminals (21, 31) on each of which a fastening means (1) is mounted, - wherein connection elements (3b) mounted on the on the semiconductor chip (30) attachment means (1) with connecting elements mounted (3a) of the of the electronic circuit board (20) fixing means (1) engage in one another and thereby electrically conductive connections between the contact terminals (31 ) to produce the semiconductor device (30) and the contact terminals (21) of the electronic circuit board (20) and - each fixing means (1) comprises a carrier element (2) and a plurality of connecting elements (3), wherein the connecting elements (3) on the respective support element (2) are arranged and each having an elongated body, consisting of the carrier element (2 ) protrudes and for engaging and...
Contacting metal traces of an integrated semiconductor chips
An integrated semiconductor chip has at least two metal leads (1, 2) of two different metallizati... more An integrated semiconductor chip has at least two metal leads (1, 2) of two different metallization (11, 12) which are arranged parallel to each other. The metal leads (1, 2) are interconnected via at least one electrically conductive contact point (3). The metal leads (1, 2) extend orthogonally to each other in a first region (10) in each direction. In a second region (20), in which they are contacted with each other, they run in each direction parallel to one another and at an oblique angle to the directions of the metal conductor tracks (1, 2) of the first region (10). With this arrangement, a comparatively small space requirement necessary for contacting each other othogonalen metal lines, is at a low effect of electromigration, possible.
A low power CMOS transmitter with Class-E power amplifiers for positioning application in multi-band
2016 German Microwave Conference (GeMiC), 2016
In this paper, a transmitter for outdoor positioning application such as animal tracking is intro... more In this paper, a transmitter for outdoor positioning application such as animal tracking is introduced. Class-E power amplifiers are exploited in the transmitter system in order to increase the energy efficiency for the demand of long operation duration of the system. Along with the need of power saving, a circuit topology is proposed to realize the modulation based on Binary Offset Carrier (BOC) technique at two different bands to achieve higher positioning accuracy and better utilization of the spectrum by transmitting data simultaneously. The operating frequencies of the system are 868 MHz and 2.4 GHz, and the circuit is designed in 150nm CMOS technology. The Class-E power amplifier shows the broadband characteristics on the power efficiency from 1 to 3GHz while the measured output power is greater than 10 dBm from 1.3 to 2.8 GHz.
A CMOS image sensor with analog pre-processing capability suitable for smart camera applications
2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2015
This work presents a novel CMOS sensor which is suitable for analog image processing operations a... more This work presents a novel CMOS sensor which is suitable for analog image processing operations and describes the benefits of analog pre-processing over digital algorithms. All needed modifications to read out a spatial NxN pixel matrix simultaneously are presented regarding pixel wiring, row decoder and column multiplexer as well as descrambling the order of the outputs. The outputs are connected via a buffer stage to the analog pre-processing circuits. As an example for such an analog computation, an averaging filter is described from design constraints to the actual implementation. Simulation results show a very low current consumption of just 55.3 μA under worst-case conditions and a computation time below 200 ns. This corresponds to a power-time product ratio of 1:18.75 compared to a digital state-of-the-art implementation.
A flexible mixed-signal image processing pipeline using 3D chip stacks
Journal of Real-Time Image Processing, 2016
This work presents a highly flexible mixed-signal CMOS image sensor suitable for smart camera app... more This work presents a highly flexible mixed-signal CMOS image sensor suitable for smart camera applications. These systems need to fit different constraints regarding power consumption, speed and quality, and the optimal compromise may differ depending on the application. Moreover, the best implementation of a desired image processing task may be in the analog or the digital domain, or even a combined computation. Different aspects starting from the image sensor and signal acquisition up to the pre-processing in analog and digital domain are investigated in this paper to optimize not just one part of the system, but the whole system altogether. Moreover, it is shown that analog processing algorithms can improve signal quality, processing speed and latency while being able to save power, which is important for real-time systems. In order to be able to carry out spatial operations, the state-of-the-art sensor is modified to be able to read out multiple pixels at the same time. This allows analog spatial filter operations which consume significantly less power. As an example, an averaging filter is described which needs less than 5.3 % of the power–time product of a digital implementation for one computation. To enhance data throughput and flexibility, 3D chip stacking is proposed to partition the sensor in smaller units and enable massively parallel processing.
Data memory with redundant memory cells used for buffering a supply voltage
Storage Element and Method for Operating a Storage Element
Integrated circuit with active regions having varying contact arrangements
Integrated semiconductor circuit with embedded semiconductor memory
A 20-Gbps low jitter analog clock recovery circuit for ultra-wide band Radio systems
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
ABSTRACT This work describes the design of high speed clock recovery circuit for UWB M-sequence b... more ABSTRACT This work describes the design of high speed clock recovery circuit for UWB M-sequence based Radio systems in the analog domain to avoid the high power consumed in the analog to digital converters (ADC). The clock recovery circuit depends on two modes, the coarse tuning mode and the fine tuning mode for final locking and tracking. It is illustrated, using this method, that low jitter is achieved while maintaining high acquisition range up to the tuning range of the VCO. The method depends on using a reference M-sequence in the receiver similar to the one used in the transmitter and an analog correlation circuit. The circuits are designed using a low cost 0.25μm 95GHz fmax SiGe-HBT-BiCMOS process technology consuming an estimated power of 185mW.
Method of manufacturing field effect transistors in integrated semiconductor circuits
Method for reducing the evaluation outlay in the monitoring of layout changes for semiconductor chips
Means of mounting for electronic components, arrangement and procedure
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Papers by Andreas Baenisch