Papers by Bal Chand Nagar
A Novel D-Latch Design for Low-Power and Improved Immunity
Smart innovation, systems and technologies, 2024
DTMOS based four-quadrant multiplier/divider with voltage difference transconductance amplifier
Analog Integrated Circuits and Signal Processing, Jan 16, 2024
FPGA Implementation of IIR Notch and Anti-Notch Filters with an Application to Localization of Protein Hot-Spots
IEEE Transactions on NanoBioscience
Junctionless FETs based on a silicon-on-insulator architecture with a buried metal fin for multi-threshold operation
Journal of Computational Electronics, Sep 27, 2022
LCINDEP: a novel technique for leakage reduction in FinFET based circuits
Semiconductor Science and Technology
Due to the continuous downsizing of metal oxide semi-conductor field effect transistor devices, p... more Due to the continuous downsizing of metal oxide semi-conductor field effect transistor devices, power dissipation is one of the vital issues for the integrated circuit design. As a result of voltage scaling at lower technology nodes, threshold voltage decreases which results in increase in leakage current, hence leads to increase in leakage power dissipation. In this paper, a novel low leakage technique called LCINDEP (leakage control input DEPendent) is proposed for nano-scaled circuits. The device characteristics and hence overall performance gets affected due to increased power dissipation. Proposed LCINDEP technique is extensively demonstrated for low power operation and reliability analysis. Various short gate (SG) fin type field effect transistor (FinFET) logic circuits are simulated using LCINDEP technique and comparative analysis is performed with the already available leakage reduction techniques. The proposed LCINDEP technique provides reduced leakage power by 89.71% and 9...
Single OTA-based tunable resistorless grounded memristor emulator and its application
Journal of Computational Electronics
New Realization of Multi-function Filter using Bulk-Driven Differential Difference Current Conveyor
2019 International Conference on Communication and Signal Processing (ICCSP)
In this article, a novel structure of voltage mode multifunction filter is proposed. The proposed... more In this article, a novel structure of voltage mode multifunction filter is proposed. The proposed circuit use two BD-DDCC and four number of passive components; two resistances and two capacitances. Proposed circuit realizes low-pass, high-pass and band-pass responses from the same topology. The non-ideality and sensitivity analysis of the circuits are also included. The theoretical results are verified with PSPICE simulation using 180nm CMOS process parameters provided by TSMC. Frequency responses for the presented filters are shown in the paper. Simulation results agree well with the theoretical values. Moreover the proposed circuit consumes very low power merely 37.1μW.
Single OTRA Based Immittance Simulator and its Application
2018 International Conference on Communication and Signal Processing (ICCSP)
In this study, new grounded immittance simulator and their application are presented. The propose... more In this study, new grounded immittance simulator and their application are presented. The proposed circuit uses single operational trans-resistance amplifier and requires three numbers of passive elements two resistors and one capacitance. The performance of the proposed immittance simulator is demonstrated through the realization of multi function filters. PSPICE simulation results are found to be close agreement with theoretical predictions.
Improved Leakage Current Performance in Domino Logic Using Negative Differential Resistance Keeper
Advances in Intelligent Systems and Computing, 2019
In this article, a new improved domino logic-based topology is proposed for achieving improved le... more In this article, a new improved domino logic-based topology is proposed for achieving improved leakage current performance using negative differential resistance (NDR) keeper circuit. The NDR keeper is used to preserve the correct output level and reduced the power consumption with negative resistance. The proposed domino circuit is verified using Synopsys HSPICE simulator with 45 nm and 16 nm technology parameter provided by PTM model library. The simulation outcomes validate the improved performance of the proposed circuit in terms of leakage power consumption and power delay product. Simulation results show that the proposed NDR keeper circuit provides lower static and dynamic power consumption up to 26 and 30% respectively for 16nm technology, as compared to the domino circuits.
Higher Order Low-Pass Filter Using Single Current Differencing Buffered Amplifier
Advances in Intelligent Systems and Computing, 2018
This paper proposes a higher order low-pass filter using only one current differencing buffered a... more This paper proposes a higher order low-pass filter using only one current differencing buffered amplifier (CDBA) as an active element. The proposed circuits realize third-order, fourth-order, and fifth-order low-pass filter responses. The PSpice simulation results using 0.5 µm CMOS technology agree well with the theoretical proposition. Power consumption and percentage of total harmonic distortion are very low for the proposed circuits which is useful for low-power VLSI design.
Squarer and Sinusoidal Frequency Doubler Based on Single OTRA
2018 2nd International Conference on Power, Energy and Environment: Towards Smart Technology (ICEPE), 2018
In this paper, a simple circuit design technique for realizing analog squarer is proposed. Its ex... more In this paper, a simple circuit design technique for realizing analog squarer is proposed. Its extension as sinusoidal frequency doubler has also been discussed. The proposed circuit uses single operational trans-resistance amplifier, two n-channel MOS transistors and one resistor. If the resistor is replaced by two n-channel MOS transistors then the circuit is fully suitable for monolithic integration. In the proposed circuit the power consumption and total harmonic distortion are found 0.743μW and 1.2% respectively. The performance of the proposed squarer and frequency doubler circuit are verified through PSPICE simulators using 0.5μm CMOS technology parameter provided by MOSIS (AGILENT). The simulation result confirms the feasibility of the proposed circuit.
New tunable resistorless grounded meminductor emulator
Journal of Computational Electronics, 2021
In this research article, a grounded resistorless meminductor emulator is proposed. The proposed ... more In this research article, a grounded resistorless meminductor emulator is proposed. The proposed emulator uses one voltage differencing transconductance amplifier (VDTA) and one operational transconductance amplifier (OTA) with corresponding grounded capacitances. It can be operated in both decremental and incremental configurations. The comparison of the proposed emulator with available literature is also included. The proposed meminductor emulator circuit has been designed and simulated in Cadence Virtuoso Analog Design Environment using 180 nm gdpk technology parameters. Moreover, the application of the proposed emulator as a second-order bandpass filter (BPF) is also given. The simulation results agree well with the theory and confirm the meminductor functionality.
New Multi-function Third-Order Inverse Filter using OTRAs
Journal of The Institution of Engineers (India): Series B, 2021
Design of a CMOS Comparator for A/D Converter Application
In this paper, an n-channel junctionless FET (JLFET) based on SOI with a buried metal fin (BMF) i... more In this paper, an n-channel junctionless FET (JLFET) based on SOI with a buried metal fin (BMF) is presented. We show that the BMF of suitable workfunction of the proposed device BMF-SOI-JLFET can control the channel electrostatic field by employing Schottky junction effectively. The enhanced association of potential between BMF and the channel combined with gate electric field makes it worthy for multi-threshold and dynamic threshold (DT) operation. Additionally, the biasing of BMF projects the broad range of threshold voltage (VTH) regulation with a high value of body factor (γ). The proposed device demonstrates γ enhancement compared to fin body (FB)-JLFET and conventional SOI-JL FET under identical conditions due to constant potential coupling. The DT mode of operation shows a 73% improvement in ON-state current in addition to reduced subthreshold swing contrast to BMF-SOI-JLFET without DT. This paper imparts a viable option for low power applications with multi-threshold opera...
Realization of OTRA-Based Quadrature Oscillator Using Third-Order Topology
Advances in Systems, Control and Automation
A New Keeper Domino Logic Based Full Adder for High Speed Arithmetic Circuits
Micro and Nanosystems
Objective: A new efficient keeper circuit has been proposed in this article for achieving low lea... more Objective: A new efficient keeper circuit has been proposed in this article for achieving low leakage power consumption and to improve power delay product of the dynamic logic using carbon nanotube MOSFET. Method: As a benchmark, an one-bit adder has been designed and characterized with both technologies Si-MOSFET and CN-MOSFET using proposed and existing dynamic circuits. Furthermore, a comparison has been made to demonstrate the superiority of CN-MOSFET technology with Synopsys HSPICE tool for multiple bit adders available in the literature. Result: The simulation results show that the proposed keeper circuit provides lower static and dynamic power consumption up to 57 and 40% respectively, as compared to the domino circuits using 32nm CN-MOSFET technology provided by Stanford University. Moreover, the proposed keeper configuration provides better performance using SiMOSFET and CN-MOSFET technologies. Conclusion: A comparison of the proposed keeper with previously published design...
Single OTRA based two quadrant analog voltage divider
Analog Integrated Circuits and Signal Processing
Improved Domino Logic Circuits and its Application in Wide Fan-in OR Gates
Micro and Nanosystems
Main concern in efficient VLSI circuit designing is low-power consumption, high-speed and noise t... more Main concern in efficient VLSI circuit designing is low-power consumption, high-speed and noise tolerance capability. In this paper, two efficient and high performance topologies are proposed for cascaded domino logic using carbon nanotube MOSFETs (CN-MOSFETs). The first topology is designed to remove the intermediate charge sharing problem without any keeper circuit, whereas the second one holds the true logic level of the evaluation phase without any voltage drop for next precharge phase. The proposed topologies are suitable for cascading of the high performance domino circuits. A wide fan-in domino OR gate circuits are designed as a benchmark to verify the proposed topologies. The proposed domino circuits are tested and verified using Synopsys HSPICE simulator with 32nm CN-MOSFET technology provided by StanfordUniversity. The power delay product of proposed DL-I and DL-II improves by 32.59 % and 40.98 % for 8-input OR gate as compared to standard logic respectively at the clock f...
Low power wide fan-in domino OR gate using CN-MOSFETs
International Journal of Sensors, Wireless Communications and Control
Background & Objective: In this paper, a modified pseudo domino configuration has been proposed t... more Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.
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Papers by Bal Chand Nagar