Cecilia Metra

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Papers by Cecilia Metra

On-Line Test and Fault Tolerance

International audienc

Special Section on Emerging Trends and Design Paradigms for Memory Systems and Storage

IEEE Transactions on Emerging Topics in Computing, 2019

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Message from the Editor-in-Chief

IEEE Transactions on Emerging Topics in Computing, 2019

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Low-Cost Strategy to Mitigate the Impact of Aging on Latches’ Robustness

IEEE Transactions on Emerging Topics in Computing, 2018

Analyses recently presented in the literature have shown that the Bias Temperature Instability (B... more Analyses recently presented in the literature have shown that the Bias Temperature Instability (BTI) ageing phenomenon may increase significantly the susceptibility to soft errors (SEs) of robust latches. Particularly, this is the case of low-cost robust latches, whose robustness is obtained by increasing the critical charge of their most susceptible node, that is the node most contributing to the latch soft error rate (SER). Therefore, in applications mandating the use of low-cost robust latches, designers will have to face the problem of such latches’ robustness degradation during the IC operation. In order to cope with this problem, we here propose a strategy to reduce the impact of BTI on the SER of standard and low-cost robust latches. It will be proven that our approach enables to reduce by approximately the 50 percent the SER increase due to BTI during circuit lifetime with respect to original latches, at limited increase in terms of area overhead, latch setup time and power consumption, and with no impact on the latch input-output delay.

Trading Off Dependability and Cost for Nanoscale High Performance Microprocessors: The Clock Distribution Problem

The continuous scaling of microelectronics technology allows for keeping on increasing IC perform... more The continuous scaling of microelectronics technology allows for keeping on increasing IC performance and complexity, but simultaneously poses serious challenges to design, test and dependability. For high performance microprocessors, guaranteeing that clock signals are distributed throughout the die with correct skew, dutycycle, limited jitter and sharp edges is becoming ever more challenging, and is expected to get even worse for next generation microprocessors. On the other hand, the availability of correct clock signals throughout the die is mandatory for their dependable operation. This problem will be described and possible approaches for dependable clock signal distribution will be discussed.

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On the design of self-checking functional units based on Shannon circuits

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)

This paper investigates the application of Shannon (BDD) circuits, that feature interesting low-p... more This paper investigates the application of Shannon (BDD) circuits, that feature interesting low-power capabilities, to the design of self-checking functional units. A technique is proposed that, by using a time redundancy approach, makes this kind of circuits totally self-checking with respect to stuck-at faults. For a set of possibly used passtransistor-based CMOS implementations, we show that the totally self-checking or the strongly fault secure properties hold for a wider set of realistic faults, including transistors stuck-open/on and bridgings.

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Crosstalk effect minimization for encoded busses

9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003.

Abstract In this paper we present a technique which allows to reduce the crosstalk-induced delay ... more Abstract In this paper we present a technique which allows to reduce the crosstalk-induced delay within busses imple- menting an error detecting/correcting code. This tech- nique is based on the observation that the maximum delay on an encoded,bus is usually due to the check bits that are added to provide the desired error detec- tion/tolerance ability. These bits, in fact,

Majority Logic

Wiley Encyclopedia of Electrical and Electronics Engineering, 1999

Error Correcting Strategy for High Speed and High Density Reliable Flash Memories

Journal of Electronic Testing, 2003

This paper presents a method to reduce area overhead and timing impact due to the implementation ... more This paper presents a method to reduce area overhead and timing impact due to the implementation of standard single symbol correcting codes for Flash memories. It is based on a manipulation of the parity check matrix which defining the code, which allows us to minimize the matrix weight and the maximum row weight. We will then introduce an analysis of

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2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems Impact of Aging Phenomena on Soft Error Susceptibility*

⎯ In this paper we address the issue of analyzing the effects of negative bias temperature instab... more ⎯ In this paper we address the issue of analyzing the effects of negative bias temperature instability (NBTI) on ICs ’ soft error susceptibility. We show that NBTI reduces significantly the critical charge of nodes of both combinational and sequential circuits during their in-field operation. Furthermore, we prove that combinational circuits present a higher relative reduction of node critical charge than sequential ones. Therefore, as an IC ages, the soft-error susceptibility of its combinational parts will increase much more than that of its sequential parts. This poses new challenges to ICs ’ soft error susceptibility modeling, mandating a time dependent modeling (in contrast to the static modeling broadly considered till now), and a diverse time dependent modeling for their combinational and sequential parts. I.

2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems On-Die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter *

– We present a novel low cost scheme for the on-die measurement of either clock jitter, or proces... more – We present a novel low cost scheme for the on-die measurement of either clock jitter, or process parameter variations. By re-using and properly modifying the Ring Oscillators (ROs) that are currently widely employed for process parameter variation measurement in high performance microprocessors, our proposed scheme can be easily set in either the process parameter variation measurement mode, or the clock jitter measurement mode, by acting on an external control signal. This way, during the test or debug phase, clock jitter can also be measured at negligible area and power costs with respect to process parameter variation measurement only. Our scheme is scalable in the provided clock jitter measurement resolution, while allowing the same process parameter variation measurement resolution as the currently employed RO based schemes. Moreover, due to its allowing both process parameter variation and clock jitter measurements, our scheme features accurate clock jitter measurement despi...

Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST

IEEE Transactions on Computers, 2015

During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activ... more During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during its in field operation. Consequently, power droop (PD) may take place during both shift and capture phases, which will slow down the circuit under test (CUT) signal transitions. At capture, this phenomenon is likely to be erroneously recognized as due to delay faults. As a result, a false test fail may be generated, with consequent increase in yield loss. In this paper, we propose two approaches to reduce the PD generated at capture during at-speed test of sequential circuits with scan-based Logic BIST using the Launch-On-Shift scheme. Both approaches increase the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, the AF of the scan chains at capture is reduced. Consequently, the AF of the CUT at capture, thus the PD at capture, is also reduced compared to conventional scan-based LBIST. The former approach, hereinafter referred to as Low-Cost Approach (LCA), enables a 50% reduction in the worst case magnitude of PD during conventional logic BIST. It requires a small cost in terms of area overhead (of approximately 1.5% on average), and it does not increase the number of test vectors over the conventional scan-based LBIST to achieve the same Fault Coverage (FC). Moreover, compared to three recent alternative solutions, LCA features a comparable AF in the scan chains at capture, while requiring lower test time and area overhead. The second approach, hereinafter referred to as High-Reduction Approach (HRA), enables scalable PD reductions at capture of up to 87%, with limited additional costs in terms of area overhead and number of required test vectors for a given target FC, over our LCA approach. Particularly, compared to two of the three recent alternative solutions mentioned above, HRA enables a significantly lower AF in the scan chains during the application of test vectors, while requiring either a comparable area overhead or a significantly lower test time. Compared to the remaining alternative solutions mentioned above, HRA enables a similar AF in the scan chains at capture (approximately 90% lower than conventional scan-based LBIST), while requiring a significantly lower test time (approximately 4.87 times on average lower number of test vectors) and comparable area overhead (of approximately 1.9% on average).

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Testing Reversible 1D Arrays for Molecular QCA

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Reversible logic design is a well-known paradigm in digital computation. While an extensive liter... more Reversible logic design is a well-known paradigm in digital computation. While an extensive literature exists on its mathematical characterization, little work has been reported on its possible technological basis. In this paper, a quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic. Two new reversible gates (denoted as QCA1 and QCA2) are proposed. These gates are compared

On-line testing of transient and crosstalk faults affecting interconnections of FPGA-implemented systems

Proceedings International Test Conference 2001 (Cat. No.01CH37260)

... Cecilia Metra Andrea Pagano Bruno Riccb DEIS University of Bologna, Wale Risorgimento 2,40136... more

Compact and highly testable error indicator for self-checking circuits

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

A novel error indicator is proposed, which can be directly connected to the outputs of the checke... more A novel error indicator is proposed, which can be directly connected to the outputs of the checker of a self-checking circuit to memorize, until reset, the error indication possibly produced, independently of the successively given output words. The proposed error indicator features high on-line self-testing ability with respect to realistic faults, and a compact structure

Fault-tolerant voting mechanism and recovery scheme for TMR FPGA-based systems

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)

... The used code is reported in the truth table shown in Table 1. The set of MVi j values repres... more

Self-checking scheme for the on-line testing of power supply noise

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

We propose a self-checking scheme for the on-line testing of power supply noise exceeding a toler... more We propose a self-checking scheme for the on-line testing of power supply noise exceeding a tolerance bound to be chosen accordingly to system's constraints. Upon the occurrence of such a noise, our scheme provides an output error message, which can be exploited for diagnosis purposes or to recover from the detected noise (thus guaranteeing the system's correct operation). As far as we are concerned, no on-line testing scheme for power supply noise has been proposed up to now. Our scheme negligibly impacts system's performance, features self-checking ability with respect to a wide set of possible internal faults and keeps on revealing on-line the occurrence of power supply noise, despite the possible presence of noise affecting also ground.

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Testing Reversible One-Dimensional QCA Arrays for Multiple F

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Reversible logic design is a well-known paradigm in digital computation. In this paper, quantum-d... more Reversible logic design is a well-known paradigm in digital computation. In this paper, quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic in array systems. C-testability of a ID array is investigated for multiple cell faults. It has been shown that fault masking is possible in the presence of multiple faults [9]. A technique for achieving C-testability

Fast and compact error correcting scheme for reliable multilevel flash memories

Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002)

ABSTRACT

Design and implementation of a self-checking scheme for railway trackside systems

Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002)

ABSTRACT

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