Delong Shang

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Papers by Delong Shang

AMA-Det: Enhancing Shared Head of One-Stage Object Detection With Adaptation, Merging, and Alignment

IEEE Access, 2023

Feature adaptation (FA) and result alignment(RA) are critical issues in one-stage object detectio... more Feature adaptation (FA) and result alignment(RA) are critical issues in one-stage object detection, since FA amends feature misalignment problem by adapting sampling points to semantically significant locations, and RA corrects result misalignment problem by estimating the localization quality. For FA, the aligned and consistent prediction of sampling points is important. Previous studies directly inherit cascaded ''proposal-refine'' philosophy from multi-stage detectors and predict sampling points by approximating their minimal external rectangle to ground-truth bounding boxes. This manner generates poorly aligned and consistent sampling points and induces irrelevant features aggregated. Moreover, their sampling points for classification are conventionally generated through the localization branch, without feeding the corresponding features of the classification branch. For RA, previous studies have verified the superiority of utilizing the predicted edge distribution to estimate localization quality; however, their directly regressed distribution is incompatible with the cascaded regression framework. To solve these problems, we firstly propose a focused feature adaptation method by softening the supervision of the proposal points. This method can predict sampling points focused above the assigned objects with excellent alignment and consistency. Subsequently, inner-branch and cross-branch merging were investigated to promote feature sharing from the classification branch. Finally, cascaded distribution-guided result alignment is advanced and verified to predict accurate localization quality. After integrating our proposed adaptation, merging, and alignment, we created AMA-Det with an enhanced shared head, which impressively reaches 43.9 mAP with ResNet50 as the backbone. AMA-Det also achieves a 54.5 mAP by multi-scale testing on MSCOCO test-dev and outperforms all existing CNN-based one-stage counterparts. Generic object detection [1] is one of the most fundamental and long-standing topics in computer vision and is intended to localize the bounding boxes of objects in an image and classify their categories. In recent years, owing to the The associate editor coordinating the review of this manuscript and approving it for publication was Sergio Consoli . rapid development of convolutional neural network(CNN), CNN-based object detection has achieved notable performance improvements, supporting various applications including autonomous driving [2], robot navigation [3] and infrared imagery [4]. Currently, popular CNN-based object detectors can be categorized into one-stage [5],

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Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip

2018 IEEE 25th Symposium on Computer Arithmetic (ARITH)

Neuromorphic chips are used to model biologically inspired Spiking-Neural-Networks(SNNs) where mo... more Neuromorphic chips are used to model biologically inspired Spiking-Neural-Networks(SNNs) where most models are based on differential equations. Equations for most SNN algorithms usually contain variables with one or more e x components. SpiNNaker is a digital neuromorphic chip that has so far been using pre-calculated look-up tables for exponential function. However this approach is limited because the memory requirements grow as more complex neural models are developed. To save already limited memory resources in the next generation SpiNNaker chip, we are including a fast exponential function in the silicon. In this paper we analyse iterative algorithms for elementary functions and show how to build a single hardware accelerator for exp and natural log, for a neuromorphic chip prototype, to be manufactured in a 22 nm FDSOI process. We present the accelerator that has algorithmic level approximation control, allowing it to trade precision for latency and energy efficiency. As an addition to neuromorphic chip application, we provide analysis of a parameterized elementary function unit that can be tailored for other systems with different power, area, accuracy and latency constraints.

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A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits

Lecture Notes in Computer Science, 2004

The hardware implementation of AES algorithm as an asynchronous circuit has a reduced leakage of ... more The hardware implementation of AES algorithm as an asynchronous circuit has a reduced leakage of information through side-channels and enjoys high performance and low power. Dual-rail data encoding and return-to-spacer protocol are used to avoid hazards, including data-dependent glitches, and in order to make switching activity data-independent (constant). The implementation uses a coarse pipeline architecture which is different from traditional

Modelling Switched-Capacitor DC-DC Converters with Signal Transition Graphs

2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2018

Switched Capacitor DC-DC converters play an important role in low power technologies such as ener... more Switched Capacitor DC-DC converters play an important role in low power technologies such as energy harvesting systems as they can provide step-up voltage outputs with lower inputs. This paper models and analyses Switched Capacitor DC-DC converters with Signal Transition Graphs, which are originally used for modelling asynchronous circuits. With this new approach, the causality relations between phases, capacitors and internal signals in Switched-Capacitor DC-DC converter can be described distinctly, especially for some complicated converters. This is the first attempt at generating formal models for these types of components, which previously have been described by natural language and waveforms.

Fast capacitance-to-digital converter with internal reference

2016 IEEE Biomedical Circuits and Systems Conference (BioCAS), Oct 1, 2016

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Low-Cost Online Tesing of Asynchronous Handshakes

Synthesis and implementation of a signal-type asynchronous data communication mechanism

Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001

This paper describes the synthesis and hardware implementation of a signal-type asynchronous data... more This paper describes the synthesis and hardware implementation of a signal-type asynchronous data communication mechanism (ACM). Such an ACM can be used in systems where a data-driven ("lazy") logic must be interfaced with a time-driven ("busy") environment. A new classification system for ACMs is introduced. The conceptual definition of the signal ACM (called simply "Signal") is refined using Petri net techniques. Based on this, a more precise, state graph specification of a twoslot Signal is then constructed. Using theory of regions, a Petri net specification of the ACM is synthesized from the state graph. The Petri net model is then translated into a hardware implementation, which is entered into Cadence tools. Simulation results show that the hardware does conform to the definitions and specifications. The techniques employed in this work are potentially useful in the development of an automated process of synthesising similar systems.

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Asynchronous communication mechanisms using self-timed circuits

Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)

Two asynchronous data communication mechanisms (ACMs) using self-timed circuits are presented. Mu... more Two asynchronous data communication mechanisms (ACMs) using self-timed circuits are presented. Mutual exclusion elements are used to concentrate potential metastability to discrete points so that it can be resolved entirely within the ACMs themselves. Self-timed circuits allow the minimisation of the interface between the reader and writer processes and the ACMs. Initial analysis shows that these VLSI solutions are more robust with regard to steering logic metastability, and can potentially run faster than solutions under fundamental mode assumptions. They are therefore more suitable for use in on-chip multi-processing systems.

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An elastic timer for wide dynamic working range

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 2015

Oscillators are needed in many systems for time keeping purposes. They are often called timers. I... more Oscillators are needed in many systems for time keeping purposes. They are often called timers. In low duty cycle systems, such as wireless sensors, such oscillators may incur a significant portion of system power consumption. Extensive research exists in making on-chip oscillators low power. However, the other part of the time keeping function, that of computing the number of oscillation cycles, is normally not treated in such research. This paper describes research that focuses on developing oscillators with an innate capability of counting its own oscillation cycles, suitable for direct use as timekeeping devices. The functional correctness of solutions based on asynchronous counters and matched delays are demonstrated and a number of designs are characterized in terms of oscillation frequency and working ranges. In addition, the proposed timers are seamlessly elastic in relation to voltage variations.

An implementation of a three-slot asynchonous communication mechanism using self-timed circuits

A hybrid power delivery method for asynchronous loads in energy harvesting systems

10th IEEE International NEWCAS Conference, 2012

ABSTRACT Energy harvesting is becoming popular for small systems such as micro-sensors or medical... more ABSTRACT Energy harvesting is becoming popular for small systems such as micro-sensors or medical implantable devices, which may not need or be able to include large energy storage devices. However power from energy harvesting circuits may be very limited and vary within a large range. Therefore an on-chip intelligent and flexible power delivery method bypassing external energy storage devices and corresponding charging circuits may be advantageous. Also, different computation loads may tolerate different degrees of variance in the supplied VDD. Thus, a hybrid power delivery method fully behaving as switched capacitor dc-dc converter or capacitor bank block to generate stable or variable power supply is developed to cope with variable harvested energy. The method is verified by hardware, which has been employed for VLSI chip testing. It can be considered as a valuable reference for later on-chip fabrication and task &amp; power scheduling research.

A Low Power Asvnchronous MSP430 Processor for Ubiquitous Sensor Network

This paper describes the design of an asynchronous implementation of a sensor network processor. ... more This paper describes the design of an asynchronous implementation of a sensor network processor. The main purpose of this work is the reduction of power consumption in sensor network node processors and the research presented here tries to explore the suitability of asynchronous circuits for this purpose. The Handshake Solutions toolkit is used to implement an asynchronous version of a sensor processor. The design is made compact, trading area and leakage power savings with dynamic power costs, targeting the typical sparse operating characteristics of sensor node processors. It is then compared with a synchronous version of the same processor. Both versions are then compared with existing commercial processors in terms of power consumption.

Improving the Robustness of Self-timed SRAM to Variable Vdds

Lecture Notes in Computer Science, 2011

ABSTRACT The most efficient power saving method in digital systems is to scale Vdd, owing to the ... more ABSTRACT The most efficient power saving method in digital systems is to scale Vdd, owing to the quadratic dependence of dynamic power consumption. This requires memory working under a wide range of Vdds in terms of performance and power saving requirements. A self-timed 6T SRAM was previously proposed, which adapts to the variable Vdd automatically. However due to leakage, the size of memory is restricted by process variations. This paper reports a new self-timed 10T SRAM cell with bit line keepers developed to improve robustness in order to work in a wide range of Vdds down to 0.3V under PVT variations. In addition, this paper briefly discusses the potential benefits of the self-timed SRAM for designing highly reliable systems and detecting the data retention voltage (DRV).

Self-Timed SRAM for Energy Harvesting Systems

Journal of Low Power Electronics, 2011

Portable digital systems tend to be not just low power but power efficient as they are powered by... more Portable digital systems tend to be not just low power but power efficient as they are powered by low batteries or energy harvesters. Energy harvesting systems tend to provide nondeterministic, rather than stable, power over time. Existing memory systems use delay elements to cope with the problems under different Vdds. However, this introduces huge penalties on performance, as the delay elements need to follow the worst case timing assumption under the worst environment. In this paper, the latency mismatch between memory cells and the corresponding controller using typical delay elements is investigated and found to be highly variable for different Vdd values. A Speed Independent (SI) SRAM memory is then developed which can help avoid such mismatch problems. It can also be used to replace typical delay lines for use in bundleddata memory banks. A 1Kb SI memory bank is implemented based on this method and analysed in terms of the latency and power consumption.

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Testing a self-timed asynchronous communication mechanism (ACM) VLSI chip

ABSTRACT A testing method and on-chip testing circuits for our VLSI chip of an asynchronous commu... more ABSTRACT A testing method and on-chip testing circuits for our VLSI chip of an asynchronous communication mechanism (ACM) using self-timed circuits are presented in this paper. The main testing objective is in the three important ACM properties, asynchrony, coherence and freshness. In addition, the general function of the chip and data loss are also of interest. Although this work is a specific solution for a specific problem, it is an important step in the development of a methodology of testing hardware solutions of fully asynchronous systems. 1

Asynchronous Checker Designs for Monitoring Handshake Interfaces

Checker designs for on-line testing of asynchronous handshake interfaces are proposed here. The c... more Checker designs for on-line testing of asynchronous handshake interfaces are proposed here. The checker monitors the interface signals that follow a protocol. The checker produces a code word at its output when the interface signals abide to the protocol, where as, when the protocol is violated, a noncode word is generated at the output. Checkers are designed to directly implement sets of forbidden transitions, otherwise known as refusals. A "busy" approach is used to design the checker. In this approach, self-test of the checker is performed during the normal operation where the output signals are constantly switching.

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Multi-resource arbiter decomposition

PSK Signalling on NoC Buses

Lecture Notes in Computer Science, 2005

ABSTRACT A novel self-timed communication protocol is based upon phase-modulation of a reference ... more ABSTRACT A novel self-timed communication protocol is based upon phase-modulation of a reference signal. The reference and the data are sent on the same transmission lines and the data can be recovered observing the sequence of events on the same lines. The sender block consists of a reference generator and variable-delay elements, while the receiver includes a delay-locked loop for synchronization and a mutual exclusion element with additional logic (validity bit and FIFO) for data recovery. This protocol exhibits high robustness with respect to transient errors caused by narrow pulse interference, usually associated with crosstalk and radiation.

High-order reconfigurable FIR filter design based on statistical analysis of CSD coefficients

2013 International Conference on Field-Programmable Technology (FPT), 2013

ABSTRACT

Variation Tolerant AFPGA Architecture

2011 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011

This paper describes the realization of an interconnect Delay Insensitive (DI) FPGA architecture ... more This paper describes the realization of an interconnect Delay Insensitive (DI) FPGA architecture with distributed asynchronous control. This architecture maintains the basic block structure of traditional FPGAs allowing the potential use of existing FPGA design tools in block design. This asynchronous FPGA architecture is mainly aimed at tolerating the unpredictable delay variations caused by process and environment variations in current and future VLSI technology nodes and also targets power supply variations, including modes such as dynamic voltage scaling and variable Vdd, such as in applications featuring energy harvesting. This is achieved by making the longer inter-block interconnects DI, keeping the computational logic single-rail, and removing global clocks.

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