Dev Gupta

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Scientist, engineer, inventor and mathematician. Serial entrepreneur have started five startups, three sold to fortune 100 companies. Adjunct Professor of Electrical Engineering at Umass, Amherst.Technical Pioneer at World Economic Forum twice.

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Memristor-CMOS Analog Coprocessor for Acceleration of High-Performance Computing Applications

ACM Journal on Emerging Technologies in Computing Systems, 2018

Vector matrix multiplication computation underlies major applications in machine vision, deep lea... more Vector matrix multiplication computation underlies major applications in machine vision, deep learning, and scientific simulation. These applications require high computational speed and are run on platforms that are size, weight, and power constrained. With the transistor scaling coming to an end, existing digital hardware architectures will not be able to meet this increasing demand. Analog computation with its rich set of primitives and inherent parallel architecture can be faster, more efficient, and compact for some of these applications. One such primitive is a memristor-CMOS crossbar array-based vector matrix multiplication. In this article, we develop a memristor-CMOS analog coprocessor architecture that can handle floating-point computation. To demonstrate the working of the analog coprocessor at a system level, we use a new electronic design automation tool called PSpice Systems Option, which performs integrated cosimulation of MATLAB/Simulink and PSpice. It is shown that ...

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Analog signal processing solution for machine vision applications

Journal of Real-Time Image Processing, 2017

The field of machine vision is continuously evolving. There are new products coming into the mark... more The field of machine vision is continuously evolving. There are new products coming into the market that have very severe size, weight and power constraints and handle very high computational loads simultaneously. Existing architectures and digital image processing solutions will not be able to meet these ever-increasing demands. There is a need to develop novel architectures and image processing solutions to address these requirements. The major contribution of this work is to show that analog signal processing is a solution to this problem. The analog processor will be used as an augmentation device which works in parallel with the digital processor, making the system faster and more efficient. We have developed a prototype of an analog processing board using commercially available off-the-shelf components and demonstrated that a prototype development has several advantages over a direct integrated circuit design. We focus on providing experimental results that demonstrate functionality of the analog processing board and show that the performance of the prototype board for low-level and mid-level image processing tasks is equivalent to a digital implementation. To demonstrate improvement in speed and power consumption over other systems, we propose an integrated circuit design of the analog processor and show that such an analog processor would be 1009 faster than existing FPGAs and 59 faster than state-of-the-art GPUs. We also compare the performance of the proposed integrated circuit design against other analog processors reported in the literature. We report a case study in which we use the processor for an object detection and recognition application and show that the processor has excellent performance.

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Scalable multimedia network

A Nalog S Ignal P Rocessing S Olution F or I Mage a Lignment

Imaging and Image sensors is a field that is continuously evolving. There are new products coming... more Imaging and Image sensors is a field that is continuously evolving. There are new products coming into the market every day. Some of these have very severe Size, Weight and Power constraints whereas other devices have to handle very high computational loads. Some require both these conditions to be met simultaneously. Current imaging architectures and digital image processing solutions will not be able to meet these ever increasing demands. There is a need to develop novel imaging architectures and image processing solutions to address these requirements. In this work we propose analog signal processing as a solution to this problem. The analog processor is not suggested as a replacement to a digital processor but it will be used as an augmentation device which works in parallel with the digital processor, making the system faster and more efficient. In order to show the merits of analog processing the highly computational Normalized Cross Correlation algorithm is implemented. We pr...

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Scalable multimedia network

Systeme et procede pour la prestation de services de reseau

Un systeme recoit une simple demande de prestations de services provenant d'un initiateur (10... more Un systeme recoit une simple demande de prestations de services provenant d'un initiateur (103). Ce systeme determine chaque entite de reseau correspondant a la demande emise par un referentiel d'entites (114) de reseau. Ce systeme effectue les operations concernees par la demande de prestations de services au niveau de chaque entite de reseau (126) et permet ensuite la fourniture de ces services sans rechercher ni examiner manuellement le reseau pour determiner les entites du reseau concernees par une demande de prestation de services particuliere.

Procédé, système et appareil de traitement de signal à bande large

Des modes de realisation comprennent des procedes, des systemes et des appareils capables de fonc... more Des modes de realisation comprennent des procedes, des systemes et des appareils capables de fonctionner de maniere dynamique et adaptative sur des signaux a bande large. Des exemples comprennent des filtres a variables d'etat dont les frequences centrales peuvent etre accordees a l'aide de blocs de gain variable couples aux sorties de filtres integrateurs. Les filtres a variables d'etat de premier ordre et de second ordre peuvent fonctionner sur des signaux en parallele et leurs sorties combinees pour produire une sortie filtree. Les filtres peuvent etre accordes pour laisser passer ou rejeter des signaux en fonction de l'application; des applications echantillons comprennent, entre autres : filtrage agile; analyse spectrale; detection et rejet des interferences; egalisation; transmission par frequence intermediaire directe; et modulation et demodulation de bande laterale unique.

Stacked 3d package with improved bandwidth and power efficiency

Additional Conferences (Device Packaging, HiTEC, HiTEN, & CICMT), 2013

Stacked die packages such as PoP are used in space - constrained portable systems e,g. SmartPhone... more Stacked die packages such as PoP are used in space - constrained portable systems e,g. SmartPhones. The processor ( SoC ) and Mobile DRAM chips are stacked vertically to fit the combination within the restricted board space. The use of wire bonds in the memory chips as well as package level interconnects introduces delays into the data transmitted between the chips and limits the max. clock rate ( at present about 533 MHz for LP DDR 2 memory ) and hence the data transfer rate / bandwidth to less than 6.4 GB per sec. For Smart Phones to become capable of PC quality Games and high speed video would require a doubling of the bandwidth to over 12.8 GB per sec. To achieve that target PoP type packages were to be replaced by 3-d stacks using TSVs and wide I/Os. However recently JEDEC has postponed the introduction of Wide I/O Mobile memory stacks ( using TSVs ) to 2015. So the bandwidth of PoP packages must be improved. A physical way to increase the Bandwidth between the SoC and memory c...

Software-defined radio

Performance monitoring for loops

Scalable multimedia network

Performance of UWB systems in the presence of severe multipath and narrowband interference

2008 IEEE International Conference on Ultra-Wideband, 2008

Performance of UWB Systems in the Presence of ... Zhiguo Lai, Harshit Joshi, and Dennis Goeckel D... more

High linearity variable capacitor array

Procede et appareil destines au multiplexage de donnees provenant d'usagers multiples d'un meme circuit virtuel

L'invention concerne un procede et un appareil destines a etablir des communications entre un... more L'invention concerne un procede et un appareil destines a etablir des communications entre un noeud destinataire sur un reseau a bande large et des usagers multiples connectes a un noeud d'acces. Un circuit virtuel est prevu a travers le reseau a bande large afin de connecter le noeud d'acces au noeud destinataire. Des unites d'information provenant d'usagers multiples sont recues au noeud d'acces, chaque unite d'information etant dotee de cellules multiples. Les unites d'information sont multiplexees sur le circuit virtuel au noeud d'acces, de sorte que les cellules de toute unite d'information ne s'entrelacent pas avec les cellules de toute autre unite d'informations sur le circuit virtuel. Dans un mode de realisation prefere, le noeud destinataire est un noeud de fournisseur de services d'un reseau ATM, et les unites d'information sont des unites d'information de protocole Ethernet comportant de multiples cellules ATM. S...

QoS Management in Trunk-and-Branch

A likely architecture for the future broadband access network will consist of a trunk-and-branch ... more A likely architecture for the future broadband access network will consist of a trunk-and-branch topology, with very high bandwidth trunks (e.g., 1‐10 Gb/s), connected to high-bandwidth drops (or branches) to homes and businesses. A multihop switched Ethernet data transport can be used over this access network. In [1] we discussed the benefits of upgrading the hybrid fiber coax plant into a distributed switched Ethernet trunk-andbranch network capable of fiber-like transmission speeds. This article focuses on QoS management in the proposed next-generation broadband access network (NGBAN) based on a multihop switched Ethernet network architecture. This network architecture and QoS management framework are more generally applicable, and we anticipate they will form the basis for the “last mile” independent of the physical medium.

Programmable State-Variable Filter with Wide Frequency and Q Tuning Range

International Journal of Electronics and Electrical Engineering, 2014

This paper presents a state-variable bandpass filter with wide frequency range coverage and wide ... more This paper presents a state-variable bandpass filter with wide frequency range coverage and wide Q tuning range. The state-variable filter was chosen because it can be easily extended to a universal biquad filter structure [1]. A digital tuning technique with a novel Q-tuning algorithm was implemented in Verilog-A, and a real-time tuning of center frequency f c and Q was demonstrated. The technique is accurate as long as there is no phase error in the system. In the presence of phase error and for high Q filter requirements, tuning algorithm based on magnitude detection was demonstrated. A bandpass filter was simulated in 45nm CMOS technology using RF components for more accurate modeling of the fets. Filter simulation results showed frequency range coverage from 520MHz to 2.2GHz, and Q range from 2 to 400. For a filter with Q=33, simulation results showed a dynamic range of 55dB over a 3dB bandwidth at f c =1.5GHz. The current consumption of the designed filter is 75mA at 1.2V.

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In a communication system

Virtual loop carrier system

Digital data service system

Broadband communication system having a virtual circuit space switch

Dev Gupta

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