Papers by Dr Mamta Khosla
ASIC Design using Post Route ECO Methodologies for Timing Closure and Power Optimization
Zenodo (CERN European Organization for Nuclear Research), Sep 24, 2023
Analysis of CNTFET for SRAM Cell Design
Nanoscale Devices, 2018
Zenodo (CERN European Organization for Nuclear Research), Jun 15, 2022
Because of the increased complexity of designs in recent years, we now have multiple components o... more Because of the increased complexity of designs in recent years, we now have multiple components on a single chip that employ independent clocks, meaning that these clocks are not synchronized. As a result, problems with Clock Domain Crossing will occur, which, if not resolved, will proliferate and destroy the entire chip. Data crossing clock domains can cause a variety of problems, including as metastability and data loss, which can lead to the device failing completely. To overcome the clock domain crossing concerns, this work presents a dual flip flop synchronizer that employs TSPC logic and is based on the SOI technology. TSPC synchronizer when implemented in SOI technology gives outstanding results. It improves the rise time by 46.15 %, the fall time by 28.57 %, dissipates 24.23% less power, power delay product by a huge margin of 59.20 % when compared to its bulk CMOS counterpart. When implemented on a chip, it also takes up the least amount of space. All the circuits are designed in DSCH and simulated in Microwind software.
Hybrid channel estimation via fuzzy method over Nakagami-m fading in MIMO-OFDM system
Intelligent Circuits and Systems, 2021
Design and Challenges in TFET
CRC Press eBooks, Dec 5, 2023
Proceedings of International Conference on Women Researchers in Electronics and Computing
AIJR Proceedings, 2021
Go to AGRIS search. Proceedings of the International Conference on Women in Livestock Development... more Go to AGRIS search. Proceedings of the International Conference on Women in Livestock Development, May 20-22, 1990 HPI International Learning and Livestock Center, Perryville, Arkansas. ...
Pressure sensor based on hetero-stack L-shape TFET: simulation study
Physica Scripta
In this paper, the first-time-ever pressure sensor based on Hetero-stack L-shape TFET has been pr... more In this paper, the first-time-ever pressure sensor based on Hetero-stack L-shape TFET has been proposed and investigated through the SILVACO ATLAS TCAD tool. Owing to the hetero-stacking of Germanium material and Silicon material, an enhanced Ion and reduced sub-threshold swing is obtained by the proposed device leading to enhanced Pressure sensor sensitivity. The basic working principle of this proposed pressure sensor device is when pressure is applied to the diaphragm, the diaphragm bends which varies the metal-dielectric thickness of the oxide layer which further alters the electrical characteristics of the proposed pressure sensor. The diaphragm bendings considered in the study are 0, 1, 2, and 2.5 nm. The performance of the proposed pressure sensor device is analyzed through different electrical performance characteristics such as energy band diagrams, electric field, potential, Ion, sub-threshold swing, electron band-to-band tunneling rate, and various other analog/RF paramet...
CNTFETモデリングと低電力SRAMセルの設計【Powered by NICT】
IEEE Conference Proceedings, 2016
量子容量限界下でのバリスティック単層CNTFETのためのコンパクトなモデル【Powered by NICT】
Journal of Semiconductors, 2016
Investigation of a Double Gate Work-function Engineered Ge-Source Vertical TFET
量子力学効果を有する円筒ナノワイヤFETのサブスレッショルド電流解析モデルのためのGaussアプローチ【Powered by NICT】
Microelectronics Journal, 2016
GeSn based heterojunction double-gate tripple metal layer vertical TFET with enhanced DC and Analog/RF performance
Micro and Nanostructures
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Papers by Dr Mamta Khosla