Papers by Ernst Habekotte
Several driving configurations with low-voltage input control for a planar power switch
IEEE Journal of Solid-State Circuits, 1984
Several flip-flop control configurations for the coplanar CMOS power switch are proposed that lea... more Several flip-flop control configurations for the coplanar CMOS power switch are proposed that lead to a reduction of the on-chip power dissipation and input control voltage. Moreover, the switch becomes less sensitive to tolerances in the capacitive voltage divider controlling the gate of the output transistor. An acceptable tradeoff between chip area consumed by the flip-flop arrangement, reduction of the on-chip power dissipation, and input control voltage is possible. The on-chip low-voltage control circuitry is also described.
Domain-specific analog/digital integrated circuits in the gate-forest environment
[Proceedings] EURO ASIC `90
ABSTRACT
A process for the production of high voltage MOS transistors are MOS integrated circuits containing, as well as circuitry for switching power circuits using such high-voltage MOS transistors
High resolution phase shifter for a mm-wave adaptive null-forming array
In future dense 60 GHz wireless environments, cochannel interference (CCI) is a potential problem... more In future dense 60 GHz wireless environments, cochannel interference (CCI) is a potential problem that degrades the link quality. In a previous paper, a genetic algorithm (GA) assisted analog adaptive array was proposed for 60 GHz applications to mitigate the CCI. The array optimizes the leastsignificant-bits of the discrete weights on each receiver path, so that the nulls in the array pattern are adjusted to the interference direction and results in an improved signal-to-interference-plusnoise ratio (SINR). To facilitate the adaptive null forming, high resolution phase shifter is required. This paper presents a high resolution LO-path phase shifter implemented in 40-nm lowpower CMOS technology. The phase shift tuning is implemented by a tunable transmission line for fine tuning, in combination with a coarse tuning available from the frequency divider-by-4 operation in a sliding-IF front-end. The measured phase shift resolution is 5.4? between 44 GHz and 54 GHz, which offers about 6...
Schaltungsanordnung zum Schalten von Leistungsstromkreisen unter Verwendung von Hochspannungs-MOS-Transistoren
Eine Schaltungsanordnung zum Schalten von Leistungsstromkreisen unter Verwendung von Hochspannung... more Eine Schaltungsanordnung zum Schalten von Leistungsstromkreisen unter Verwendung von Hochspannungs-MOS-Transistoren enthalt einen mit seiner gesteuerten Strecke in Reihe zu einer Ausgangslast (beispielsweise 114) liegenden Hochspannungs-MOS-Schalttransistor (beispielsweise 110), eine an der Reihenschaltung aus gesteuerter Strecke des Schalttransistors (beispielsweise 110) und Ausgangslast (beispielweise 114) liegende zu schaltende Spannung (V) und einen an dieser Spannung liegenden kapazitiven Spannungsteiler (beispielsweise 111, 112), an dessen Abgriff das Gate des Schalttransistors (beispielsweise 110) liegt.
Robust null-forming in a mm-wave adaptive array with discrete phase shifting schemes
In future dense 60 GHz wireless environments, cochannel interference (CCI) is a potential problem... more In future dense 60 GHz wireless environments, cochannel interference (CCI) is a potential problem degrading the link quality. In [1], a genetic algorithm (GA) assisted analog adaptive array was proposed for 60 GHz applications to mitigate the CCI. The array optimizes the least-significant-bits of the discrete weights on each receiver path, so that the nulls in the array’s antenna pattern are adjusted to the interference direction resulting in an improved signal-to-interference-plus-noise ratio (SINR). In this paper, we propose two different phase shifting schemes in a 60 GHz sliding-IF receiver front-end, in LO path and in baseband respectively. High resolution is targeted for the GA assisted null-forming array. Simulations of the two sets of constellation points by the two schemes allow verifying the performance of the adaptive array. The results show that the SINR can be improved significantly and efficiently. This paper further demonstrates that the optimization is robust against...
A 300 Volt CMOS Coplanar Power Switch
ESSCIRC 80: 6th European Solid State Circuits Conference, 1980
A 300 V power switch using planar n-channel DMOS and p-channel pinched resistance transistors to ... more A 300 V power switch using planar n-channel DMOS and p-channel pinched resistance transistors to switch dynamically currents of 300 mA will be presented here.
A 300 Volt CMOS Coplanar Power Switch
Robotics and Computer-integrated Manufacturing, 1980
A 300 V power switch using planar n-channel DMOS and p-channel pinched resistance transistors to ... more A 300 V power switch using planar n-channel DMOS and p-channel pinched resistance transistors to switch dynamically currents of 300 mA will be presented here.
A 300 Volt CMOS Coplanar Power Switch
Robotics and Computer-integrated Manufacturing, 1980
A 300 V power switch using planar n-channel DMOS and p-channel pinched resistance transistors to ... more A 300 V power switch using planar n-channel DMOS and p-channel pinched resistance transistors to switch dynamically currents of 300 mA will be presented here.
Circuit arrangement for switching power circuits by using high-voltage MOS transistors
LINC architecture: A discussion
A discussion about the LINC architecture with alternative views on the power combiner merged with... more A discussion about the LINC architecture with alternative views on the power combiner merged with the antenna, reduction of gain mismatch with less impact of PA output impedance and broadband behavior.
Data Path for Lithography Apparatus
A Non-Isolated Power-Combining Antenna for Outphasing Radio Transmitters
IEEE Transactions on Antennas and Propagation, 2015
A MOS Switched Capacitor A/D Converter for a Capacitive Microtransducer
Esscirc 84 Tenth European Solid State Circuits Conference, Sep 1, 1984
This paper reports of a micropower high precision MOS switched capacitor converter for a capaciti... more This paper reports of a micropower high precision MOS switched capacitor converter for a capacitive microtransducer. The converter has a digital output which is linearly related to the applied physical quantity and which is compatible with microprocessor systems. The principle of measurement used in this converter will be presented. The realized testchip and its performance will be described.
Method of making integrated MOS circuits comprising high-voltage MOS transistors, and circuitry for switching power circuits by using such high-voltage MOS transistors
Proceedings of the IEEE, 1987
This paper is not intended to cover CMOS analog circuit design exhaustively. Yet, it describes ho... more This paper is not intended to cover CMOS analog circuit design exhaustively. Yet, it describes how much CMOS technology has been involved in analog circuit design despite the general opinion that CMOS is only suited for digital design. After some developments in the CMOS technology have been discussed, the analog building block scene is covered. The analog building blocks can roughly be divided into two subgroups: the switched-capacitor and the non-switched-capacitor building blocks. Following this subdivision different approaches are briefly looked at. Several tables conclude this review and indicate that new analog developments in CMOS circuit design are still to be expected. Next, the CAD tool development for analog CMOS is discussed, showing that there is still a lot to be done in the field of automated analog design. In conclusion, some ideas concerning analog CAD or, concerning CAD in a more general sense are described.
A 48 GHz 6-bit LO-path phase shifter in 40-nm CMOS for 60 GHz applications
2013 Proceedings of the ESSCIRC (ESSCIRC), 2013
ABSTRACT This paper presents a 48 GHz high resolution LO-path phase shifter implemented in 40-nm ... more ABSTRACT This paper presents a 48 GHz high resolution LO-path phase shifter implemented in 40-nm low-power CMOS technology. The full 360° phase shift tuning is implemented by a switched capacitor loaded tunable transmission line for fine tuning, in combination with a selection of one out of the N×45° phase steps available from the frequency divider-by-4 for coarse tuning. The measured phase shift resolution is 5.4° between 44 GHz and 54 GHz, which offers about 6-bit resolution. The chip area of the core circuitry is 550μm×260μm, and the total current consumption is 14.1 mA from a 1.2 V supply voltage.
A scalable baseband phase shifter with 12 GHz I/Q Mixers in 40-nm CMOS for 60 GHz applications
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
ABSTRACT
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Papers by Ernst Habekotte