Papers by Kamala Mahapatra
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017
FPGA based product development companies need third party IP cores to complete the product design... more FPGA based product development companies need third party IP cores to complete the product design time effectively and cost effectively. The one-time payment upfront licensing of IP cores is impractical for FPGA based products, which does not benefit either IP core vendors or product engineering companies. There is a need for good competitive pricing scheme which benefit product development companies and also secure the revenue to IP core vendors. The Pay-per-Device (PPD) pricing model scheme is a suitable pricing scheme. The PPD pricing schemes proposed in the past are complex in terms of communication between different stake holders and inflexible for product development companies to change the FPGA vendor. In this paper, we propose a PPD pricing scheme which overcomes the disadvantages of earlier techniques with better key management and without compromising the security of IP cores. The product development company can change the FPGA vendor at any time in the product life cycle by incorporating the proposed PPD pricing model. The proposed scheme is verified on Xilinx Artix-7 series FPGA.
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020
This paper presents an ultra-low-power solar energy harvesting system with a power management mod... more This paper presents an ultra-low-power solar energy harvesting system with a power management module (SEHS-PMU) for the Internet-of-Things (IoT) applications. The voltages generated are suitable for the IoT sensors used for smart cities as well as Internet-of-Medical-Things (IoMT) based biomedical applications. The SEHS-PMU is harvesting energy from the solar cell, and it can provide regulated voltages of 3.3 V, 1.8 V, 1 V, and 0.5 V. The harvesting mechanism leads to battery-less IoT, and is safe for the humanity and environment. Charge pumps (CP) are used as a boost and buck converter, which is suitable for monolithic integration. Low drop-out regulators (LDOs) are used for regulating the loads. A digital controller controls the selection of loads as per requirement for saving the power. The SEHS-PMU is designed in CMOS 180 nm technology library.
2010 International Conference on Power, Control and Embedded Systems, 2010
As the circuit complexity is increasing in demand for the more computations on a single VLSI chip... more As the circuit complexity is increasing in demand for the more computations on a single VLSI chip, low power VLSI design has become important specially for portable devices powered by battery. Digital camera is one of them where realtime image capturing, compression and storage of compressed image data is done. Most of the digital camera implement JPEG baseline algorithm to store highly compressed image in camera memory. In this paper we report and present low cost, low power and computationally efficient circuit design of JPEG for digital camera to get highly compressed image by exploiting removal of subjective redundancy from the image.
PUF-Based Secure Test Wrapper for SoC Testing
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018
The increased testability and observability due to test structures make chips vulnerable to side ... more The increased testability and observability due to test structures make chips vulnerable to side channel attacks. The intention of side channel attack are leaking secret keys used in cryptographic cores and getting access to trade related sensitive information stored in chips. Several countermeasures against test based side-channel attacks are available in research literature. One such countermeasure scheme is password based access protection to IEEE 1500 test wrapper, such that only an authentic user with valid password is allowed to access the test structures. IEEE 1500 is a core test standard for enabling the streamlined test integration and test reuse. The trust model of existing schemes assume outsourced assembly and test (OSAT) centre are completely trusted and design house will share secret keys to unlock the IEEE 1500 wrapper during testing. In this paper, we propose a Physical Unclonable Function (PUF) based technique incorporating challenge-response to support comprehensive test security in which there is no need for design house to share secret keys with untrusted OSAT centre to unlock the scan chains. The proposed scheme comes at the cost of reasonable area and performance overhead.
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017
Hardware Trojan (HT) is one of the well known hardware security issue in research community in la... more Hardware Trojan (HT) is one of the well known hardware security issue in research community in last one decade. HT research is mainly focused on HT detection, HT defense and designing novel HT's. HT's are inserted by an adversary for leaking secret data, denial of service attacks etc. Trojan benchmark circuits for processors, cryptography and communication protocols from Trust-hub are widely used in HT research. And power analysis based side channel attacks and designing countermeasures against side channel attacks is a well established research area. Trust-Hub provides a power based side-channel attack promoting Advanced Encryption Standard (AES) HT benchmarks for research. In this work, we analyze the strength of AES HT benchmarks in the presence well known side-channel attack countermeasures. Masking, Random delay insertion and tweaking the operating frequency of clock used in sensitive operations are applied on AES benchmarks. Simulation and power profiling studies confi...
Energy Efficient Ultra Low Power Solar Harvesting System Design with MPPT for IOT Edge Node Devices
2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2018
Towards designing an on-chip harvesting system design for IoT, an inductor free methodology is pr... more Towards designing an on-chip harvesting system design for IoT, an inductor free methodology is proposed. The solar system behavior is analyzed and proper control algorithm for maximum power point tracking (MPPT) is adopted. The control section monitors the computational circuit and recharging of the battery. Capacitor value modulation (CVM) is used for impedance matching. The conversion efficiency of the DC-DC converter is from 87% to 97%. The resulting output is in the range of 3-3.55V.
SEHS: Solar Energy Harvesting System for IoT Edge Node Devices
Advances in Intelligent Systems and Computing, 2020
Ultra-Low Power Solar Energy Harvester for IoT Edge Node Devices
2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2019
An Ultra-low power solar energy harvesting system (EHS) for IoT end node devices is presented in ... more An Ultra-low power solar energy harvesting system (EHS) for IoT end node devices is presented in this paper. To provide an uninterrupted power supply to IoT nodes is a challenge. The solar cell is used as an input source and this low input voltage is boosted by using the DC-DC converter. The charge pump is used as a voltage booster and the impedance matching between the solar cell and the converter is achieved through frequency tuning and capacitor value modulation. A hill-climbing technique is used for maximum power point (MPP) achievement. The EHS designed is self-sustainable and the output is in the range of 3-3.55 V with an input of 1-1.5 V. The EHS is designed in CMOS 90 nm technology library. The simulation results validate the proposed concept and the EHS is consuming a power of 22 µW, which is within the Ultra-low power range of IoT smart nodes.
2010 International Conference on Computational Intelligence and Communication Networks, 2010
The Discrete Tchebichef Moment (DTM) is a linear orthogonal transform which has higher energy com... more The Discrete Tchebichef Moment (DTM) is a linear orthogonal transform which has higher energy compactness property like other orthogonal transform. It is recently found applications in image analysis and compression. This paper proposes a new approach of fast zigzag pruning algorithm of 4x4 DTM coefficients. The principal ideal of the proposed algorithm is to make use of the distributed arithmetic and the symmetry property of 2-D DTM, which combines the similar terms of the pruned output. The multiplication terms are replaced by shift and add operations so as to reduce the computation. Equal number of zigzag pruned coefficients and block pruned coefficients are used for comparison to test the efficiency of our algorithm. Experimental method shows that our method is competitive with the block pruned method. Specifically for 3x3 block pruned case our method provides lesser computational complexity and has higher peak signal to noise ratio (PSNR).
Energy Perspectives in IoT Driven Smart Villages and Smart Cities
IEEE Consumer Electronics Magazine, 2021
The Internet-of-Things (IoT) consists of a large number of different and heterogeneous devices un... more The Internet-of-Things (IoT) consists of a large number of different and heterogeneous devices under one umbrella. Building a typical architecture for the devices used in IoT is a challenge due to the involvement of a vast number of devices, layers, protocols, middleware, and software. The sensors in IoT have to monitor the activities regularly, making the end node devices energy hungry. Traditional fixed batteries get drained out in limited time, requiring continuous replacement, thereby increasing the budget. This article focuses on consumer technologies in the perspective of IoT computing targeted for smart villages and smart cities. The article discusses security-by-design (SbD) concepts in the energy harvester technologies for sustainable and secured IoT with uninterrupted energy resource smart villages and smart cities. 
Uploads
Papers by Kamala Mahapatra