Papers by Philippe Benabes
Convertisseur sigma-delta
HAL (Le Centre pour la Communication Scientifique Directe), Feb 25, 2010
HAL (Le Centre pour la Communication Scientifique Directe), May 1, 2008
A methodology for the simulation of Continuous Time Sigma-Delta (CTΣ∆) converters is presented in... more A methodology for the simulation of Continuous Time Sigma-Delta (CTΣ∆) converters is presented in this paper. This method permits the simulation of Σ∆ modulators employing continuous-time filters using a fixed-step algorithm. The analysis method is based on the discretization of a continuous-time model and using a discrete simulator, which is more efficient than an analog simulator. In our analysis approach, each samplingperiod is divided into a fixed number of steps. This transformation is exact in term of Noise Transfer Function and asymptotically exact in term of Signal Transfer Function (the Signal Transfer Function of the model rapidly tends to the continuous time model transfer function when the number of steps increases). Moreover, the ideal step-size can be estimated from the bandwidth of the input signal.
Design of an ECG front-end considering ST segment distortion
JICS. Journal of integrated circuits and systems, Apr 30, 2022
Selecting the relevant layout techniques is a key point to obtain a high-performance integrated c... more Selecting the relevant layout techniques is a key point to obtain a high-performance integrated circuit. Most of the common layout techniques, beside allowing the improvement of performance, also leads to an area overhead. Moreover, this area overhead is generally not accurately evaluated. It is proposed in this review to analyze and to evaluate the surface versus performance trade-off in three types of circuits : digital, low-frequency and radiofrequency analog circuits. Each circuit is post-layout simulated using BiCMOS SiGe 55 nm technology from STMicroelectronics. The first analysis evaluates the surface, power consumption and speed trade-off in a digital circuit implementing a 16-bit gray counter, when selecting different combinations of gates from the B55 digital library. The second analysis focuses on the implementation of an accurate capacitor ratio for switched capacitor circuits and quantifies the surface versus accuracy performance. The third analysis evaluate the performance trade-off for six different layout techniques applied on a negative resistor required for a VCO.
A CMOS readout circuit for a low shunt resistance IR photo-detector
Specific Infrared (IR) detection systems are a solution for non-invasive monitoring of polymer ag... more Specific Infrared (IR) detection systems are a solution for non-invasive monitoring of polymer aging in electrical power plants. For such application, the target photo-detector has a low shunt impedance of 40Ω and produces a large photocurrent of 70 µA. This paper proposes a readout circuit designed in XFAB 0.18µm technology. Based on a CMDI architecture, a bi-cascode current mirroring direct injection circuit is proposed. It offers a 98 % charge injection efficiency. The structure performs the DC current cancellation and integrate the resulting current in a 20pF capacitance. The 20µs duration pulses are integrated with a linearity error of 0.01 %.
The demand for high resolution CMOS image sensors (CIS) is rising. Analog-to-digital converters (... more The demand for high resolution CMOS image sensors (CIS) is rising. Analog-to-digital converters (ADC) represent one of the major bottleneck of CIS. One of the candidates to overcome the existing limits is the column-parallel ADC. Column-parallel extended counting ADCs (EC-ADC) are able to reach high resolution thanks to their two-step conversion. However the EC-ADC area increases due to the two-step design. A solution is to use the same hardware twice to perform both steps. This paper proposes a 14-b, 100 kHz Nyquist frequency, two-step incremental Σ∆ (IΣ∆) analogto-digital converter suitable for column-parallel CIS. Several architectures with different modulator order are compared to determine the most promising one. The proposed architecture, compared to a one-step second order modulator, reduces the total oversampling ratio (OSR) from 150 to 60 to reach a resolution of 14-b. The operational transconductance amplifiers (OTA) is the most critical part in our ADCs. Its required DCgain is around 80 dB for a 120 MHz gain-bandwidth product (GBW). The ideal DNL and INL of our two-step IΣ∆ ADC are respectively +0.55/-0.6 LSB and +0.5/-0.5 LSB. This work achieves a SNDR of 89 dB when a full scale sinusoid of 100 kHz is applied.
2019 14th International Conference on Advanced Technologies, Systems and Services in Telecommunications (TELSIKS)
This paper presents a wideband compact phaser with a linear group delay, a key block to many Anal... more This paper presents a wideband compact phaser with a linear group delay, a key block to many Analog Signal Processing applications as Real-Time Fourier Transforming systems (RTFT). The phaser, designed in a 130 nm BiCMOS technology, presents a group delay dispersion of 3 ns, a layout area of only 30 µm by 330 µm and power consumption of 7.2 mW. Between 300 MHz and 2.5 GHz, the linearity error of the group delay is lower than 5%. The enhanced linearity of the group delay has been obtained thanks to an association of active first-order all-pass filters and active second-order all-pass filters. The benefit of using exclusively active components are the reduced layout area and the signal amplification achieved by the phaser.
2017 European Conference on Circuit Theory and Design (ECCTD), 2017
Comparators are a critical element of Analog-to-Digital converters (ADCs) intended to operate in ... more Comparators are a critical element of Analog-to-Digital converters (ADCs) intended to operate in a harsh environments such as the automotive. The influence of temperature on key comparator properties such as the delay must be well understood to maximize their speed. In this paper a Double-Tail latch analysis leads to an analytical expression for the delay to more accurately guide the design over a wide temperature range. The results given by this model agree well with spice postlayout simulation for a CMOS 0.18-μm SOI process, taking into consideration both process and temperature variations. To verify experimentally the correctness of the model we also propose a novel on-chip fully digital asynchronous architecture to measure the delay of the comparator, robust against extreme temperature variations.
Procédé et dispositif de traitement des signaux de sortie d'un capteur inductif de déplacement
Convertisseur sigma-delta
La présente invention concerne un convertisseur sigma-delta comportant une pluralité stages de tr... more La présente invention concerne un convertisseur sigma-delta comportant une pluralité stages de traitement sigma-delta, chaque étage de traitement comportant une cellule de traitement analogique (20i) et un quantificateur (30i), les étages de traitement tant relis ensemble de telle sorte qu'un étage de traitement traite au moins une partie du bruit d'un autre étage de traitement du convertisseur, au moins un étage de traitement comportant une cellule de traitement analogique (20i) passe-bas ou passe-haut d'ordre au moins deux ou passe-bande d'ordre au moins quatre
Convertisseur analogique-numérique delta-sigma
The invention relates on a sigma delta digital to analog converter, digitally sequenced by a cloc... more The invention relates on a sigma delta digital to analog converter, digitally sequenced by a clock, comprising a main line and a feedback line, the main line comprising: an input port, a linear filter G(z) and a multibit quantifier, a digital to analog converter, an output port, and the feedback line comprising a correcting memory table, able to process a correcting signal, and an adder able to subtract said correcting signal from an input signal, wherein the correcting memory table time cycle is k times greater than the clock time cycle.
A new algorithm for an incremental sigma-delta converter reconstruction filter
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019
Image sensors dedicated for the applications of the Earth observation require medium-speed and hi... more Image sensors dedicated for the applications of the Earth observation require medium-speed and high-resolution analog-to-digital converters (ADCs). For that purpose, an incremental sigma-delta analog-to-digital converter (IΣ∆ ADC) has been designed. Post-layout simulations highlighted a degradation in resolution caused by the circuit imperfections. Therefore, a digital correction has been investigated. This paper proposes a new reconstruction filter which takes into account not only the bit values of the modulator output sequence but also the occurrence of certain patterns. This technique has been applied to an incremental sigma-delta analog-to-digital converter in order to correct the conversion errors. Performing with 400 clock periods for each conversion cycle, the theoretical resolution is 15.4 bits. Post-layout simulation shows that a 13.5-bit resolution is obtained by using the classical optimal filter whereas a 14.8-bit resolution is obtained with our reconstruction filter.
A circuit-level inverter-based switched capacitor integrator model justified by post-layout simulations of an incremental sigma-delta converter
Analog Integrated Circuits and Signal Processing, 2021
International audienc
Electronics Letters, 2019
This study suggests several analogue bandwidth mismatch compensation techniques for time-interlea... more This study suggests several analogue bandwidth mismatch compensation techniques for time-interleaved analogue-to-digital converters. All the techniques adjust the equivalent on-resistance of the track and hold (T/H) under calibration. Simulations of a two-channel time interleaved T/H running at f s = 4 GHz shows the effectiveness of the proposed compensations.
Analog Integrated Circuits and Signal Processing, 2018
This paper presents a 14-bit Incremental Sigma Delta analog-to-digital converter suitable for col... more This paper presents a 14-bit Incremental Sigma Delta analog-to-digital converter suitable for column wise integration in a CMOS image sensor. A two step conversion is performed to improve the conversion speed. As the same Σ ∆ modulator is used for both steps, the overall complexity is reduced. Furthermore, the use of inverter-based amplifiers instead of operational transconductance amplifier facilitates the integration within the column pitch and decreases power consumption. MonteCarlo simulations have been done in order to validate the design of the inverter. The proposed ADC is designed in 0.18 µm CMOS technology. The simulation shows that for a 1.8 V voltage supply, a 20 MHz clock frequency and an oversampling ratio (OSR) of 70, the power consumption is 460 µW, achieving an SNDR of 85.4 dB. Keywords ADC • incremental • sigma-delta • CMOS Image Sensor • column-parallel • inverter-based
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014
A Compact Active Phaser with Enhanced Linearity of Group Delay for Analog Signal Processing
International audienc
A methodology for the simulation of bandpass continuous time sigma-delta (SD) modulators is prese... more A methodology for the simulation of bandpass continuous time sigma-delta (SD) modulators is presented in this paper. This method permits the simulation of SD modulators employing continuous-time filters using a fixed-step algorithm. The method is based on the discretization of a continuous-time model and the use of a discrete simulator, which is more efficient than an analog simulator. This transformation is exact in term of Noise Transfer Function and asymptotically exact in term of Signal Transfer Function (the Signal Transfer Function of the model rapidly tends to the continuous time model transfer function when the number of steps increases).
Analog bandwidth mismatch compensation for time-interleaved ADCs using FD-SOI technology
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017
This paper introduces an analog bandwidth mismatch compensation technique for Time-Interleaved An... more This paper introduces an analog bandwidth mismatch compensation technique for Time-Interleaved Analog-to-Digital Converters (TI-ADCs). It takes advantage of a Fully Depleted Silicon On Insulator (FD-SOI) technology to compensate for the bandwidth mismatch errors among channels. Our technique utilizes the body-effect to adjust the on-resistance of the sampling switch, by means of a 6-bit Digital-to-Analog-Converter (DAC). Simulations of a 2-channel TI-ADC running at fs= 4GHz shows the effectiveness of the correction. The spurious-free dynamic range (SFDR) is improved from 44.63 dB to 83.12 dB for a sine-wave just below the Nyquist frequency(fNyquist) of 2 GHz.
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Papers by Philippe Benabes