Papers by Robert Wisnieff
arXiv: Quantum Physics, 2019
In a recent paper, we showed that secondary storage can extend the range of quantum circuits that... more In a recent paper, we showed that secondary storage can extend the range of quantum circuits that can be practically simulated with classical algorithms. Here we refine those techniques and apply them to the simulation of Sycamore circuits with 53 and 54 qubits, with the entanglement pattern ABCDCDAB that has proven difficult to classically simulate with other approaches. Our analysis shows that on the Summit supercomputer at Oak Ridge National Laboratories, such circuits can be simulated with high fidelity to arbitrary depth in a matter of days, outputting all the amplitudes.
With the current rate of progress in quantum computing technologies, systems with more than 50 qu... more With the current rate of progress in quantum computing technologies, systems with more than 50 qubits will soon become reality. Computing ideal quantum state amplitudes for circuits of such and larger sizes is a fundamental step to assess both the correctness, performance, and scaling behavior of quantum algorithms and the fidelities of quantum devices. However, resource requirements for such calculations on classical computers grow exponentially. We show that deferring tensor contractions can extend the boundaries of what can be computed on classical systems. To demonstrate this technique, we present results obtained from a calculation of the complete set of output amplitudes of a universal random circuit with depth 27 in a 2D lattice of $7 \times 7$ qubits, and an arbitrarily selected slice of $2^{37}$ amplitudes of a universal random circuit with depth 23 in a 2D lattice of $8 \times 7$ qubits. Combining our methodology with other decomposition approaches found in the literature,...
Array tester for determining contact quality and line integrity in a TFT/LCD
Driving method and circuit for pixel multiplexing circuits
Method and apparatus for analog testing
Electroplating apparatus and four mask TFT array process with electroplated metal
Silicon Photonic Chip Optical Coupling Structures
Functional Glass Handler Wafer with Through Vias
A method of determining contact quality and line integrity in a TFT/LCD array tester
Method for testing a partially constructed electronic circuit
Method and apparatus for analog testing of thin film transistor arrays
Formation of alpha particle shields in chip packaging
Thin film transistor and multilayer film structure and manufacturing method of same
Display fabrication using modular active devices
Integrated prism sheet for improved viewing angle in direct view color filterless liquid crystal displays
A six-mask TFT-LCD process using copper-gate metallurgy
Journal of the Society for Information Display, 1997
ABSTRACT — A novel reduced mask process is used to fabricate high-resolution high-aperture-ratio ... more ABSTRACT — A novel reduced mask process is used to fabricate high-resolution high-aperture-ratio 10.5-in. SXGA (1280 × 1024) displays. The process uses copper gate-metallurgy with redundancy, without the need for extra processing steps. The resulting displays have 150-dpi color resolution, an aperture ratio of over 35%, and excellent image quality, making them the first high-resolution displays that are suitable for notebook applications.
Characterization of TFT/LCD arrays
Conference Record of the 1991 International Display Research Conference
Page 1. CHARACTERIZATION OF TFT/LCD ARRAYS Ronald R. T"an Lestie C. Jenkim Robert J.... more Page 1. CHARACTERIZATION OF TFT/LCD ARRAYS Ronald R. T"an Lestie C. Jenkim Robert J. Pd.stre Robert L. Wisnieff IBM Research Division TJ Watson Research Center P. 0. Box 704 Yodctown Heights, NY 10598 (914) 681-SS21 Abstract ...
Langmuir, 2003
The thin-film transistor (TFT) array of liquid-crystal displays (LCDs) comprises a number of meta... more The thin-film transistor (TFT) array of liquid-crystal displays (LCDs) comprises a number of metallic, semiconducting, and insulating layers, which need to be deposited and patterned accurately with very high yields on a (large) glass substrate. We are exploring how to fabricate the gate metal lines of the TFT array in an entirely new and potentially cost-effective waysby depositing the metal layer of the TFT array using electroless deposition (ELD) and by patterning the gates using microcontact printing (µCP). To achieve this goal, we separately explore first the plating conditions to deposit a gate metal on 15 in. glass substrates, and second the printing process to finally combine them later in the work. Here, we review in depth the metallization of the glass by ELD of NiB as gate material, and we demonstrate the patterning of the gate layer using a conventional photoengraving process (PEP, i.e., photolithography and wet etching). We selected NiB because this material can fulfill the conductivity requirements for making an SXGA (1280 pixels × 1020 pixels) display having a 157 pixel per inch resolution. Because ELD requires the presence of a catalyst on the substrate, we derivatized the glass by grafting 3-(2-aminoethylamino)propyltrimethoxysilane (EDA-Si) from an aqueous solution, which serves as linker between the glass and colloidal Pd/Sn particles. We identify the optimum conditions for the derivatization of the glass and to activate it with colloidal Pd/Sn in a uniform manner so as to electroless deposit high-quality NiB layers. We plated uniform NiB films of 120 nm thickness on both faces of 15 in. glass substrates, and we removed the NiB from one face of the substrate using HNO3 dissolved in water. The remaining NiB layer was patterned using a mask of photoresist and an etch bath comprising an aqueous solution of 3-nitrobenzenesulfonic acid (NBSA) and ethylenediamine (EDA) at pH ∼ 9. This etch system minimizes the galvanic coupling between the Pd/Sn particles and the NiB, and it enabled patterning the gates with an accuracy better than 1 µm. Annealing the NiB layer at 400°C reduces its specific resistivity from 25 to 13 µΩ cm, and the roughness and adhesion of the layer to the glass enable the plasma deposition of silicon nitride (SiN x) and amorphous silicon (a-Si) layers over the patterned array of gates. Building an array of TFTs for a SXGA display using the NiB as the gate layer yielded transistors with transfer and output characteristics similar to those fabricated using a conventional gate material. The work presented here may spur the introduction of novel surface chemistry processes into flat-panel-display factories.
IEEE Transactions on Electron Devices, 1989
Liquid-crystal displays addressed by thin-film transistors are subject to crosstalk associated wi... more Liquid-crystal displays addressed by thin-film transistors are subject to crosstalk associated with parasitic capacitances. An addressing technique is described that provides compensation for crosstalk, eliminating its visible effects. Each row-addressing time interval is subdivided into two intervals, one of which is used for normal data transfer into the row. During the other subinterval, all gates are inactive, and a compensation voltage is applied to each column that is complementary to the data voltage for the row being addressed. * Robert L. Wisnieff (M'89) was born in Yonkers, NY on March 27, 1958. He received the B.S. degree in mechanical engineering from Tufts University in 1980 and Ph.D. degree in applied physics from Yale University in 1986. Since 1986, he has been a Physicist at the IBM Thomas J. Watson Research Center, studying devices for active matrix displays.
IBM Journal of Research and Development, 1998
A 157-dot-per-inch, 262K-color, 10.5-in.diagonal, 1280 x 1024 (SXGA) display has been fabricated ... more A 157-dot-per-inch, 262K-color, 10.5-in.diagonal, 1280 x 1024 (SXGA) display has been fabricated using a six-masl(process with Cu or Al-alloy thin-film gates. The combination of high resolution and gray-scale accuracy has been shown to render color images and text with paperlike legibility. The low-resistivity gate metallization and trilayer-type TFTs with a channel length of 6-8 ju,m were fabricated with a six-mask process which is extendible to larger, higher-resolution displays. A combination of double-sided driving and active line repair was used so that open gate lines or data lines did not result in visible line defects. A flexible drive-electronics system was developed to address the display and characterize its performance under different drive conditions. ^Copyright 1998 by International Business Macliines Corporation. Copying in printed form for private use is permitted witliout payment of royalty provided tliat (1) eacli reproduction is done without alteration and (2) tlie
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Papers by Robert Wisnieff