Suman Datta

Silicon nano-transistors and breaking the 10 nm physical gate length barrier

Silicon nano-transistors for logic applications

Physica E-low-dimensional Systems & Nanostructures, Jul 1, 2003

Silicon transistors have undergone rapid miniaturization in the past several decades. Recently re... more Silicon transistors have undergone rapid miniaturization in the past several decades. Recently reported CMOS devices have dimensional scales approaching the "nano-transistor" regime. This paper discusses performance characteristics of a MOSFET device with 15 nm physical gate length. In addition, aspects of a non-planar CMOS technology that bridges the gap between traditional CMOS and the nano-technology era will be presented. It is likely that this non-planar device will form the basic device architecture for future generations of nano-technology.

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High-&lt;tex&gt;$kappa$&lt;/tex&gt;/Metal–Gate Stack and Its MOSFET Characteristics

IEEE Electron Device Letters, Jun 1, 2004

We show experimental evidence of surface phonon scattering in the high-dielectric being the prima... more We show experimental evidence of surface phonon scattering in the high-dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN metal-gate electrode is effective in screening phonon scattering in the high-dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other metal-gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel mobilities to close to those of the conventional SiO 2 /poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high-/metal-gate CMOS transistors with desirable threshold voltages.

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Advanced CMOS transistors in the nanotechnology era for high-performance, low-power logic applications

Advanced CMOS Transistors in the Nanotechnology Era for High-Performance, Low-Power Logic Applica... more

Advanced si and sige strained channel NMOS and PMOS transistors with high-k/metal-gate stack

Sustaining Moore's Law of scaling Si CMOS transistors will require not only shrinking the transis... more Sustaining Moore's Law of scaling Si CMOS transistors will require not only shrinking the transistor dimensions, but also introduction of new materials and structures. In the future, advanced high performance CMOS transistors are likely to incorporate highly strained Si and SiGe channel for enhanced carrier transport and high-Wmetal-gate stack for low gate leakage. This work describes the recent advances made in integrating strained Si and SiGe channel transistors with high-Wmetal-gate stack for future high performance, low power logic applications.

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Emerging silicon and non-silicon nanoelectronic devices: opportunities and challenges for future high-performance and low-power computational applications (invited paper)

Emerging Silicon and Non-Silicon Nanoelectronic Devices: Opportunities and Challenges for Future ... more

Compensating for induced strain in the channels of metal gate transistors

Tri-gate transistor device with stress incorporation layer and method of fabrication

Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned SI to SIGE conversion processes and structures formed thereby

Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate

Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials, 2002

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Advanced CMOS transistors in the nanotechnology era for high-performance, low-power logic applications

Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004.

Advanced CMOS Transistors in the Nanotechnology Era for High-Performance, Low-Power Logic Applica... more

High mobility Si/SiGe strained channel MOS transistors with HfO/sub 2//TiN gate stack

IEEE International Electron Devices Meeting 2003

We integrate strained Si channel with HfO2 dielectric and TiN metal gate electrode to demonstrate... more We integrate strained Si channel with HfO2 dielectric and TiN metal gate electrode to demonstrate NMOS transistors with electron mobility better than the universal mobility curve for Si02, inversion equivalent oxide thickness of 1.4nm @OT=lnm), and with three orders of magnitude reduction in gate leakage. To understand the physical mechanism that improves the inversion electron mobility at the Hf02/strained Si interface, we measure mobility at various temperatures and extract the various scattering components.

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Silicon nano-transistors and breaking the 10 nm physical gate length barrier

61st Device Research Conference. Conference Digest (Cat. No.03TH8663)

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Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)

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Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.

We have combined the benefits of the fully depleted TriGate transistor architecture with high-k g... more We have combined the benefits of the fully depleted TriGate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering. High performance NMOS and PMOS trigate transistors are demonstrated with I DSAT =1.4mA/um and 1.1mA/um respectively (I OFF =100nA/um, V CC =1.1V and L G =40nm) with excellent short channel effects (SCE) -DIBL and subthreshold swing, ∆S. The contributions of strain, the <100> vs. <110> substrate orientations, high-k gate dielectrics, and low channel doping are investigated for a variety of channel dimensions and FIN profiles. We observe no evidence of early parasitic corner transistor turn-on in the current devices which can potentially degrade I ON -I OFF and ∆S.

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Substrate band gap engineered multi-gate pMOS devices

Inducing strain in the channels of metal gate transistors

Non-planar MOS structure with a strained channel region

Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow

Block contact architectures for nanoscale channel transistors

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