Vinodh Gopal

Techniques to encode and compress fault dictionaries

Dictionary encoding schemes have not addressed the cost of reconstructing the dictionary during f... more Dictionary encoding schemes have not addressed the cost of reconstructing the dictionary during fault location. We show that by modifying a previously proposed dictionary encoding scheme only small portions of the information need be reconstructed during fault location. This provides a mechanism to reduce the number of secondary accesses during fault location. For pass-fail dictionaries, we present a simplified encoding scheme that reduces both the secondary storage requirement as well as the number of secondary accesses. A novel dictionary structure, known as hybrid dictionaries, which retains the full resolution with respect to modeled faults is presented. Heuristics to compute such dictionaries, its usefulness and how such dictionaries can be encoded for quick information retrieval are discussed

Accelerated Processing of Secure Email by Exploiting Built-in Security Features on the Intel EP80579 Integrated Processor with Intel QuickAssist Technology

Domain Keys Identified Mail (DKIM) is one of the widely used mechanisms by which email messages c... more Domain Keys Identified Mail (DKIM) is one of the widely used mechanisms by which email messages can be cryptographically signed, permitting a signing domain to claim responsibility for the release of an email into the mail stream. As the volume of emails exchanged becomes large, the software implementations of DKIM using OpenSSL library will become a limiting factor of performance due to the heavy computations involved. In this largely empirical work, we identify the computation intensive modules of DKIM and solve the performance issues by implementing their functions on COTS hardware. Our approach makes use of the Intel Embedded processor Tolapai (Intel EP80579) that has several built-in cryptographic functionalities, viz. security accelerators for bulk encryption, authentication, hashing and public/private key generation and digital signing. Experimental results show that an overall 50% acceleration can be achieved by transparently migrating the DKIM functionalities to hardware.

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34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms

A 9,296µm2 DEFLATE accelerator targeted for firmware decompression in battery-constrained IoT pla... more A 9,296µm2 DEFLATE accelerator targeted for firmware decompression in battery-constrained IoT platforms is fabricated in 14nm tri-gate CMOS, and operates over a wide supply range of 210-900m V. Dual-ALU block-adaptive Huffman decoder enables simultaneous evaluation of a pair of code-lengths with opportunistic skipping of non-existent symbols improving throughput by 34% to 1.65Gb/s at 750mV, 25°C, while in-line literal packing and fenced-record generation achieves 63% memory bandwidth reduction for LZ77 reconstruction. Absence of register file and CAM circuits result in a fully-synthesizable implementation enabling ultra-low voltage operation with peak energy-efficiency of 1.56Tbps/W and 34.4Mbps throughput at 22µW total power consumption measured at 310mV.

Intel HEXL

Modern implementations of homomorphic encryption (HE) rely heavily on polynomial arithmetic over ... more Modern implementations of homomorphic encryption (HE) rely heavily on polynomial arithmetic over a finite field. This is particularly true of the BGV, BFV, and CKKS HE schemes. Two of the biggest performance bottlenecks in HE primitives and applications are polynomial modular multiplication and the forward and inverse number-theoretic transform (NTT). Here, we introduce Intel® Homomorphic Encryption Acceleration Library (Intel® HEXL), a C++ library which provides optimized implementations of polynomial arithmetic for Intel® processors. Intel HEXL takes advantage of the recent Intel® Advanced Vector Extensions 512 (Intel® AVX512) instruction set to provide state-of-the-art implementations of the NTT and modular multiplication, measuring up to 7.2x single-threaded speedup over a native C++ baseline. Intel HEXL is available open-source at under the Apache 2.0 license and has been adopted by the Microsoft SEAL and PALISADE homomorphic encryption libraries. • Mathematics of computing → Mathematical software performance.

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A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS

A 10,790μm2 dynamic Huffman decoder targeted for DEFLATE header decompression in area and energy ... more A 10,790μm2 dynamic Huffman decoder targeted for DEFLATE header decompression in area and energy constrained IoT platforms is fabricated in 14nm Trigate CMOS. Ternary CAM (TCAM) assisted concurrent literal-length and distance tree generation, opportunistic code-skipping with register file tagging to leverage symbol sparsity, and 3-way forward-reverse-parallel Huffman decoding results in 300 cycle header processing latency, 2.4× faster than conventional serial decoding approach. Absence of custom circuits enables a fully synthesizable design operating over a wide supply range of 210-900mV with 895M codes/s throughput measured at 750mV, 25°C. Near-threshold voltage operation and clock power reduction with vector latch insertion provides peak energy-efficiency of 3.1pJ/code (5.9× higher than nominal) at 280mV, 15MHz operation with 32μW and 6μW total and leakage power consumption.

Data De-duplication and Event Processing for Security Applications on an Embedded Processor

Network security schemes generally deploy sensors and other network devices which generate huge v... more Network security schemes generally deploy sensors and other network devices which generate huge volumes of data, overwhelming the underlying decision making algorithms. An example is corporate networks employing intrusion detection systems where there is a deluge of alert data, confounding the computations involved in sensor information fusion and alert correlation. One way to obtain fast and real-time responses is to preprocess such data to manageable sizes. In this paper, we show that data deduplication using computationally efficient fingerprinting algorithms can provide real-time results. We present an algorithm which utilizes Rabin Fingerprinting/hashing scheme for the purpose of data de-duplication. We have implemented this algorithm on Intel Atom, which is a powerful, energy efficient embedded processor. Our study is intended to show that the relatively low performing embedded processors are capable of providing the needed computational support if they were to handle security functions in the field. When compared to the algorithmic performance on a high end system, viz. Intel Core 2 Duo processor, the positive results obtained make a case for using the Atom processor in networked applications employing mobile devices.

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Intel HEXL: Accelerating Homomorphic Encryption with Intel AVX512-IFMA52

arXiv (Cornell University), Mar 30, 2021

Modern implementations of homomorphic encryption (HE) rely heavily on polynomial arithmetic over ... more Modern implementations of homomorphic encryption (HE) rely heavily on polynomial arithmetic over a finite field. This is particularly true of the BGV, BFV, and CKKS HE schemes. Two of the biggest performance bottlenecks in HE primitives and applications are polynomial modular multiplication and the forward and inverse number-theoretic transform (NTT). Here, we introduce Intel® Homomorphic Encryption Acceleration Library (Intel® HEXL), a C++ library which provides optimized implementations of polynomial arithmetic for Intel® processors. Intel HEXL takes advantage of the recent Intel® Advanced Vector Extensions 512 (Intel® AVX512) instruction set to provide state-of-the-art implementations of the NTT and modular multiplication. On the forward and inverse NTT, Intel HEXL provides up to 7.2x and 6.7x single-threaded speedup, respectively, over a native C++ implementation. Intel HEXL also provides up to 6.0x single-threaded speedup on the element-wise vector-vector modular multiplication, and 1.7x single-threaded speedup on the element-wise vectorscalar modular multiplication. Intel HEXL is available open-source at under the Apache 2.0 license and has been adopted by the Microsoft SEAL and PALISADE homomorphic encryption libraries.

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Processeurs, Procédés, Systèmes et Instructions Pour Exponentiation Modulaire Sécurisée

A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS

2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2018

A 10,790μm2 dynamic Huffman decoder targeted for DEFLATE header decompression in area and energy ... more A 10,790μm2 dynamic Huffman decoder targeted for DEFLATE header decompression in area and energy constrained IoT platforms is fabricated in 14nm Trigate CMOS. Ternary CAM (TCAM) assisted concurrent literal-length and distance tree generation, opportunistic code-skipping with register file tagging to leverage symbol sparsity, and 3-way forward-reverse-parallel Huffman decoding results in 300 cycle header processing latency, 2.4× faster than conventional serial decoding approach. Absence of custom circuits enables a fully synthesizable design operating over a wide supply range of 210-900mV with 895M codes/s throughput measured at 750mV, 25°C. Near-threshold voltage operation and clock power reduction with vector latch insertion provides peak energy-efficiency of 3.1pJ/code (5.9× higher than nominal) at 280mV, 15MHz operation with 32μW and 6μW total and leakage power consumption.

323686 Fast Cryptographic Computation on IA Processors Via Function Stitching Executive Summary

Cryptographic applications often run more than one independent algorithm such as encryption and a... more Cryptographic applications often run more than one independent algorithm such as encryption and authentication. This fact provides a high level of parallelism which can be exploited by software and converted into instruction level parallelism to improve overall performance on modern super-scalar processors. We present fast and efficient methods of computing such pairs of functions on IA processors using a method called “function stitching”. Instead of computing pairs of functions sequentially as is done today in applications/libraries, we replace the function calls by a single call to a composite function that implements both algorithms. The execution time of this composite function can be made significantly shorter than the sums of the execution times for the individual functions and, in many cases, close to the execution time of the slower function. Function stitching is best done at a very fine grain, interleaving the code for the individual algorithms at an instruction-level gra...

34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), 2018

A 9,296µm2 DEFLATE accelerator targeted for firmware decompression in battery-constrained IoT pla... more A 9,296µm2 DEFLATE accelerator targeted for firmware decompression in battery-constrained IoT platforms is fabricated in 14nm tri-gate CMOS, and operates over a wide supply range of 210-900m V. Dual-ALU block-adaptive Huffman decoder enables simultaneous evaluation of a pair of code-lengths with opportunistic skipping of non-existent symbols improving throughput by 34% to 1.65Gb/s at 750mV, 25°C, while in-line literal packing and fenced-record generation achieves 63% memory bandwidth reduction for LZ77 reconstruction. Absence of register file and CAM circuits result in a fully-synthesizable implementation enabling ultra-low voltage operation with peak energy-efficiency of 1.56Tbps/W and 34.4Mbps throughput at 22µW total power consumption measured at 310mV.

A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS

2019 IEEE Custom Integrated Circuits Conference (CICC), 2019

A 82,000μm2 canonical Huffman encoder (CHE) for accelerating DEFLATE data compression is fabricat... more A 82,000μm2 canonical Huffman encoder (CHE) for accelerating DEFLATE data compression is fabricated in 14nm CMOS. Concurrent 2-stage sorting and binary tree construction, opportunistic skipping of missing symbols during Huffman code generation, and in-line length-limitation without recursive weight pruning eliminates serial data dependency in encoder pipeline enabling 179Mcode/s throughout at 650MHz operation measured at 0.75V, 25°C with 1150cycle total CHE latency, 17× faster than previously reported hardware accelerators. Unified datapath for literal-length and distance symbol processing, optimal register-file partitioning, shared address generation and reconfigurable ALU circuits maximize logic sharing resulting in fully synthesizable 330Kgate design that improves area-efficiency by 25% over prior-art. Absence of custom memory macros enables robust ultra-low voltage operation down to 220mV with 36pJ/code peak energy-efficiency (4.9× higher than nominal) measured at near-threshold voltage operation of 290mV.

High Performance DEFLATE Compression on Intel ® Architecture Processors

There is a critical need for lossless data compression in enterprise storage and applications suc... more There is a critical need for lossless data compression in enterprise storage and applications such as databases and web servers, which process huge amounts of data. DEFLATE is a widely used standard to perform lossless compression, and forms the basis of utilities such as gzip and libraries such as Zlib. In these applications, compression imposes a large computational burden on the servers, and they could benefit from a highly optimized implementation. This paper describes the performance characteristics of fast prototype implementations of DEFLATE compression, on Intel ® processors based on the 32-nm micro-architecture. As the performance of compression is data dependent, we report the performance on various industry standard corpora data sets. This paper describes the performance characteristics of fast prototype implementations of DEFLATE compression. In terms of throughput, we are able to perform DEFLATE compression at the aggregate rate of ~2.7 Gigabits/sec on the Calgary Corpu...

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Optimized Galois-Counter-Mode Implementation on Intel ® Architecture Processors

Executive Summary Galois-Counter-Mode (GCM) is a block cipher mode of operation that uses univers... more Executive Summary Galois-Counter-Mode (GCM) is a block cipher mode of operation that uses universal hashing over a binary Galois field to provide authenticated encryption. Galois Hash is used for authentication, and the Advanced Encryption Standard (AES) block cipher is used for encryption in counter mode of operation. This paper describes an optimized implementation of GCM benefiting from the PCLMULQDQ instruction and AES-NI set of instructions on Intel ® processors based on the 32-nm microarchitecture. This paper describes an optimized implementation of GCM that combines function stitching with novel polynomial multiplication methods. We are able to achieve performance of ~ 2.8 Cycles/byte on large buffers, on a single core of an Intel ® Core™ i5 650 processor, with Intel ® Hyper-Threading Technology. This represents a new record for GCM performance on Intel ® processors.

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Processeurs, Procédés, Systèmes et Instructions Pour Exponentiation Modulaire Sécurisée

Intel HEXL

Proceedings of the 9th on Workshop on Encrypted Computing & Applied Homomorphic Cryptography, 2021

Modern implementations of homomorphic encryption (HE) rely heavily on polynomial arithmetic over ... more Modern implementations of homomorphic encryption (HE) rely heavily on polynomial arithmetic over a finite field. This is particularly true of the BGV, BFV, and CKKS HE schemes. Two of the biggest performance bottlenecks in HE primitives and applications are polynomial modular multiplication and the forward and inverse number-theoretic transform (NTT). Here, we introduce Intel® Homomorphic Encryption Acceleration Library (Intel® HEXL), a C++ library which provides optimized implementations of polynomial arithmetic for Intel® processors. Intel HEXL takes advantage of the recent Intel® Advanced Vector Extensions 512 (Intel® AVX512) instruction set to provide state-of-the-art implementations of the NTT and modular multiplication, measuring up to 7.2x single-threaded speedup over a native C++ baseline. Intel HEXL is available open-source at under the Apache 2.0 license and has been adopted by the Microsoft SEAL and PALISADE homomorphic encryption libraries. • Mathematics of computing → Mathematical software performance.

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A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array

2019 Symposium on VLSI Circuits, 2019

A $33,464 \mu \mathrm {m}^{2}$ GZIP decompression accelerator is fabricated in 14nm CMOS, achievi... more A $33,464 \mu \mathrm {m}^{2}$ GZIP decompression accelerator is fabricated in 14nm CMOS, achieving industry-leading 20.5Gbps throughput. The design features out-of-order speculative Huffman decoder to break the fundamental serial dependency resulting in 69% higher decode throughput. The hybrid dual-path decoder provides $2.3 \times $ higher performance with multi-write enabled register-file array increasing decompression throughput by up to 41%. The arithmetic-architecture-circuit co-optimized design operates at 1.4GHz at 750mV, $25 ^{\circ}\mathrm {C}$ with peak measured energy-efficiency of 1.86pJ/code at 280mV, $2.7 \times $ higher than previously reported implementations.

Toward postquantum security for embedded cores

IEEE Micro, 2019

THE USE OF firmware agents-including their use to define the functionality of embedded cores-has ... more THE USE OF firmware agents-including their use to define the functionality of embedded cores-has proliferated on computer systems of all scales, especially servers. The agents are often not visible to the operating system as they independently perform configuration, monitoring, and certain control tasks. For example, the baseboard management controller (BMC) on server platforms runs a firmware stack (e.g., OpenBMC ()), has a network port, some peripherals on external buses (e.g., I2 C's, SPI, etc.), and storage. The BMC is effectively another full (but scaled-down) computing system on the server of which it is a component. While the BMC can directly affect the operation of a server (e.g., by controlling its power states), it does not interact with the OS. Its behavior is defined completely by its firmware.

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Processor-Based Apparatus and Method for Processing Bit Streams

Processor to Perform a Bit Range Isolation Instruction

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Papers by Vinodh Gopal

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