Yves BERTRAND

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Papers by Yves BERTRAND

Design, characterization & modelling of a CMOS magnetic field sensor

Proceedings of the conference on Design, automation and test in Europe - DATE '99, 1999

This paper presents both the design and the characterization of a full CMOS magnetic field sensor... more

format_quoteA complete methodology for characterizing electro-mechanical properties in CMOS processes is presented, comparing it with existing products.format_quote

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Low-noise ASIC and New Layout of Multipolar Electrode for both High ENG Selectivity and Parasitic Signal Rejection

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007

In order to extract and separate Action Potential (AP) signals according to their nerve fascicule... more In order to extract and separate Action Potential (AP) signals according to their nerve fascicule origins, we propose a new architecture of a multipolar cuff electrode and an optimized integrated acquisition circuit. The proposed electrode has a specific layout of a large number of poles in order to both reject parasitic signals, such as electromyogram and provide a maximum of spatial selectivity for ENG signals. For one channel to be recorded, we need to consider seven recording sites. A low-noise integrated circuit (ASIC) has been designed in order to perform this first step of analog processing on each set of seven considered poles

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Micromachined CMOS magnetic field sensors with low-noise signal conditioning

Technical Digest. MEMS 2002 IEEE International Conference. Fifteenth IEEE International Conference on Micro Electro Mechanical Systems (Cat. No.02CH37266)

Two original electromechanical magnetic sensors have been developed using fully industrial fabric... more Two original electromechanical magnetic sensors have been developed using fully industrial fabrication process that relies on bulk wet etching of CMOS dies. The first device uses the Lorentz force to actuate a Ushaped cantilever beam, while piezoresistive polysilicon gauges convert the beam bending into electrical signal. A 2µT sensor resolution has been achieved, making this device suitable for earth magnetic field measurement. The second prospective device uses a ferromagnetic material deposited on top of a free standing mechanical frame. Such approach leads in the design of a passive sensor that does not require any electrical power for actuation.

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A low-cost adaptive ramp generator for analog BIST applications

Proceedings 19th IEEE VLSI Test Symposium. VTS 2001

This paper presents a high-quality and area-efficient ramp generator to be used for on-chip testi... more This paper presents a high-quality and area-efficient ramp generator to be used for on-chip testing of analog and mixed-signal circuits. An original adaptive scheme is developed to palliate the inaccuracy of a basic ramp generator. As a result, the proposed adaptive ramp generator exhibits very good performances in terms of slope precision and ramp linearity while maintaining a low area overhead.

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Multipolar Electrode and Preamplifier Design for ENG-Signal Acquisition

Communications in Computer and Information Science, 2008

Cuff electrodes have several advantages for in situ recording ENG signal. They are easy to implan... more Cuff electrodes have several advantages for in situ recording ENG signal. They are easy to implant and not very invasive for the patient. Nevertheless, they are subject to background parasitic noise, especially the EMG generated by the muscles. We show that the use of cuff electrodes with large numbers of poles can increase their sensitivity and their selectivity with respect to an efficient noise rejection. We investigate several configurations and compare the performances of a tripolar cuff electrode versus a multipolar one in numerical simulation. One the other hand the use of cuff electrodes leads to the recording of the sum of the signals generated by all the axons within the nerve. This puts in evidence the need of signal separation techniques that require a great quantity of information. Again, we show that multipolar electrodes can solve this problem since poles can be switched one to another, provided that they are distributed along a regular tessellation. Finally, we present the structure of an ASIC preamplifier processing a spatial filtering to obtain the Laplacian of the potential rejecting low-frequency noise.

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Low-noise averaging amplifier dedicated to ENG recording with hexagonal cuff electrode

2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, 2008

In the case of spinal cord injurie, Functional Electrical Stimulation, which creates artificial m... more In the case of spinal cord injurie, Functional Electrical Stimulation, which creates artificial muscle contractions by electrical stimulation, has proven to be capable of helping to restore impaired biological functions. Sensory information from natural sensors going through afferent nervous fibers could be used as feedback information in a closed-loop FES system. In order to get this information, we propose a new multipolar cuff electrode with hexagonal patterns as well as first elements of signal processing and amplification. The hexagonal cuff electrode presented in this paper allows higher sensitivity and a better rejection of parasitic signals than a classical tripolar cuff electrode. The preamplifier associated with this electrode presents the asset to integrate, at the transistor levels, a rejection technique of parasitic signals based on the average. This technique is used to perform electroneurogram (ENG) recording. This integration at the transistor level allows us to reduce the noise level due to processing electronics during sensory information acquisition.

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Modeling gate oxide short defects in CMOS minimum transistors

Proceedings The Seventh IEEE European Test Workshop

In this paper a new model is proposed for Gate Oxide Short defects based on a non-split MOS trans... more In this paper a new model is proposed for Gate Oxide Short defects based on a non-split MOS transistor. Because the MOS is not split, this model allows to simulate minimum transistors in realistic digital circuits. The construction of the model is presented in details using a comprehensive and didactic approach. It is demonstrated that the electrical behavior of the proposed model matches in a satisfactory way the defective transistor behavior.

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On-chip analog output response compaction

Proceedings European Design and Test Conference. ED & TC 97, 1997

In this paper, we propose a technique for on-chip analog output response compaction in order to i... more In this paper, we propose a technique for on-chip analog output response compaction in order to implement self-test capabilities in analog and mixed-signal integrated circuits. The integration function is identified as a powerful analog compression scheme and an analog signature analyzer is proposed. The opamp-based implementation allows to define single and multiple-input versions. The multipleinput analyzer permits the monitoring of some extra internal nodes in addition to the classical output nodes, or the concurrent control of both voltage and current levels. This ability leads to an improvement of the circuit testability and consequently, the on-chip response evaluation gives a higher fault coverage than the off-chip one.

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Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing

SOC Design Methodologies, 2002

Using 100% industrial fabrication processes, the design and the fabrication of a monolithic CMOS ... more Using 100% industrial fabrication processes, the design and the fabrication of a monolithic CMOS MEMS magnetic field sensor, targeting noise reduction, are developed in this paper. The sensor is based on a resonant cantilever structure with optimized electronics for signal treatment and noise filtering in order to achieve competitive performances. With a final sensitivity of 350V rmJT and a 2/l T resolution, the system is able to measure earth natural magnetic field.

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A Multi-Mode Signature Analyzer for Analog and Mixed Circuits

VLSI: Integrated Systems on Silicon, 1997

In this paper a multi-mode signature analyser is proposed to be built into analog and mixed-signa... more In this paper a multi-mode signature analyser is proposed to be built into analog and mixed-signal integrated circuits. The analyser circuitry is based on analog integrators and can perform transient (with one integrator) and frequency (with two integrators) response compaction. The area overhead incurred can be very low, since the same signature analyser can be shared by several analog macros. Besides that, whenever integrators are available on-chip for functional purposes, they can be shared with the testing circuitry. Experiments carried on a Sallen-Key (transient response compaction) and on a biquad filter (frequency response compaction) showed that a very high coverage of catastrophic and pammetric faults can be obtained by using the proposed multi-mode signature analyser.

format_quoteThe proposed Multi-Mode Signature Analyzer uses two cascaded follower-integrators for versatile signal processing, enhancing response accuracy.format_quote

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Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europe

Second IEEE International Workshop on Electronic Design, Test and Applications

The launching of the EuNICE-Test project was announced two years ago at the first DELTA Conferenc... more The launching of the EuNICE-Test project was announced two years ago at the first DELTA Conference [1]. This project is now completed and the present paper describes the project actions and outcomes. The original idea was to build a long-lasting European Network for test engineering education using both test resource mutualisation and remote experiments. This objective is fully fulfilled and we have now, in Europe, five centres of competence able to deliver high-level and highspecialized training courses in the field of test engineering using a high-performing industrial ATE. All the centres propose training courses on digital testing, three of them propose mixed-signal trainings and three of them propose memory trainings. Taking into account the demand in test engineering, the network is planned to continue in a stand alone mode after project end. Nevertheless a new European proposal with several new partners and new test lessons is under construction.

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Test Engineering Education in Europe

IFIP — The International Federation for Information Processing

The present paper describes the CRTC and EuNICE-Test project actions and outcomes. The original i... more The present paper describes the CRTC and EuNICE-Test project actions and outcomes. The original idea was to build a long-lasting European Network for test engineering education using both test resource mutualisation and remote experiments. This objective is fully fulfilled and we have now, in Europe, five centers of competence able to deliver high-level and high-specialized training courses in the field of test engineering using a high-performing industrial ATE. All the centers propose training courses on digital testing, three of them propose mixed-signal trainings and three of them propose memory trainings. Taking into account the demand in test engineering, the network is planned to continue in a stand alone mode.

format_quoteTesting multimedia/telecom mixed-signal circuits can account for up to 50% of total product costs, indicative of significant economic challenges ahead.format_quote

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On-chip generator of a saw-tooth test stimulus for ADC BIST

SOC Design Methodologies, 2002

In the context of analog BIST for A-to-D converters, this paper presents an implementation of an ... more In the context of analog BIST for A-to-D converters, this paper presents an implementation of an on-chip ramp generator. It is demonstrated that the proposed original adaptive scheme allows the internal generation of a highly saw-tooth signal with a very precise control of the signal amplitude. In addition, the implementation of the adaptive ramp generator exhibits a very low silicon area.

format_quoteThe ramp generator produces a 3V amplitude symmetrical ramp with a duration of 0.1ms, suitable for histogram testing.format_quote

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Implementation of a linear histogram BIST for ADCs

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001

This paper validates a linear histogram BIST scheme for ADC testing. This scheme uses a time deco... more This paper validates a linear histogram BIST scheme for ADC testing. This scheme uses a time decomposition technique in order to minimize the required hardware circuitry. A practical implementation is described and the structure together with the operating mode of the different modules are detailed. Through this practical implementation, the performances and limitations of the proposed scheme are evaluated both in terms of additional circuitry and test time.

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Improving the efficiency of the oscillation-based test methodology for parametric faults

In this paper we introduce the use of Monte-Carlo (MC) simulations in order to facilitate OTM imp... more In this paper we introduce the use of Monte-Carlo (MC) simulations in order to facilitate OTM implementation and to evaluate fault coverage quantitatively even for parametric faults. Thanks to a case study, we demonstrate the contribution of MC simulations for both tolerance range and test efficiency determination.

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Electrical performances of a new multipolar micro-stimulator

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On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring

2008 14th IEEE International On-Line Testing Symposium, 2008

Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. ... more Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the variations of power/ground lines at the interface between noncoherent logic blocks in order to warn that a logic error is likely to occur. This information can then be used for any scheme that takes corrective actions.

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New implantable stimulator for the FES of paralyzed muscles

Proceedings of the 30th European Solid-State Circuits Conference

We propose a new implantable circuit for the internal Functional Electrical Stimulation (FES) of ... more We propose a new implantable circuit for the internal Functional Electrical Stimulation (FES) of motor nerves for paraplegic people. The circuit is designed to deliver precise calibrated stimulation pulses to specific multipolar electrodes. Several original design features have been developed to respond to the particular specifications imposed by safety constraints. In particular, the DAC has been thought to be fully monotonic and the output stage to ensure a passive and secure discharge of the safety capacitor. Also some tricky features have been added in order to improve the classical charge pump that generates on-chip high voltage.

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Reuse of existing resources for analog BIST of a switch capacitor filter

Proceedings of the conference on Design, automation and test in Europe, 2000

The objective of this paper is to discuss the possibility of reusing the existing hardware origin... more The objective of this paper is to discuss the possibility of reusing the existing hardware originally present in an analog application to implement test functions for a completely autonomous self-testable solution. In this first approach, a 8 th analog linear filter is used as an application example. The required modifications in the circuit are presented with the results in terms of area overhead and fault coverage.

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