Papers by khaled hayatleh
A bio-medical compatible self bias opamp in 45nm CMOS technology
2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)
In this paper a low power, high gain self bias opamp suitable for biomedical applications has bee... more In this paper a low power, high gain self bias opamp suitable for biomedical applications has been described. A novel trans conductance boosting technique is introduced without having any additional power consumption. A simple technique of biasing the opamp has been introduced for very low offset and without having any requirement for external reference circuit. A prototype of two stage amplifier design presented to verify the proposed technique and described its robustness across PVT variations by showing simulation results. The design is implemented in 45nm CMOS technology and simulated with Spectre. Simulation results show that the proposed opamp exhibits FOM of 625 and 2 times better than state of art. The circuit consumes 26uW from 1.5V supply and occupying 0.00282mm2 silicon area.
V2I Communications for Non-Signalised Intersection Control with Connected Vehicles
A 31 ppm/ $$^{\circ }$$ C Pure CMOS Bandgap Reference by Exploiting Beta-Multiplier
Communications in Computer and Information Science, 2019
Often Bandgap Reference performance limits the SNR of the bio-medical transceiver, hence sensitiv... more Often Bandgap Reference performance limits the SNR of the bio-medical transceiver, hence sensitivity. In this paper, conventional beta multiplier has been explored to design a new low voltage pure CMOS bandgap architecture, which avoids op-amps and resistors, hence very less mismatch and area. Line sensitivity has been improved by adding an extra gain stage in the circuit. The circuit implementation of the proposed technique was done in 65 nm TSMC CMOS technology to generate 460 mV output voltage. The minimum operating voltage of the circuit is 650 mV. Post-layout simulation results are as follows, 31 ppm/\(^{\circ }\)C temperature coefficient against temperature variation of −40\(^{\circ }\) to 125 \(^{\circ }\)C, 0.5% regulation against supply variation of 0.65−1 V and 0.42% PVT variation. Circuit draws 2.3 A current from 650 mV from power-supply. The proposed band gap reference occupies 0.00144 mm\(^{2}\) silicon area.
2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), 2017
In this paper a low opamp compensation technique suitable for the bio-medical application has bee... more In this paper a low opamp compensation technique suitable for the bio-medical application has been proposed and intuitive explained the existing compensation techniques. The Present technique relies on the passive damping factor control rather power hungry damping. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that 100dB dc gain, well compensated 25MHz bandwidth opamp while driving a 1pF capacitive load. Draws with 12uW power consumption from 1V supply and occupying 0.004875mm 2 silicon area.
2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2018
Integrated low noise neural amplifiers become recently practical in CMOS technologies. In this pa... more Integrated low noise neural amplifiers become recently practical in CMOS technologies. In this paper, a low noise OTA technique has been proposed while keeping the power consumption constant. A capacitive feedback, ac coupled 46dB amplifier with high pass cutoff frequency close to the 90Hz has been achieved. The proposed amplifier has been implemented in 65nm CMOS technology; at room temperature circuit consumes 323uA current from 1.2V power supply. The circuit occupies 2627um 2 silicon area.
Measurement of cell and bacterial activity using array-based ISFET Chemical Current-Conveyor in weak-inversion
2012 IEEE International Symposium on Circuits and Systems, 2012
The ISFET chemical current conveyor (CCCII+) was first reported by the authors at ISCAS 2008. In ... more The ISFET chemical current conveyor (CCCII+) was first reported by the authors at ISCAS 2008. In this paper a new application of the CCCII+ is presented, namely to provide a direct means of measuring cell and bacterial activity. The measurement system is based on an array of unmodified ISFET CCCII+ sensors each of which when operated in weak inversion gives an output corresponding to the time derivative of hydrogen ions. Combining each of the CCCII+ time derivative outputs in the array using the analog computational versatility of the CCCII+ current output stage provides a signal corresponding to cell and bacterial activity. The design has been fully simulated using Triple-well 0.18-μm CMOS technology and the results presented in this paper show that a viable system for direct measurement of cell and bacterial activity can be obtain, further confirming the utility of the CCCII+ for another biochemical sensing application.
A high-speed low-distortion voltage-follower
2006 3rd International Conference on Electrical and Electronics Engineering, 2006
Complementary symmetry is used extensively in the emitter-follower-based design of a voltage-foll... more Complementary symmetry is used extensively in the emitter-follower-based design of a voltage-follower which, over the temperature range -20 degC to +100 degC and for a quiescent power dissipation of some 60 mW, is gain-flat to within 0.1 dB up to 280 MHz. The new design has total harmonic distortion better than -60 dB for a lV-pk sinusoidal output signal across a 5 kOmega load, and exhibits a slew-rate better than 4800 V/mus
Cascode amplifier: A cautionary tale
2012 8th International Symposium on Communication Systems, Networks & Digital Signal Processing (CSNDSP), 2012
The cascode amplifier has the potential of providing high gain and high bandwidth simultaneously.... more The cascode amplifier has the potential of providing high gain and high bandwidth simultaneously. However, the design is not as intuitive as one might at first think. In this paper we present a detail analysis of the single cascode amplifiers. The relationship between gain and bandwidth is important. When used to achieve maximum bandwidth the voltage gain of the common-source stage is close to unity. However when the cascode is designed to obtain a high voltage gain, then the gain-bandwidth trade-off, typical in the common source amplifier, re-appears. This analysis is used to provide the basis for practical cascode amplifier design.
Comparing Dual Current-Conveyor Configurations
Journal of Circuits, Systems and Computers, 1996
Composite current-conveyors formed by connecting monolithic dual devices to operate as a single C... more Composite current-conveyors formed by connecting monolithic dual devices to operate as a single CCII are examined in detail. Comparisons between the two common configurations show that the net performance favors one or the other depending upon the particular application requirements.
Our goal is development of an algorithm capable of<br> predicting the directional trend of ... more Our goal is development of an algorithm capable of<br> predicting the directional trend of the Standard and Poor's 500 index<br> (S&P 500). Extensive research has been published attempting to<br> predict different financial markets using historical data testing on an<br> in-sample and trend basis, with many authors employing excessively<br> complex mathematical techniques. In reviewing and evaluating these<br> in-sample methodologies, it became evident that this approach was<br> unable to achieve sufficiently reliable prediction performance for<br> commercial exploitation. For these reasons, we moved to an out-ofsample<br> strategy based on linear regression analysis of an extensive<br> set of financial data correlated with historical closing prices of the<br> S&P 500. We are pleased to report a directional trend accuracy of<br> greater than 55% for tomorrow (t+1) in predicting the S&P 500.
Bandgap reference using 2 BJT devices are well explored in the literature. Usually, less number o... more Bandgap reference using 2 BJT devices are well explored in the literature. Usually, less number of BJT's would reduce the cost of the chip in modern CMOS technologies. A single BJT based reference was discussed here. V BE of the BJT has been used as CTAT voltage and a CMOS differential pair offset voltage based PTAT generation circuit used to generate zero temp coefficient reference. A prototype was developed in 45nm TSMC CMOS technology and post-layout simulationswere performed. Designed for a nominal voltage of 525mV with 10.2ppm/°C temperature coefficient. Its supply sensitivity is 0.4% and works with 1V power supply. The proposed solution consumes 51.8μW power from 1V power supply and occupies 2478 μm2 silicon area
Analog Integrated Circuits and Signal Processing, 2022
This paper introduces a Transimpedance Amplifier (TIA) design capable of producing an incremental... more This paper introduces a Transimpedance Amplifier (TIA) design capable of producing an incremental input resistance in the ohmic range, for input signals in the microampere range, such as are encountered in the design of instrumentation for electrochemical ampero-metric sensors, optical-sensing and current-mode circuits. This low input-resistance is achieved using an input stage incorporating negative feedback. In a Cadence simulation of an exemplary design using a 180nm CMOS process and operating with ±1.8V supply rails, the input resistance is 1.05ohms and the power dissipation is 93.6µW. The bandwidth, for a gain of 100dBohm, exceeded 9MHz. For a 1µA, 1MHz sinusoidal input signal the Total Harmonic Distortion, with this gain, is less than 1%. The input referred noise current with zero photodiode capacitance is 2.09pA/√Hz and with a photodiode capacitance of 2pF is 8.52pA/√Hz. Graphical data is presented to show the effect of a photodiode capacitance varying from 0.5pF to 2pF, when the TIA is used in optical sensing. In summary, the required very low input resistance, at a low input current level (µA) is achieved and furthermore a Table is included comparing the characteristics and a widely used Figure of Merit (FOM) for the proposed TIA and similar published low-power TIAs. It is apparent from the Table that the FOM of the proposed TIA is better than the FOMs of the other TIAs mentioned.
A wide bandwidth voltage-follower with low distortion and high slew rate
2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006
A symmetrical BJT voltage-follower is presented which combines low harmonic distortion and high s... more A symmetrical BJT voltage-follower is presented which combines low harmonic distortion and high slew rate. Unlike conventional class-AB voltage-followers the proposed design provides large signal swing, some plusmn4.5 V on a plusmn5 V power supply, as well as large positive and negative output currents for driving capacitive loads, resulting in high slew-rate capability. The circuit exhibits gain flatness of 0.1 dB at 728 MHz with an inductive behaviour coming in at higher frequencies. The operational range is -20degC to +100degC with a power consumption of 55 mW at room temperature.
… and Computers in …, 2008
This paper presents a novel voltage-follower, implemented in bipolar technology, based on a globa... more This paper presents a novel voltage-follower, implemented in bipolar technology, based on a global feedback technique. The evaluation of the circuit has been carried out using extra fast complimentary transistors and the biasing circuitry followed the same design philosophy. The proposed design exhibits very high input and very low output impedance, due to the feedback technique, for operating frequencies beyond 1GHz. The small-signal bandwidth achieved is higher than 3GHz, the output voltage swing is some ±3.2V, the offset voltage is around 200uV while the input offset current is just above 130nA. The new circuit achieved gain flatness to within 0.1dB up to 170MHz, featuring total harmonic distortion better than-65dB and intermodulation distortion of around-70dB, for capacitive loads up to 10pF. The operation of the novel design is specified from-20 o C to +100 o C and the power dissipation is some 52mW on a ±5V power supply.
Traditional BGR circuits require a 1.05V supply due to the VBE of the BJT. Deep submicron CMOS te... more Traditional BGR circuits require a 1.05V supply due to the VBE of the BJT. Deep submicron CMOS technologies are limiting the supply voltage to less than 940mV. Hence there is a strong motivation to design them at lower supply voltages. The supply voltage limitation in conventional BGR is described qualitatively in this paper. Further, a current mirror-assisted technique has been proposed to enable BGR operational at 0.82V supply. A prototype was developed in 65nm TSMC CMOS technology and post-layout simulation results were performed. A self-bias opamp has been exploited to minimize the systematic offset. Proposed BGR targeted at 450mV works from 0.82-1.05V supply without having any degradation in the performance while keeping the integrated noise of 15.2µV and accuracy of 23.4ppm/0C. Further, the circuit consumes 21µW of power and occupies 73*32µm2 silicon area
2017 Second International Conference on Electrical, Computer and Communication Technologies (ICECCT), 2017
In this paper a novel CMOS temperature and supply voltage independent current reference has been ... more In this paper a novel CMOS temperature and supply voltage independent current reference has been proposed. This design is based on the subtraction of two scaled version PTAT (proportional to absolute temperature) currents to provide a temperature independent current reference. The design was simulated with Spectre, and implemented in 45nm CMOS technology. Simulation results shows that the proposed current reference achieves temperature coefficient of 22ppm/ 0 C against temperature variation of-40 0 C-120 0 C and line sensitivity of 337ppm/V against supply variation of 0.6-1.8V, while consuming 135uW from 1.8V supply and occupying 5184um2 Keywords-current reference; PTAT; voltage independent; temperature independent; MOS.
2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2018
In this paper two stage Miller compensated opamp has been discussed qualitatively and quantitativ... more In this paper two stage Miller compensated opamp has been discussed qualitatively and quantitatively. A modification to the conventional compensation network has been proposed, which will reduce the capacitor size hence circuit area. Transfer function for the newly proposed solution has been derived and explained the results. A prototype was developed in 65nm TSMC CMOS technology and simulation results have been presented. Amplifier achieved 60dB low frequency gain, 12MHz bandwidth and 55 0 phase margin while consuming 650uW power from 1.2V power supply. Circuit occupies 5348um 2 silicon area.
A Single BJT 10.2 ppm/°C Bandgap Reference in 45nm CMOS Technology
2020 11th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2020
Bandgap reference using 2 BJT devices are well explored in the literature. Usually, less number o... more Bandgap reference using 2 BJT devices are well explored in the literature. Usually, less number of BJT's would reduce the cost of the chip in modern CMOS technologies. A single BJT based reference was discussed here. VBE of the BJT has been used as CTAT voltage and a CMOS differential pair offset voltage based PTAT generation circuit used to generate zero temp coefficient reference. A prototype was developed in 45nm TSMC CMOS technology and post-layout simulationswere performed. Designed for a nominal voltage of 525mV with 10.2ppm/°C temperature coefficient. Its supply sensitivity is 0.4% and works with 1V power supply. The proposed solution consumes $51.8\mu \mathrm{W}$ power from 1V power supply and occupies $2478\ \mu \mathrm{m}^{2}$ silicon area.
Journal of Circuits, Systems and Computers, 2019
This paper describes a high-performance impedance measurement circuit for the application of skin... more This paper describes a high-performance impedance measurement circuit for the application of skin impedance measurement in the early detection of skin cancer. A CMRR improvement technique has been adopted for OTAs to reduce the impact of high-frequency common mode interference. A modified three-OTA instrumentation amplifier (IA) has been proposed to help with the impedance measurement. Such systems offer a quick, noninvasive and painless procedure, thus having considerable advantages over the currently used approach, which is based upon the testing of a biopsy sample. The sensor has been implemented in 65[Formula: see text]nm CMOS technology and post-layout simulations confirm the theoretical claims we made and sensor exhibits sensitivity. Circuit consumes 45[Formula: see text]uW from 1.5[Formula: see text]V power supply. The circuit occupies 0.01954[Formula: see text]mm2 silicon area.
Wideband current-mode absolute value circuits
ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)
Two wideband current-mode absolute value, or precision full-wave rectifier (PFWR), circuits have ... more Two wideband current-mode absolute value, or precision full-wave rectifier (PFWR), circuits have been designed and developed. They are transistor level based designs, ideally suited for ASIC realisation. The two different, architecture circuits are described. In the first design a comparator is used to control a current-steering circuit to achieve the required unipolar output response. The topology of the circuit exhibits high speed performance with minimum transients. The second design is a development from the first. The circuit has lower overall complexity and provides enhanced performance. It is based on an emitter-coupled common-collector, with a NPN Quasi-Darlington dynamic buffer. Both techniques show promising performance in terms of operating speed.
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Papers by khaled hayatleh