A Sub-${\mu}$W 22-kHz CMOS Oscillator for Ultra Low Power Radio
Journal of the Institute of Electronics Engineers of Korea, 2010
A sub-W CMOS Wien-Bridge oscillator for ultra low power (ULP) radio applications is presented. Th... more A sub-W CMOS Wien-Bridge oscillator for ultra low power (ULP) radio applications is presented. The Wien-Bridge oscillator is based on an non-inverting opamp amplifier with a closed-loop gain as a means of providing necessary loop gain. An additional RC network provides appropriate phase shift for satisfying the Barkhausen oscillation condition at the given frequency of 1/(). In this design, we propose a novel loop gain control method based on a variable capacitor network instead of a rather conventional variable resistor network. Implemented in CMOS, the oscillator consumes only 560 nA at the oscillation frequency of 22 kHz.
Design considerations for bluetooth low energy CMOS RF transceivers for IoT
Bluetooth low energy (BLE) is one of the key wireless connectivity standards for future IoT era. ... more Bluetooth low energy (BLE) is one of the key wireless connectivity standards for future IoT era. In this work, the BLE standard specifications are investigated to derive the required RF transceiver specifications. Also, architectures and design trends of BLE RF transceivers are examined. With those design considerations taken into account, an optimum transceiver architecture is introduced with key target performance parameters.
A 24 GHz millimeter-wave direct-conversion radio-frequency (RF) receiver with wide-range and prec... more A 24 GHz millimeter-wave direct-conversion radio-frequency (RF) receiver with wide-range and precise I/Q mismatch calibration is designed in 65 nm CMOS technology for radar sensor applications. The CMOS RF receiver is based on a quadrature direct-conversion architecture. Analytic relations are derived to clearly exhibit the individual contributions of the I/Q amplitude and phase mismatches to the image-rejection ratio (IRR) degradation, which provides a useful design guide for determining the range and resolution of the I/Q mismatch calibration circuit. The designed CMOS RF receiver comprises a low-noise amplifier, quadrature down-conversion mixer, baseband amplifier, and quadrature LO generator. Controlling the individual gate bias voltages of the switching FETs in the down-conversion mixer having a resistive load is found to induce significant changes at the amplitude and phase of the output signal. In the calibration process, the mixer gate bias tuning is first performed for the ...
A 30-GHz CMOS LC VCO with Optimal Tail Filter Considering Tail FET's Output Resistance
2022 17th European Microwave Integrated Circuits Conference (EuMIC)
A 55-GHz Highly Linear Direct-Conversion RF Transmitter in 40 nm CMOS
2022 17th European Microwave Integrated Circuits Conference (EuMIC)
A 28GHz Direct Conversion Receiver in 65nm CMOS for 5G mmWave Radio
2019 International SoC Design Conference (ISOCC), 2019
This paper presents a direct-conversion zero-IF receiver front-end circuit for 28-GHz 5G mobile c... more This paper presents a direct-conversion zero-IF receiver front-end circuit for 28-GHz 5G mobile communications. The RF receiver is composed of LNA, quadrature downconversion mixer, wideband 50-ohm driving buffer, and I/Q generation LO buffer. The low-noise amplifier is designed in two-stage, in which the first cascode stage performs the single-to-differential conversion by using a transformer load. The mixer is a gilbert-cell active type. The 50-ohm driving buffer performs the differential-to-single conversion for test interface purpose. An external LO signal is fed to a RC polyphase filter, and splits into differential I/Q LO signals. Designed in 65nm CMOS process, extensive electromagnetic simulations after chip layout are carried out to evaluate the performances. The full receiver dissipates 90 mW from a 1.2-V supply. The Rx full-path gives the gain of +27.4 dB, noise figure of 4.6 dB, 1-dB input compression point of -38 dBm, and the baseband channel bandwidth of 1 GHz. The die size is 2 mm2including RF pads.
Design considerations for bluetooth low energy CMOS RF transceivers for IoT
2016 URSI Asia-Pacific Radio Science Conference (URSI AP-RASC), 2016
Bluetooth low energy (BLE) is one of the key wireless connectivity standards for future IoT era. ... more Bluetooth low energy (BLE) is one of the key wireless connectivity standards for future IoT era. In this work, the BLE standard specifications are investigated to derive the required RF transceiver specifications. Also, architectures and design trends of BLE RF transceivers are examined. With those design considerations taken into account, an optimum transceiver architecture is introduced with key target performance parameters.
Reduction of parasitic capacitance in heterojunction bipolar transistor and its monolithic integration with field effect transistor = 이종접합 바이폴라 트랜지스터의 성능향상과 전계효과 트랜지스터와의 집적에 관한 연구
A millimeter-wave direct-conversion radio-frequency (RF) transmitter requires precise in-/quadrat... more A millimeter-wave direct-conversion radio-frequency (RF) transmitter requires precise in-/quadrature-phase (I/Q) mismatch calibration and dc offset cancellation to minimize image rejection ratio (IRR) and LO feedthrough (LOFT) for ensuring satisfactory output spectral purity. We present a 28-GHz CMOS RF transmitter with an improved calibration technique for fifth generation (5G) wireless communication applications. The RF transmitter comprises a baseband amplifier, quadrature up-conversion mixer, power amplifier driver, and quadrature LO generator. The I/Q amplitude mismatch is calibrated by tuning the gate biases of the switching stage FETs of the mixer, the I/Q phase mismatch is calibrated by tuning the varactor capacitances at the LC load of LO buffer, and the dc offset is cancelled by tuning the body voltages of the differential-pair FETs at the baseband amplifier. The proposed technique provides precise calibration accuracy by employing mV-resolution tuning voltage generation v...
Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS
2017 International SoC Design Conference (ISOCC), 2017
A fractional-N PLL synthesizer is designed in 65 nm CMOS general process for Bluetooth low-energy... more A fractional-N PLL synthesizer is designed in 65 nm CMOS general process for Bluetooth low-energy applications. For low-power consumption, the PLL synthesizer is designed in a single 1-V supply. The tuning range of PLL Synthesizer is 1.9–2.7 GHz to cover the ISM band for 1/5-fRF sliding-IF receiver. The simulated VCO phase noises at 1 MHz offset are −110 and −120 dBc/Hz at 2.7 and 1.9 GHz, respectively. With a fast VCO frequency calibration process included, the total lock time of the synthesizer is 12 μs. The synthesizer dissipates 3 mW from 1 V supply voltage.
JSTS:Journal of Semiconductor Technology and Science, 2007
A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile b... more A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65 %. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in 0.18-µm CMOS, the PLL covers 154 ~ 303 MHz (VHF-III), 462 ~ 911 MHz (UHF), and 1441 ~ 1887 MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is-96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.
The Journal of Korean Institute of Electromagnetic Engineering and Science, 2015
In this paper, a wireless video streaming system is designed and implemented for TV white space a... more In this paper, a wireless video streaming system is designed and implemented for TV white space applications. It consists of a RF transceiver module, a digital modem, a camera, and a LCD screen. A VGA resolution video is captured by a camera, modulated by modem, and transmitted by RF transceiver module, and finally displayed at a destination 2.6-inch LCD screen. The RF transceiver is based on direct-conversion architecture. Image leakage is improved by low pass filtering LO, which successfully covers the TVWS. Also, DC offset problem is solved by current steering techniques which control common mode level at DAC output node. The output power of the transmitter and the minimum sensitivity of the receiver is +10 dBm and-82 dBm, respectively. The channel bandwidth is tunable among 6, 7 and 8 MHz according to regulations and standards. Digital modem is realized in Kintex-7 FPGA. Data rate is 9 Mbps based on QPSK and 512ch OFDM. A VGA video is successfully streamed through the air by using the developed TV white-space RF communication module.
Abstract-A CMOS direct conversion transmitter for IEEE 802.22 cognitive radio applications is pre... more Abstract-A CMOS direct conversion transmitter for IEEE 802.22 cognitive radio applications is presented. In-band harmonic distortions are effectively suppressed across the full TV band by exploiting single-conversion dual-path architecture with integrated harmonic rejecting ...
2007 IEEE Asian Solid-State Circuits Conference, 2007
A fractional-N frequency synthesizer with a fractional bandwidth of 67 % for UHF/VHF-band mobile ... more A fractional-N frequency synthesizer with a fractional bandwidth of 67 % for UHF/VHF-band mobile broadcasting tuners is presented. A novel linearized coarse tuned VCO with a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth. The proposed technique successfully reduces the variation of K VCO and per-code frequency step by 2.7 and 2.1 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) structure is employed for high speed operation, low power consumption, and small silicon area. Implemented in 0.18-μm CMOS, the PLL covers 154 ~ 303 MHz (VHF) and 462 ~ 911 MHz (UHF) with a single VCO. The integrated phase noise is 0.807 and 0.910 degree for the integer-N and fractional-N modes, respectively, at 827.5-MHz output frequency. The in-band noise at 1 kHz offset is-95 dBc/Hz in the integer-N mode and degraded only by 3.8 dB in the fractional-N mode. I.
Investigation of forward body bias effects on TSPC RF frequency dividers in 0.18 μm CMOS
2008 International SoC Design Conference, 2008
Effects of forward body biasing (FBB) is investigated as an effective mean of on-chip scaling of ... more Effects of forward body biasing (FBB) is investigated as an effective mean of on-chip scaling of power consumption and operating speed in CMOS true single phase clock (TSPC) RF frequency divide-by-2 circuits. Through extensive dc and RF simulations in 0.18 mum CMOS, the effects of the forward body bias on the threshold voltage, propagation delay, and current dissipation are examined. Then, it is shown that only with the FBB voltage of 0.2 V, the divide-by-2 circuits achieves 22% and 21% improvements in the maximum operating speed while only at the cost of 15% and 32% more current dissipation for TSPC and extended TSPC (E-TSPC) type logics, respectively. We believe that the forward body biasing technique is instrumental in realizing on-chip on-the-fly scalable TSPC dividers for low power applications.
A 54–862 MHz CMOS direct conversion transceiver for IEEE 802.22 cognitive radio applications
A CMOS single-chip transceiver IC is developed for IEEE 802.22 cognitive radio applications. Over... more A CMOS single-chip transceiver IC is developed for IEEE 802.22 cognitive radio applications. Over the 54 to 862 MHz ultra wideband, the in-band harmonic distortions of the transmitter and the unwanted harmonic mixing of the receiver are effectively suppressed by exploiting the dual-path direct-conversion architecture. A seamless coverage of the full band is achieved by employing a fractional-N PLL with
Fast Estimation of Spectral Spreading in GSM OPLL Transmitters Based on Folding Effects Analysis in Quadrature Phase Modulator
IEEE Transactions on Microwave Theory and Techniques, 2008
ABSTRACT
A 17-GHz Push–Push VCO Based on Output Extraction From a Capacitive Common Node in GaInP/GaAs HBT Technology
IEEE Transactions on Microwave Theory and Techniques, 2006
This paper presents a new push-push voltage-controlled oscillator (VCO) technique that extracts a... more This paper presents a new push-push voltage-controlled oscillator (VCO) technique that extracts a second harmonic output signal from a capacitive common node in a negative-gm oscillator topology. The generation of the second harmonics is accounted for by the nonlinear current-voltage characteristic of the emitter-base junction diode causing: 1) significant voltage clipping and 2) different rise and fall times during the switching operation of the core transistors. Comparative investigations show the technique is more power efficient in the high-frequency region than a conventional push-push technique using an emitter common node. A prototype 17-GHz VCO realized in GaInP/GaAs HBT technology produces an output power of -6dBm and a phase noise of -110.4dBc/Hz at 1-MHz offset, which is equivalent to a VCO figure-of-merit of -184.3dBc/Hz, while drawing 4.38 mA from a 3.0-V supply
A 54–862-MHz CMOS Transceiver for TV-Band White-Space Device Applications
IEEE Transactions on Microwave Theory and Techniques, 2011
A 54-862-MHz single-chip CMOS transceiver with a singleLC voltage-controlled oscillator (VCO) fra... more A 54-862-MHz single-chip CMOS transceiver with a singleLC voltage-controlled oscillator (VCO) fractional- synthe- sizer is developed for TV-band white-space communications and cognitive radio applications. The transceiver is based on a single- conversion zero-IF architecture with integrated harmonic filtering capability. A combined harmonic rejection mixer and coarse RF tracking filter significantly lessens the in-band harmonic emission problem in the transmitter, as
Uploads
Papers by Hyunchol Shin