Low power register file architecture for application specific DSPs
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002
In this paper, an architecture for register files suited for synthesiz- able DSP cores is propose... more In this paper, an architecture for register files suited for synthesiz- able DSP cores is proposed. The principal focus is on the imple- mentation of DSP algorithms with several identical channels, used in e.g. stereo audio, filterbanks or network IC implementations. Nevertheless, it is shown that the result of this work can be ex- tended to many single channel applications
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Papers by J. Nossek