Arteris

What does a "golden specification" look like in the era of AI, chiplets, and heterogeneous computing? According to the experts featured in Semiconductor Engineering's latest article, it has become much more than a design document. It is evolving into a machine-readable, system-level foundation that connects architecture, implementation, and verification across the silicon lifecycle. Guillaume Boillet has contributed his perspective on why modern specifications must account for system-level behavior across heterogeneous dies, with the network-on-chip playing an increasingly central role. Read the full article for an insightful discussion on where chip verification is headed: https://lnkd.in/dXFQ55aM #verification #semiconductors #innovation #chiplet #NoC #AI #Arteris

Numerous conversations shaping the future of semiconductor design are happening at DAC, The Chips to Systems Conference, and Arteris will be there to help you navigate complexity. Join the Arteris team for two expert panel discussions exploring some of the industry's most important topics: from building security into the silicon lifecycle to navigating the strategic decisions shaping the future of AI chip development. 🎤 From RTL to Reality: Building Security into the Silicon Lifecycle 📅 Monday, July 27 🕑 2:00 PM-2:45 PM 📍 DAC Pavilion 🎤Build vs Buy: Who Owns the Intelligence Behind Tomorrow's Chips? 📅 Tuesday, July 28 🕑 3:00 PM-3:45 PM 📍 DAC Pavilion Join Michal Siwinski from Arteris alongside industry experts as they discuss how engineering teams can identify and address hardware security risks earlier in development to build more resilient silicon. While at DAC, be sure to also stop by Booth #833 to meet the Arteris team. Whether you are designing for AI, automotive, HPC, or other advanced applications, let us show you how our solutions help engineering teams connect, integrate, and secure increasingly complex designs. Learn more about what we are showcasing at DAC here: https://lnkd.in/gG5pbvuA We look forward to seeing you in Long Beach, CA! #ChipsToSystemsConference26 #semiconductors #AI #chiplets #SoC #innovation #Arteris

📰 NEWS ALERT: Arteris Deployed by Speedata.io for Data Center Compute As organizations process ever-growing volumes of data, efficient movement of information across increasingly complex semiconductor architectures has become essential to delivering high-performance analytics infrastructure. We are excited to announce that Speedata has deployed Arteris FlexNoC technology in its purpose-built Analytics Processing Unit (APU), enabling large-scale data analytics workloads with scalable, high-performance on-chip communication. Rafi Shalom, CTO, Chief Architect & Co-founder of Speedata 🎤 : "AI inference is transforming every technology stack and industry at speed and scale, with real-time data analytics, accelerated by Speedata APU, as the catalyst. Arteris FlexNoC has been an important enabling technology across both Callisto and our next-generation Andromeda APU, giving our engineering teams the flexibility to focus on innovation in accelerated data analytics while relying on a proven interconnect foundation." Read the full announcement: https://hubs.ly/Q04p7_4F0 #AI #DataCenters #semiconductors #NoC #SoC #FlexNoC #innovation #Arteris

Tune in to hear the conversation between Amelia Dalton and our very own Jason Oberg about hardware security in the #AI Era 🎧

What will it take to bring Physical AI from concept to real-world deployment? Watch Gabriel Yin of Arteris join EE Times | Electronic Engineering Times' Nitin Dahad, Sudipto Bose of GlobalFoundries, and Mamoru Nakano of Tenstorrent for an engaging discussion on the key challenges and opportunities shaping the future of Physical AI at the recent "Physical AI is Agentic AI at the Edge" event in Taipei. ➡️ See the video here: https://lnkd.in/ePN_4e48 #EETimes #MIPS #Arteris #semiconductors #innovation #AI #COMPUTEX

How do you build AI processors that can scale with tomorrow's workloads? In this interview with Aniket Saha, VP of Product Management, Tenstorrent, discover how they use Arteris NoC IP to connect heterogeneous compute, support chiplet-based architectures, and enable the high-performance data movement required for advanced AI systems. Watch the video to learn how FlexNoC and Ncore helped provide the scalability, flexibility, and performance foundation behind Tenstorrent's next-generation designs. 📌 Explore the full case study for a deeper look at the design challenges, solution, and successful results: https://hubs.ly/Q04prSMg0 #AI #semiconductors #SoC #chiplets #Noc #HPC #Arteris #Tenstorrent

📰 NEWS ALERT: Arteris Expands Partnership with Arm to Accelerate Semiconductor Cybersecurity Building on five years of collaboration and successful use on select Arm CPU designs, Arm is expanding adoption of Cycuity Radix hardware security assurance technology from Arteris across additional next-generation processor programs. Integrated into Arm’s security assurance processes, Cycuity Radix helps engineering teams identify and mitigate potential security weaknesses and vulnerabilities earlier in the CPU design flow. Security assurance is moving upstream — into the design process, where potential issues can be found and addressed earlier. Lyndon Fawcett, Head of Product Security at Arm 🎤 : " Trusted compute is foundational to the next generation of AI, from agentic AI infrastructure in the data center to intelligent systems at the edge. Through our work with Arteris, we are strengthening our security assurance processes across our CPU portfolio, helping ensure developers can deploy secure, high-performance, energy-efficient compute with greater confidence from cloud to edge." Read the announcement to learn more: https://hubs.ly/Q04pj0d00 #semiconductors #cybersecurity #AI #CPU #SoC #SiliconSecurity #SecureCompute #innovation #Arm #Arteris

DAC 2026 is almost here, and I'm looking forward to seeing many friends and colleagues in Long Beach next month! If you haven't registered yet, advanced registration ends tomorrow (June 26), so now is a good time to make your plans. This year's conference is especially meaningful for me because it will be my first DAC at #Arteris. I'll be spending some time at the Arteris booth 833 throughout the conference. If you'd like to talk about SoC architecture, network-on-chip technology, IP integration, verification, SystemVerilog, standards activities, or catch up, please stop by and say hello. I'll also be chairing the Engineering Track session: Beyond the Block: Verifying Complex Systems in Context 📅 Wednesday July 29 🕜 1:30 PM 📍 Seaside Ballroom A This session explores some of today's most challenging verification problems that extend beyond individual IP blocks to complete systems, including power-aware verification, hardware emulation, and firmware-hardware collaborative debug. Whether you're coming for the technical sessions, the exhibit floor, or the conversations with colleagues across the industry, I hope we can connect. See you in Long Beach! #DAC2026 #Arteris #EDA #Verification #SystemVerilog #SoC #ChipDesign #Semiconductors

One of the biggest constraints in our industry right now isn’t around technology, but around talent. Developer shortage is the number one challenge facing the semiconductor industry over the next two years, according to the KPMG Global Semiconductor Outlook Survey 2025. And with the continued acceleration of AI and growth in system complexity, that pressure is only increasing. Designing today’s SoCs and multi-die systems requires deep expertise across architecture, data movement, and integration, which raises a broader question: how do we continue to scale innovation without requiring proportionally more specialized expertise? There’s no single solution. But improving how we design is part of the answer, and this has directly influenced our product strategy at Arteris. FlexGen was developed to reduce the manual effort and specialized expertise traditionally required to architect network-on-chip interconnect. By automating key aspects of NoC design, it enables teams to move faster, explore more options, and deliver predictable results. What I find encouraging is how quickly this approach is gaining traction. Leading companies, including AMD, are already adopting FlexGen, and demand keeps growing. Addressing the talent challenge will take time, but enabling engineers to do more, faster, is clearly part of the path forward.

📬 The latest edition of Connected by Arteris is here: Designing Secure, Intelligent and Scalable Semiconductor Systems This edition explores how to strengthen hardware security throughout the design lifecycle, what the European Cyber Resilience Act means for semiconductor development, and why efficient data movement, NoC modeling, and chiplet architectures are becoming essential for next-generation AI systems. You will also find our white paper on measuring and improving hardware security coverage, expert perspectives on optimizing HBM-based AI systems, a practical guide to multi-die chiplet design, updates on our expanding global engineering team, and opportunities to connect with us at upcoming industry events around the world. 👋 Featuring: Rocco Jonack, André Bonnardot, EDN: Voice of the Engineer, Semiconductor Engineering, DAC, The Chips to Systems Conference, AI Infra Summit, Michal Siwinski 📩 There are two easy ways to subscribe: 🔸 Hit the Subscribe button here on LinkedIn 🔸 Sign up via the form: https://hubs.ly/Q03mq__G0 #AI #semiconductors #chiplets #SoC #cybersecurity #innovation #Arteris