Lam Research

Every great lineup needs a player who can deliver in any situation. Meet Flex® — our product family that delivers the precision, repeatability, and tunability needed for advanced dielectric etch applications. See what it brings to the plate (literally). 👇 https://bit.ly/44V42Q0

Every transistor starts with the right foundation. ⚙️ This Word(s) of the Week explores the carefully engineered layers of insulating and conducting materials that form the gate of a field-effect transistor and help control how a device operates. See if you can guess the word(s) below. 👇

Making an impact, one community at a time. 💙 During our Week of Service, employees across our U.S. locations volunteered their time to support local organizations and causes. See the numbers behind the impact below.

Advanced packaging challenges for the AI era: solved. ✅ Watch the full video to learn how our tools like Syndion® and SABRE® 3D address key challenges in microbump uniformity, void-free plating, and interface-free bonding. https://bit.ly/3LHykB0

Lam Research, ASML, and imec recently presented joint research at the 2026 VLSI Symposium focused on high-NA EUV patterning. The work demonstrates 20nm resistive unit lines achieved with single exposure high-NA EUV using Lam’s Aether® technology. As patterning approaches the limits of conventional EUV, manufacturing complexity continues to increase. This latest research shows how reducing reliance on multi patterning can help address cost, yield, and scaling challenges at advanced nodes. The results reflect coordinated collaboration across process, lithography, and integration expertise. This type of ecosystem alignment is becoming increasingly important as the industry works to translate leading edge research into manufacturable solutions. https://bit.ly/4wAuewi

As AI demand skyrocketed in 2025, the pressure on chipmakers grew just as fast. We met that moment with a wave of innovation, including the release of Akara®, Aether®, and ALTUS® Halo. See which breakthrough made our 2025 time capsule.

Engineering smarter, one building block at a time. 🧱 This Word of the Week refers to reusable functional circuit blocks that are manufactured separately before being integrated into a single package. Swipe below to find out what it is.

At advanced DRAM nodes, even nanometer-scale variation in mandrel width or spacer thickness can cascade into pitch walk, and combined with line-edge roughness, it can trigger a line-bridge defect that shorts the device. Our Semiverse® Solutions team used Monte Carlo virtual fabrication in SEMulator3D® to map these compounding interactions across Self-Aligned Quadruple Patterning (SAQP) — defining a more robust process window before a single wafer hits the chamber. See how virtual fabrication helps engineers better understand and control process complexity: https://bit.ly/4fabxIQ

What’s holding back on-chip photonics? Moving optical engines closer to compute can improve data movement efficiency, but thermal challenges remain a key hurdle. Our Technical Director for Advanced Packaging Prahalad Parthangal explains: “Temperature change is one of the reasons why the shift of optical engines from the edge of the PCB to the package itself is taking a long time.” Read more about the manufacturing challenges behind scaling on-chip photonics via the Semiconductor Engineering article. https://bit.ly/3To7q4k

Not all chip connections behave the same under process variation. Using SEMulator3D®, the Semiverse® Solutions team modeled nano-TSVs to buried power rails in backside power delivery networks (BSPDNs), analyzing how overlay variation and patterning effects impact resistance. The results? Rounded corners increase sensitivity to overlay-induced resistance, making realistic process modeling essential for BSPDN optimization. Read the blog post to learn more. https://bit.ly/4f7vj8R