MIPS

In a recent conversation with Nitin Dahad, MIPS by GF CEO Sameer Wasson and CTO Yankin Tanurhan shared how MIPS’ software to silicon with RISC-V strategy is stronger with the combination of MIPS and ARC AI and processors, creating the largest RISC-V IP provider on the planet. They also cover the future architectural shifts in autonomous machines and highlight automotive and factory floor robotics as the largest manifestations of Physical AI.   Learn more in the video linked below. #PhysicalAI #MIPS #ARC #RISCV

MIPS by GF delivers software to silicon with RISC-V for building Physical AI platforms. As decisions move closer to where data is generated and actions are taken, new Physical AI systems are emerging. MIPS virtual platforms enable software-first design, leveraging open, standards-based processor IP to address the computing challenges of the “sense, think, act, communicate” signal-chain.     The combined MIPS and ARC team deliver the world’s best RISC-V portfolio backed by the deep expertise required for building the autonomous edge platforms of tomorrow. These platforms will blend modern AI inference with signal processing, event-driven control, mission-critical applications, and data processing at the point of action in harsh, unpredictable environments.    Learn more in this video  🎥  #MIPS #ARC #RISCV #PhysicalAI

As AI expands into more devices and environments, purpose-built compute architectures will be critical to bringing efficient intelligence to the edge. At DAC, The Chips to Systems Conference, MIPS by GF's Gert Goossens and Viswateja Nemani will present “Designing Power- and Area-Efficient Custom NPUs for Edge AI,” exploring how application-specific architectures can be tailored to the AI workloads they need to run, helping optimize power consumption and silicon area. The presentation will highlight “SmarT,” an application-specific instruction-set processor with a RISC-V ISA and specialized vector units designed for edge AI workloads, including low-power sensor, audio and video applications. Learn more and join the presentation Wednesday, July 29, at 10:45 a.m.  #DAC2026 #EdgeAI #AI #RISCV #NPU #Semiconductors #EmbeddedAI

📢 MIPS, by GF will be at multiple industry events this August. As AI tokens migrate to the edge, compute is shifting from centralized processing to real-time decision-making at the point of action. MIPS is leading this shift, bringing software to silicon with RISC-V. Meet with the MIPS team at these events to learn more.  #MIPS #PhysicalAI #AItokens #FMS 

The path from FPGA prototype to custom ASIC silicon can be out of reach for many of the small design teams driving the most novel work in semiconductors. A new HyperFRAME Research whitepaper highlights how Apex Compute used the MIPS, by GF, open, RISC-V-based SoC platform to ship a working full-stack FPGA development kit and establish a path to a production ASIC. With the ARC Processor IP Solutions portfolio now part of the portfolio of AI, MPU, MCU, and DSP cores, the combined catalog further extends what customers can build. Read more in the whitepaper below ↓    #MIPS #IP #RISCV  

At #COMPUTEX2026, MIPS, by GF CEO Sameer Wasson shared MIPS' software-first approach to Physical AI: open, standards-based RISC-V IP inside purpose-built silicon, enabling customers to customize for their own workloads.      Sameer explained that software to silicon with RISC-V is critical as Agentic AI at the edge is redefining the compute paradigm. The industry has historically started with hardware, but MIPS takes a software-first open approach, enabling customers to customize instead of being locked into proprietary architecture, which stifles innovation.      With the ARC and MIPS portfolios now one team, MIPS is the largest RISC-V IP provider and the second largest compute and AI IP provider on the planet. This gives MIPS scale, stability, and an end-to-end portfolio from entry-level cores to high-end NPUs, all designed with Physical AI in mind to sense, think, act, and communicate. MIPS lowers the barriers of adoption for custom silicon and accelerates turnkey enablement for customers to innovate quickly.     Watch Sameer's presentation at the link below to learn more.    #COMPUTEX2026 #PhysicalAI #RISCV #EdgeAI #MIPS

Physical AI is Agentic AI at the edge, where sensing, thinking, acting, and communicating happen in real time, as part of a closed-loop signal-chain.  The MIPS Atlas portfolio of processor IP was designed to deliver real-time autonomy.  The combined MIPS and ARC #RISCV processor IP suite spans AI, MPU, MCU, and DSP cores, designed with #software in mind for Physical AI.   #PhysicalAI #EdgeAI #RISCV  

In the agentic AI inference era, every #CPU will be defined from software to silicon with #RISCV and MIPS. Check out our products page to learn more.      #MIPS #Atlas #CPU 

EE Times | Electronic Engineering Times’ Nitin Dahad spoke with Sameer Wasson, CEO of MIPS, by GF and Andrea Gallo, CEO of RISC-V International, discussing how software-to-silicon approaches are shaping how next-generation systems are built.    Their discussion covered recent industry consolidation and what this means for customers, why RISC-V is increasingly emerging as the default ISA for new silicon designs, and how the industry is shifting toward software-first, workload-optimized architectures for AI at the edge. As AI enables more autonomous environments, the industry is converging on a new design model, where workloads, architecture, and software are defined together.  Watch the video linked below ⬇️  #PhysicalAI #EdgeAI #RISCV #EmbeddedSystems