Reusable FPGA IP for Secure Systems and Designs

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The FM-S28 provides two QSFP/QSFP+ module interfaces directly connected to the carrier card using the differential pairs of the FMC HPC connector. This enables a wide range of full data rate 40 Gigabit Ethernet, Fiber Channel, Infiniband and other very high performance serial standards to communicate with FPGA devices that have built in 10 Gigabit serial transceivers, such as the AMD Virtex-6 HXT family. More details: https://lnkd.in/gXqiNAue

Every embedded design starts with a challenge that needs to be solved by launch. That might be a product launch. Or, in some cases, a literal launch... into space. BLT helps organizations design, develop, and deploy FPGA, SoC, and embedded systems for mission-critical applications where performance and reliability matter. Have a complex FPGA or embedded challenge? Let BLT help you engineer the solution. https://lnkd.in/gP8H8VU

It's always nice when we *can* talk about our work! This case is about using pre-silicon simulations to confirm side channel leakage and countermeasures on a commercial AES implementation.

Keysight and Rambus collaborated to demonstrate that side-channel vulnerabilities in an Advanced Encryption Standard (AES) design can be detected at the pre-silicon stage. Rambus selected a pre-release version of one of its AES designs, in which an SCA vulnerability had previously been identified through traditional Field-Programmable Gate Array-based (FPGA) #validation testing. Using Keysight Inspector Pre-Silicon SCA, the Keysight Device Security team identified side-channel leakage from AES design signals directly from simulation, along with its root cause, without needing physical #hardware.  The results closely matched traditional FPGA validation performed by the Rambus team. Learn more: https://ow.ly/2U6R50Zrsn3

𝐘𝐨𝐮𝐫 𝐚𝐥𝐩𝐡𝐚 𝐢𝐬 𝐟𝐢𝐧𝐞. 𝐘𝐨𝐮𝐫 𝐭𝐢𝐜𝐤-𝐭𝐨-𝐭𝐫𝐚𝐝𝐞 𝐢𝐬𝐧'𝐭. Edge stopped being research-bound. It's pipeline bound. Right signals but wrong fills, latency that swings between the open and the close, risk checks living in code instead of hardware, that's ~50 microseconds-plus burned before your order leaves the box. An FPGA pipeline does wire-to-decision in nanoseconds, deterministically, with risk inline. In production on our ULL FPGA Framework: 50ns wire-to-wire, sub-2ns jitter. Find the microseconds you're losing, and where to close the gap. Talk to our team: https://hubs.la/Q04nQlf-0 #FPGA #LowLatency #HFT #FPGAEngineering #CapitalMarkets

The FM-S18 utilizes 2.5V signaling to ensure interoperability across the Spartan-6 and Virtex-6 FPGA families, as well as with previous generations of the Virtex family. More details: https://lnkd.in/gHdtrCwd

Keysight and Rambus collaborated to demonstrate that side-channel vulnerabilities in an Advanced Encryption Standard (AES) design can be detected at the pre-silicon stage. Rambus selected a pre-release version of one of its AES designs, in which an SCA vulnerability had previously been identified through traditional Field-Programmable Gate Array-based (FPGA) #validation testing. Using Keysight Inspector Pre-Silicon SCA, the Keysight Device Security team identified side-channel leakage from AES design signals directly from simulation, along with its root cause, without needing physical #hardware. The results closely matched traditional FPGA validation performed by the Rambus team. Learn more: https://gag.gl/fCC8nw

Lattice Gains Globee Awards Recognition Programmable logic innovator Lattice Semiconductor has confirmed that its MachXO5-NX TDQ family of FPGA devices triumphed in the First-to-Market Innovation category at the prestigious 2026 Globee Awards for Technology, which were recently held in San Francisco. This FPGA family is ground breaking, because it has full CNSA 2.0-compliant post-quantum cryptography (PQC) capabilities - with the latest encryption key establishment and digital signature requirements both being met. “With increased urgency to adopt quantum-resistant solutions, both crypto-agility and hardware-rooted security are becoming more important than ever,” comments Mamta Gupta, Lattice’s AVP of Strategic Business Development for Data Centre & Security, comments. “We are honored to receive this recognition from the Globee Awards for Lattice’s continued leadership in secure, low power programmable solutions.” Sophia Hong David Thomas Ravi Kiran Balla Mahj Leoparte Baguisi, ECE Dr. Hardik Shah Princess Joy Tusi Ravi Sharma Iliana Chen Gianluca Mariani Eric S. Joel Coplen Mark Hoopes Deepak Boppana Rakesh Agarwal Liam Weight Helmut Demel #fpga #pqc

I am pleased to share the publication of our recent research article entitled: “A high-throughput FPGA-based image encryption architecture using a CBC-inspired chaos-driven AES scheme” published in Integration, the VLSI Journal – Elsevier. https://lnkd.in/dkvbjVr9 This work presents a high-throughput FPGA-based image encryption architecture that combines AES-128 with a three-dimensional chaotic system through a CBC-inspired chaos-driven masking approach. The proposed design was implemented on a Xilinx PYNQ-Z2 FPGA using AXI4-Stream interfaces, DMA-based data transfer, and a pipelined AES-128 core. The results demonstrate strong statistical security and real-time hardware performance, including entropy values close to the ideal value, low adjacent-pixel correlation, strong NPCR/UACI results, successful NIST SP 800-22 statistical testing, and real-time encryption performance reaching approximately 100 frames/s for Full HD RGB images. I would like to thank all my co-authors for their valuable collaboration and contributions to this work. This publication reflects our continued research interest in FPGA-based cryptographic architectures, secure multimedia systems, embedded security, and real-time hardware acceleration. #FPGA #Cybersecurity #Cryptography #ImageEncryption #AES #ChaosBasedCryptography #EmbeddedSystems #HardwareSecurity