Adaptive A/D Conversion

This research theme investigates innovative architectural designs and conversion algorithms in adaptive sub-ranging and cyclic ADCs that leverage iterative digital estimation methods and adaptive gain control to enhance resolution beyond conventional limits while reducing conversion duration and power consumption. It focuses on overcoming analog component imperfections, saturation issues, and matching constraints by algorithmically optimizing the conversion process and digital post-processing in real time.

This theme addresses digital and hardware techniques that facilitate flexible and precise adjustment of ADC sampling rates beyond integer decimation factors. It includes FPGA-based real-time resampling circuits, interpolation methods, polyphase filter structures, and synchronization strategies that enable digital storage oscilloscopes and ADC hardware to generate arbitrary sampling rates with fine resolution, overcoming limitations of fixed clocks and integer decimation. The investigations highlight methods to seamlessly change sampling rates, reduce aliasing, and optimize memory and processing efficiency.

This area explores digital calibration strategies embedded within ADC systems that utilize lookup tables (LUTs) and automatic online correction to compensate integral and differential non-linearities (INL/DNL) caused by device mismatches, aging, temperature changes, and signal dynamics. Adaptive LUT update mechanisms and sine-wave based calibration measurements enable in situ error estimation and correction without interrupting normal ADC operation. These methods ensure stable high-precision conversion by continuously tracking and adjusting for time-varying non-idealities in the analog front-end.