Compiler Optimization

The quality of compiler-optimized code for high-performance applications is far behind what optimization and domain experts can achieve by hand. Although it may seem surprising at first glance, the performance gap has been widening over time, due to the tremendous complexity increase in microprocessor and memory architectures, and to the rising level of abstraction of popular programming languages and styles. This paper explores in-between solutions, neither fully automatic nor fully manual ways to adapt a computationally intensive application to the target architecture. By mimicking complex sequences of transformations useful to optimize real codes, we show that generative programming is a practical means to implement architecture-aware optimizations for high-performance applications. This work explores the promises of generative programming languages and techniques for the high-performance computing expert. We show that complex, architecture-specific optimizations can be implemented in a type-safe, purely generative framework. Peak performance is achievable through the careful combination of a high-level, multi-stage evaluation language -MetaOCamlwith low-level code generation techniques. Nevertheless, our results also show that generative approaches for high-performance computing do not come without technical caveats and implementation barriers concerning productivity and reuse. We describe these difficulties and identify ways to hide or overcome them, from abstract syntaxes to heterogeneous generators of code generators, combining high-level and type-safe multi-stage programming with a back-end generator of imperative code.

Quantum simulation of lattice gauge theories (LGTs) represents one of the most promising applications of near-term intermediate-scale quantum (NISQ) devices. This review provides a comprehensive synthesis of recent developments in NISQ-era quantum simulation methodologies for lattice gauge theories, focusing on three critical pillars: qubit encoding strategies, variational quantum algorithms, and error mitigation techniques. We examine the transition from naive encoding schemes to compact and symmetry-preserving encodings that dramatically reduce qubit requirements, analyze the performance of variational quantum eigensolvers (VQE) and quantum approximate optimization algorithms (QAOA) for gauge theory Hamiltonians, and evaluate state-of-the-art error mitigation strategies including zero-noise extrapolation, probabilistic error correction, symmetry verification, and unified mitigation frameworks. Furthermore, we assess hardware implementations across superconducting, trapped-ion, and neutral atom platforms, and discuss scalability challenges and emerging quantum-classical hybrid approaches such as neural-network quantum states and quantum variational Monte Carlo methods. Our analysis reveals that while significant progress has been made in reducing resource overhead-with compact encodings achieving up to 70% qubit reduction-substantial challenges remain in circuit depth optimization and error mitigation overhead for practically relevant system sizes. This review aims to provide researchers with a structured understanding of the current landscape and identify critical pathways toward achieving quantum advantage in lattice gauge theory simulations.

Matrix multiplication is a fundamental operation in linear algebra libraries, serving as the computational backbone for scientific computing, machine learning, and data analytics applications. This paper presents a comprehensive analysis of optimization techniques for General Matrix Multiply (GEMM) operations on modern CPU architectures. We examine six core optimization strategies: loop unrolling, vectorization using SIMD instructions, cache blocking, matrix packing, hardware-specific acceleration (including Intel AMX and IBM Power10 MMA), and prefix caching. Additionally, we discuss specialized optimizations for matrix-vector multiplication (GEMV) when matrix dimensions reduce to vectors. Our experimental results demonstrate performance improvements ranging from 2x to 24x over naive implementations, achieving 73-78% of theoretical peak performance across IBM Power architectures. The paper provides detailed implementation examples, particularly highlighting IBM Power10 Matrix-Multiply Assist (MMA) instructions based on OpenBLAS implementations.

There is an active research community concentrating on visualizations of algorithms taught in CS1 and CS2 courses. These visualizations can help students to create concrete visual images of the algorithms and their underlying concepts. Not only fundamental algorithms can be visualized, but also algorithms used in compilers. Visualizations that exist for use in compiler courses are mostly for the front end, though. In this article we propose the use of visualizations for understanding optimization passes. Optimization passes are complex algorithms that operate on large amounts of code and it is not obvious when, where and how often each optimization is applied to the code. We show in this article how visualizations for a procedural abstraction optimization pass can capture the effect of all instances of this optimization over an entire program to make it easier for students to comprehend procedural abstraction.

The efficiency of a software piece is a key factor for many systems. Real-time programs, critical software, device drivers, kernel OS functions and many other software pieces which are executed thousands or even millions of times per day require a very efficient execution. How this software is built can significantly affect the run time for these programs, since the context is that of compile-once/run-many. In this sense, the optimization flags used during the compilation time are a crucial element for this goal and they could make a big difference in the final execution time. In this paper, we use parallel metaheuristic techniques to automatically decide which optimization flags should be activated during the compilation on a set of benchmarking programs. The using the appropriate flag configuration is a complex combinatorial problem, but our approach is able to adapt the flag tuning to the characteristics of the software, improving the final run times with respect to other spread practices.

The work described here introduces a practical and accurate tool for predicting power consumption for FPGA circuits. The utility of the tool is that it enables FPGA circuit designers to evaluate the power consumption of their designs without resorting to the laborious and expensive empirical approach of instrumenting an FPGA board/chip and taking actual power consumption measurements. Preliminary results of the tool presented here indicate that an error of less than 5% is usually achieved when compared with actual physical measurements of power consumption.

The Aho-Corasick algorithm derives a failure deterministic finite automaton for finding matches of a finite set of keywords in a text. It has the minimum number of transitions needed for this task. The DFA-Homomorphic Algorithm (DHA) algorithm is more general, deriving from an arbitrary complete deterministic finite automaton a language-equivalent failure deterministic finite automaton. DHA takes formal concepts of a lattice as input. This lattice is built from a state/out- transition formal context that is derived from the complete deterministic finite automaton. In this paper, three general variants of the abstract DHA are benchmarked against the specialised Aho-Corasick algorithm. It is shown that when heuristics for these variants are suitably chosen, the minimality attained by the Aho-Corasick algorithm can be closely approximated. A published non-lattice-based algorithm is also shown to perform well in experiments.

Failure of a safety-critical application on an embedded processor can lead to severe damage or even loss of life. Here we are concerned with two kinds of failure: stack overflow, which usually leads to run-time errors that are difficult to diagnose, and failure to meet deadlines, which is catastrophic for systems with hard real-time characteristics. Classical software validation methods like simulation and testing with debugging require a lot of effort, are expensive, and do not really help in proving the absence of such errors. AbsInt's tools StackAnalyzer and aiT (timing analyzer) provide a solution to these problems. They use abstract interpretation as a formal method that leads to statements valid for all program runs. Both tools have been used successfully at Hispano-Suiza to analyze applications running on a Motorola PowerPC MPC555. They turned out to be well-suited for analyzing large safety-critical applications developed at Hispano-Suiza. They can be used either during the development phase providing information about stack usage and runtime behavior well in advance of any run of the analyzed application, or during the validation phase for acceptance tests prior to the certification review.

The increasing complexity of cloud-native, distributed, and AI-enabled software systems has rendered traditional, static quality assurance (QA) practices increasingly inadequate, as fixed test suites and manually curated strategies struggle to keep pace with rapid release cycles, architectural heterogeneity, and continuously evolving system behavior. Although automated test generation techniques such as random testing, symbolic execution, and evolutionary algorithms have matured considerably since the early 2000s, they are typically deployed as standalone tools with limited awareness of broader quality objectives, execution cost, or contextual risk, thereby constraining their effectiveness in large-scale, real-world environments. Recent advances in large language models (LLMs), reinforcement learning, and agent-based system design enable a fundamentally new paradigm in which testing capabilities are embedded within autonomous quality agents that can reason, adapt, and learn over time. This article introduces a policy-driven autonomous quality agent framework that unifies classical test generation techniques with modern AI-based orchestration, drawing on established systems such as EvoSuite and KLEE alongside recent LLM-based architectures like TESTPILOT. By incorporating feedback-aware control loops, cost-and risk-sensitive policies, and iterative refinement mechanisms, the proposed approach enables test generation strategies to be dynamically selected, combined, and optimized in response to system changes and empirical outcomes. As a result, autonomous quality agents emerge as first-class actors within modern CI/CD pipelines, continuously optimizing coverage, defect detection, and resource utilization under realistic operational constraints rather than operating as passive, one-off automation tools.

In this article, we investigate compiler transformation techniques regarding the problem of scheduling VLIW instructions aimed at reducing power consumption of VLIW architectures in the instruction bus. The problem can be categorized into two types: horizontal scheduling and vertical scheduling. For the case of horizontal scheduling, we propose a bipartite-matching scheme for instruction scheduling. We prove that our greedy bipartite-matching scheme always gives the optimal switching activities of the instruction bus for given VLIW instruction scheduling policies. For the case of vertical scheduling, we prove that the problem is NP-hard, and we further propose a heuristic algorithm to solve the problem. Our experiment is performed on Alpha-based VLIW architectures and an ATOM simulator, and the compiler incorporated in our proposed schemes is implemented based on SUIF and MachSUIF. Experimental results of horizontal scheduling optimization show an average 13.30% reduction with four-...

Graphics Processing Units (GPU) have become the platform of choice for accelerating a large range of data parallel and task parallel applications. Both AMD and NVIDIA have developed GPU implementations targeted at the high performance computing market. The rapid adoption of GPU computing has been greatly aided by the introduction of highlevel programming environments such as NVIDIA's CUDA C and Khronos' OpenCL. Given the fact that CUDA C has been on the market for a number of years, a large number of applications have been developed in the HPC community. In this paper we describe Caracal, our implementation of a dynamic translation framework that allows CUDA C programs to run on alternative GPU platforms. Here we target the AMD Evergreen family of GPUs. We discuss the challenges of compatibility and correctness faced by the translator using specific examples. We analyze the overhead of the translator compared with the execution time of several benchmarks. We also compare the quality of the code generated by our framework with that produced by the AMD OpenCL library. Our dynamically translated code performs comparably to the native OpenCL library, expands the opportunities for running CUDA C on new heterogeneous architectures, and provides a vehicle for evaluating compiler optimizations in the future.

The performance of data-parallel processing can be highly sensitive to any contention in memory. In contrast to multi-core CPUs which employ a number of memory latency minimization techniques such as multi-level caching and prefetching, Graphics Processing Units (GPUs) require that the data-parallel computations reference memory in a deterministic pattern in order to reap the benefits of these many-core platforms. Memory access sensitivity is primarily due to the Massively Parallel Processing (MPP) execution ...

This paper discusses a repertoire of well-known and new compiler optimizations that help produce excellent server application performance and investigates their performance contributions. These optimizations combined produce a 40% speed-up in on-line transaction processing (OLTP) performance and have been implemented in the Intel C/C++ Itanium compiler. In particular, the paper presents compiler optimizations that take advantage of the Itanium register stack, proposes an enhanced Linux preemption model and demonstrates their performance potential for server applications.

This paper examines the efficiency of the register stack engine (RSE) in the canonical Itanium architecture, and introduces novel optimization techniques to enhance the RSE performance. To minimize spills and fills of the physical register file, optimizations are applied to reduce internal fragmentation in statically allocated register stack frames. Through the use of dynamic register usage (DRU) and dead register value information (DVI), the processor can dynamically guide allocation and deallocation of register frames. Consequently, a speculatively allocated register frame with a dynamically determined frame size can be much smaller than the statically determined frame size, thus achieving minimum spills and fills. Using the register stack engine (RSE) in the canonical Itanium architecture as the baseline reference, we thoroughly study and gauge the tradeoffs of the RSE and the proposed optimizations using a set of SPEC CPU2000 benchmarks built with different compiler optimizations. A combination of frame allocation policies using the most frequent frame size and deallocation policies using dead register information proves to be highly effective. On average, a 71% reduction in aggregate spills and fills can be achieved over the baseline reference.

This paper discusses a repertoire of well-known and new compiler optimizations that help produce excellent server application performance and investigates their performance contributions. These optimizations combined produce a 40% speed-up in on-line transaction processing (OLTP) performance and have been implemented in the Intel C/C++ Itanium compiler. In particular, the paper presents compiler optimizations that take advantage of the Itanium register stack, proposes an enhanced Linux preemption model and demonstrates their performance potential for server applications.

Hybrid architectures combining conventional processors with con gurable logic resources enable ecient coordination of control with datapath computation. With integration of the two components on a single device, loop control and data-dependent branching can be handled by the conventional processor, while regular datapath computation occurs on the con gurable hardware. This paper describes a novel pragma-based approach to programming such h ybrid devices. The NAPA C language provides pragma directives so that the programmer or an automatic partitioner can specify where data is to reside and where computation is to occur with statement-level granularity. The NAPA C compiler, targeting National Semiconductor's NAPA1000 chip, performs semantic analysis of the pragma-annotated program and cosynthesizes a conventional program executable combined with a con guration bit stream for the adaptive logic. Compiler optimizations include synthesis of hardware pipelines from pipelineable loops.

Modern software demands high performance, portability, and adaptability, driving innovations in compiler technologies. This article investigates advanced optimization strategies in modern compilers, focusing on Just-In-Time (JIT), Ahead-of-Time (AOT), and hybrid compilation pipelines. Using architectural modeling, benchmark-based simulations, and comparative analysis, the study demonstrates how hybrid compilers combine static and dynamic optimizations to maximize runtime performance while maintaining determinism and portability. The results provide valuable insights for future compiler design and adaptive optimization strategies.

The widespread use of the continuation-passing style (CPS) transformation in compilers, optimizers, abstract interpreters, and partial evaluators reflects a common belief that the transformation has a positive effect on the analysis of programs. Investigations by Nielson [13] and Burn/Filho [5,6] support, to some degree, this belief with theoretical results. However, they do not pinpoint the source of increased abstract information and do not explain the observation of many people that continuation-passing confuses some conventional data flow analyses. To study the impact of the CPS transformation on program analysis, we derive three canonical data flow analyzers for the core of an applicative higher-order programming language. The first analyzer is based on a direct semantics of the language, the second on a continuation-semantics of the language, and the last on the direct semantics of CPS terms. All analyzers compute the control flow graph of the source program and hence our resu...

Quantum computing is poised to revolutionize computational paradigms by leveraging quantum mechanics principles such
as superposition and entanglement. However, the full-scale deployment of quantum applications remains constrained by hardware
limitations, including high error rates and quantum decoherence. Quantum Software Engineering (QSE) emerges as a critical field
addressing these challenges by optimizing algorithm design, error mitigation, and compiler strategies to enhance fault tolerance.
Algorithm design in QSE focuses on developing quantum algorithms that efficiently exploit quantum parallelism while minimizing
resource overhead. Key advancements include quantum variational algorithms, hybrid quantum-classical frameworks, and novel
quantum heuristics tailored for optimization and cryptographic problems. Error mitigation techniques play a pivotal role in extending
quantum circuit reliability without requiring full quantum error correction. Methods such as zero-noise extrapolation, probabilistic
error cancellation, and quantum embedding techniques help reduce computational inaccuracies. Additionally, compiler optimization
ensures efficient quantum program execution by minimizing gate depth, optimizing qubit mapping, and leveraging noise-adaptive
scheduling to enhance quantum hardware performance. This paper explores the synergy between these three pillars of QSE, analyzing
their impact on improving the feasibility of fault-tolerant quantum computing. It also examines emerging trends, including AI-driven
quantum compilers, adaptive error mitigation techniques, and hardware-aware quantum software development. By bridging the gap
between theoretical advancements and practical implementations, QSE provides a structured approach to accelerating quantum
computing adoption across domains such as cryptography, materials science, and artificial intelligence. The findings underscore the
necessity of interdisciplinary collaboration in developing robust quantum software solutions that maximize computational efficiency
while mitigating inherent quantum hardware limitations.

For the worst-case execution time (WCET) analysis, especially loops are an inherent source of unpredictability and loss of precision. This is caused by the difficulty to obtain safe and tight information on the number of iterations executed by a loop in the worst case. In particular, datadependent loops whose iteration counts depend on function parameters are extremely difficult to analyze precisely. Procedure cloning helps by making such data-dependent loops explicit within the source code, thus making them accessible for high-precision WCET analyses. This paper presents the effect of procedure cloning applied at the source-code level on worst-case execution time. The optimization generates specialized versions of functions being called with constant values as arguments. In standard literature, it is used to enable further optimizations like constant propagation within functions and to reduce calling overhead. We show that procedure cloning for WCET minimization leads to significant improvements. Reductions of the WCET from 12% up to 95% were measured for real-life benchmarks. These results demonstrate that procedure cloning improves analyzability and predictability of real-time applications dramatically. In contrast, average-case performance as the criterion procedure cloning was developed for is reduced by only 3% at most. Our results also show that these WCET reductions only implied small overhead during WCET analysis.

This thesis would not have been completed without the help of others. I would like to take this opportunity to express my gratitude towards them and acknowledge them. First of all, I would like to offer my deepest gratitude to my supervisors Olivier Barais and Benoit Baudry for their useful advices, and for guiding my steps over more than three years. Special thanks are also due to my "third" supervisor Gesron Sunyé that always knew how to motivate me and help me to overcome the difficult times in my thesis. I owe special thanks to my Master's supervisor Marouane Kessentini, with whom I discovered the software engineering research world, for encouraging me to continue in the research field as a PhD candidate. I would also like to thank the members of my jury. My examiners, Hélène Waeselynck and Philippe Merle for having accepted to serve on my examination board and for the time they have invested in reading and evaluating this thesis. Thanks are also due to Erven Rohou for agreeing to preside over my jury. I would also like to thank Jean-Marie Mottou and Franck Fleury for attending as members of the jury. I greatly appreciate and wish to thank all the (former and current) members of the DiverSE research team for providing a great and friendly work atmosphere, and for all the different discussions, seminars, and DiverSE coffees. Finally, I would like to thank my family. Even so far away from home, they are always present in my life during these three years. I first express my gratitude to my parents Najoua and Noureddine for their support, comprehension, confidence and, especially for their patience. You have always been behind me and believed in me. Then, thanks to my sisters Imene and Jihene for encouraging me to succeed in everything I do. By now, we can say that we have a Doctor in the Boussaa family ! i Résumé en Français vii

The Amsterdam Compiler Kit is a widely used compiler building system. Up until now, the emphasis has been on producing good object code. In this paper we describe recent work that has focused on reducing compile time. The techniques described in this paper have resulted in C compilers for the Sun-3 and VAX that are 3 to 4 times faster than the native compilers provided by the manufacturers.

The general translator formalism and computing specific implementations are proposed. The implementation of specific elements necessary to process the source and destination information within the translators are presented. Some common directives or instructions, such as classes and procedures, were unified and generalized in order to allow general translations implementations. In order to cover general cases, two levels of processing are required, related to the source and destination information appropriate transformations, with the related control and processing instructions. The proposed general translator elements are useful for processing natural or artificial information described through any types of languages or systems.

The general translator formalism and computing specific implementations are proposed. The implementation of specific elements necessary to process the source and destination information within the translators are presented. Some common directives or instructions, such as classes and procedures, were unified and generalized in order to allow general translations implementations. In order to cover general cases, two levels of processing are required, related to the source and destination information appropriate transformations, with the related control and processing instructions. The proposed general translator elements are useful for processing natural or artificial information described through any types of languages or systems.

We exhibit an aggressive optimizing compiler for a functionalprogramming language which includes a first-class forward automatic differentiation (AD) operator. The compiler's performance is competitive with FORTRAN-based systems on our numerical examples, despite the potential inefficiencies entailed by support of a functional-programming language and a first-class AD operator. These results are achieved by combining (1) a novel formulation of forward AD in terms of a reflexive mechanism that supports firstclass nestable nonstandard interpretation with (2) the migration to compile-time of the conceptually run-time nonstandard interpretation by whole-program inter-procedural flow analysis.

We exhibit an aggressive optimizing compiler for a functionalprogramming language which includes a first-class forward automatic differentiation (AD) operator. The compiler's performance is competitive with FORTRAN-based systems on our numerical examples, despite the potential inefficiencies entailed by support of a functional-programming language and a first-class AD operator. These results are achieved by combining (1) a novel formulation of forward AD in terms of a reflexive mechanism that supports firstclass nestable nonstandard interpretation with (2) the migration to compile-time of the conceptually run-time nonstandard interpretation by whole-program inter-procedural flow analysis.

Execution of a program almost always involves multiple address spaces, possibly across separate machines. Here, an approach to reducing such costs using compiler optimization techniques is presented. This paper elaborates on the overall vision, and as a concrete example, describes how this compiler assisted approach can be applied to the optimization of system call performance on a single host. Preliminary results suggest that this approach has the potential to improve performance significantly depending on the program's system call behavior.

Current trends in many-core architectures show a switch from a small number of architecturally sophisticated cores (e.g. Intel Core2, IBM PowerPC) to many simple cores (e.g SiCortex and Tilera multiprocessor). These simple cores lack many of the advanced features of the complex cores (e.g. out-of-order execution, rotating register files, predication, speculation, etc.), which puts extra burden on the compiler to produce an efficient schedule, especially for loops. We provide an advanced loop scheduling framework using software pipelining, which does not rely on any special hardware support. This open-source framework makes software pipelining available to simple cores and helps to mitigate the lack of advanced hardware features. The paper also provides measurements to demonstrate the effectiveness of this framework.

This paper is an introduction to Lambdix, a lazy Lisp interpreter implemented at the Research Laboratory of Paris XI University (Laboratoire de Recherche en Informatique, Orsay). Lambdix was devised in the course of an investigation into the relationship between the semantics of programming languages and their implementation; it was used to demonstrate that in the Lisp domain, semantic correctness is consistent with efficiency, contrary to what has often been claimed. The first part of the paper is an overview of well-known semantic difficulties encountered by Lisp as well as an informal presentation of Lambdix; it is shown that the difficulties which Lisp encouters do not arise in Lambdix. The second part is about efficiency in implementation models. It explains why Lambdix is better suited for lazy evaluation than previous models. The section ends by giving comparative execution time tables.