Digital Signal Processing (DSP)

This paper presents the design of a new digital signal processing (DSP) stand alone evaluation board for real time application using TMS320F28335 DSP processor. A standalone evaluation board is a general purpose board with an embedded processor and generally with a way to download and execute user's program on it. The evaluation board is tested by implementing some DSP based algorithm to generate SPWM signal, used to drive the gate driver of IGBT. The algorithm development methodology and the experimental results are presented. The schematic and layout is designed using Eagle v6.1.0 PCB designer.

Reconfigurable finite impulse response (FIR) filters whose filter coefficients and filter order change dynamically during run-time play an important role in the software defined radio (SDR) systems, multi-channel filters, and digital up/down converters. However, there are not many reports on such reconfigurable designs which can support dynamic variation of filter order and filter coefficients. The purpose of this paper is to provide an architectural solution for the FIR filters to support run-time variation of the filter order and filter coefficients. First, two straightforward designs, namely, (i) single-MAC based design and (ii) fullparallel design are presented. For large variation of the filter order, two designs based on (iii) folded structure and (iv) fast FIR algorithm are presented. Finally, we propose (v) high throughput design which provides significant advantage in terms of hardware and/or time complexities over the other designs. We compare complexities of all the five structures, and provide the synthesis results for verification.

SDM POSTPROCESSOR / ADAPTIVE EQUALISER Sub-band Adaptive (Automatic) Volume Control (SB-AVC) for Cancellation of "sensory-neural shock" caused by narrow band spectral signal in a Hearing Aid COPERNICUS Project - CP940515 Int. Mic. (Szolgálati célú, alapelv ismertető munkaanyag!) Nagy Gábor KKMF-MAI 1996. jún. 21. Az 1996, Jan. 16-án kelt Előzetes vázlat-ban összefoglalt elképzeléseket folytatva, az 1996. Ápr. 7-én kelt blokkvázlat szerinti, hallásjavítás célú posztprocesszort tekintjük a továbbiakban részleteiben kidolgozandó elméleti útiránynak. A Postprocesszor technológia kutatási task számára az 1996. Máj. 14-én kelt Előzetes vázlat 2.-ben lettek összefoglalva az aritmetikai/technológia komplexítás előzetes becslésének eredményei. A Sigma-Delta Modulátor/Sensor (SDM, SDM95v1) kutatás eredménye egy SDM front-end processzorral ellátott "Integrált mikrofon", illetve távlatilag egy "Intelligens mikrofon". A kis méret és az elérhető legjobb CMOS technológián való adaptálástól remélhető kis fogyasztás közeli realitássá teszi az új chip hallásjavító készülékekben való alkalmazását is. Azonban az igazán radikális újdonságot nem az SDM mikrofon önmagában való alkalmazása adja, hanem az elméleti hipotézis, hogy az SDM 1-bites jelterében olyan jelmanipulációk hajthatók végre, melyek a hagyományostól lényegesen kisebb komplexitású, így kisebb fogyasztású DSP struktúrára vezetnek. Erre vannak is már kezdeti próbálkozások, publikációs hivatkozások. Bármilyen célú "Postprocesszor chip stratégia, architektúra" tekintetében kiemelten fontos a kis komplexitás és fogyasztás ami az SDM jel direkt feldolgozásánál kiadódó szorzásmentes struktúrától nagy valószínűséggel remélhető. A szorzások multiplexálásokra és shiftelésekre egyszerűsíthetők, ill. mindenhol ilyenre törekszünk. Több helyen egyszerűsítést jelent az aritmetika kis bitszáma is. A minimális feladatként eredetileg megcélzott "Adaptiv Equalizer" funkció már elméletileg igazolhatóan mindenképpen teljesíthető, de igazi tartalmat, értelmet csak egy alkalmazási funkció megjelölésével kap. Ilyen funkció pl. egy új típusú hallásjavító készülék.

The introduction of SRAM-based field programmable gate arrays (FPGAs) has opened up a new dimension to parallel computing architectures. This paper describes an alternative approach to parallel computing-reconfigurable or virtual parallel processing (VPP). Rather than mapping an application onto a given parallel machine, the WP approach synthesizes the appropriate type and number of processing elements, as well as the interconnection topology, that is optimal for the application. For each application, configuration data is downloaded to the machine that personalizes the hardware for the task at hand. The paper provides a brief description of the authors reconfigurable computer, Archimedes. The benefits of the VPP approach are highlighted by two example applications-the 2-D FFT and a narrow-band digital filter. A novel parallel implementation of a polynomial transform based 2-D transform is described and compared with results for distributed memory parallel machines that have been reported in the literature. The comparison highlights the computational advantage provided by reconfigurable computing. The digital filter implementation employs sigma-delta modulation encoding to reduce the arithmetic workload. The application of this technology to a communications receiver is explained. ᭧ 1998 Elsevier Science B.V.

Software-Defined Radio (SDR) is a radio communication system where components that have been traditionally implemented in hardware (e.g. mixers, filters, amplifiers, modulators/demodulators, detectors, etc.) are instead implemented by means of software on a personal computer or embedded system. Reconfigurable Finite Impulse Response (RFIR) filter plays an important role in SDR systems, whose filter coefficient change dynamically during runtime. In this paper, Low Cost Carry Bypass adder Reconfigurable Finite Impulse Response (LC-CBA-RFIR) is introduced to perform the RFIR filter operations. DRAM-based Reconfigurable Partial Product Generators (DRPPG) consists of MUX and dual port distributed RAM, which has coefficient to perform a FIR filter operation. With the help of Verilog code, the RFIR filter architecture was verified in Modelsim software. The same Verilog code was used to analyse the FPGA performances such as LUT, flip flop, slice and frequency. After implementing FPGA, all the performance improved in LC-CBA-RFIR method compared to the conventional methods.

The existing algorithms for approximation of DCT targets only on the DCT of small transform lengths, the main objective is reducing the power and calculation time. Multiplications are the operations in DCT which consumes majority of time and power and it is very complex to calculate the values of DCT. Approximation is needed in DCT for higher transform lengths as computational complication increases non-linearly with higher size lengths DCT. To offer lower circuit complexity and superior compression performance Multiplier-free approximate DCTs have been implemented which can be easily implemented in VLSI hardware by using only addition operation and subtraction operations. Thus, compared to integer and conventional DCTs, approximated DCTs result in reduction of the chip area as well as in power consumption. In this paper, here an algorithm is presented for approximation of DCT where an approximate DCT of length N could be derived from pair of DCTs of length (N/2) at cost of N additi...

Neutron and gamma ray discrimination is crucial for measurements with detectors sensitive to both neutron and gamma radiation. All neutron sources usually emit gamma rays to which the detectors are sensitive. So, we need to seperate the gamma events from the neutron events. Two major techniques which are generally used to identify n/γ events, are Pulse Shape Discrimination (PSD) and Time of Flight (TOF). PSD and TOF was simultaneously performed using digital oscilloscope by our group using LaCl3(Ce) and BC501 liquid scintillator with Cf fission source [1]. We have also characterized a uni-directionally grown 1,3,5-Triphenylbenzene (3PB) single crystal using TOF technique with conventional analog electronics. The neutron energy spectrum of Cf was reproduced nicely (see Ref. [2]). In the present work, we have used CAEN made digitizer to do PSD and TOF measurements simultaneously with Digital Pulse Processing (DPP) technique. In this measurement, the 3PB crystal which is previously cha...

Subband coding has recently emerged as the leading standardization candidate in audio/video/image compression, echo cancellation, radar, image analysis, communications, medical imaging etc. Due to this, Discrete Wavelet Transform has gained much attention in memory efficient technique for handling large amounts of data. The implicit overlapping and variable-length basis functions from wavelets produce smoother and more pleasant reconstructions. Data compression, bit rate reduction is done by implementing memory efficient Discrete Wavelet Transform based on Coextensive Distributive Computation on FPGA. In this work Low complexity DWT Architecture which utilizes the Look-Up Table, using Shift register FPGA structure is developed to develop a filter bank without multiplier which is the important components in a DWT structure. This results in better space usage and reduction in the area size. Filter bank construction is done using DB-4 Daubechies 9/7 wavelets. This paper presents a consistent performance, good operating speed and area efficient DWT processor along with best utilization of resources available on target FPGA. The proposed Discrete Wavelet Transform System is implemented on Xilinx xc2vp30-7-ff896 Field Programmable Gate Array with highest operating frequency of 141.055MHz.

The existing algorithms for approximation of DCT targets only on the DCT of small transform lengths, the main objective is reducing the power and calculation time. Multiplications are the operations in DCT which consumes majority of time and power and it is very complex to calculate the values of DCT. Approximation is needed in DCT for higher transform lengths as computational complication increases non-linearly with higher size lengths DCT. To offer lower circuit complexity and superior compression performance Multiplier-free approximate DCTs have been implemented which can be easily implemented in VLSI hardware by using only addition operation and subtraction operations. Thus, compared to integer and conventional DCTs, approximated DCTs result in reduction of the chip area as well as in power consumption. In this paper, here an algorithm is presented for approximation of DCT where an approximate DCT of length N could be derived from pair of DCTs of length (N/2) at cost of N additi...

An efficient Lookup Table (LUT) design for memory-based multiplier is proposed. This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage (OMS), we have proposed utilizing Even Multiple Storage (EMS) scheme for memory-based multiplication and by doing so we are able to achieve a less complex and high-speed design. Because of the very simpler control circuit used in our design, to extract the odd multiples of the product term, we are also able to achieve a significant reduction in path delay and area complexity. For validation, the proposed design of the multiplier is coded in VHDL, simulated and synthesized using Xilinx tool and then implemented in Virtex 7 XC7vx330tffg1157 FPGA. Various key performance metrics like number of sli...

In order to understand the performance of the PARIS (Photon Array for the studies with Radioactive Ion and Stable beams) detector, detailed characterization of two individual phoswich (LaBr 3 (Ce)-NaI(Tl)) elements has been carried out. The detector response is investigated over a wide range of E γ = 0.6 to 22.6 MeV using radioactive sources and employing 11 B(p, γ) reaction at E p = 163 keV and E p = 7.2 MeV. The linearity of energy response of the LaBr 3 (Ce) detector is tested upto 22.6 MeV using three different voltage dividers. The data acquisition system using CAEN digitizers is set up and optimized to get the best energy and time resolution. The energy resolution of ∼ 2.1% at E γ = 22.6 MeV is measured for the configuration giving best linearity upto high energy. Time resolution of the phoswich detector is measured with a 60 Co source after implementing CFD algorithm for the digitized pulses and is found to be excellent (FWHM ∼ 315 ps). In order to study the effect of count rate on detectors, the centroid position and width of the E γ = 835 keV peak were measured upto 220 kHz count rate. The measured efficiency data with radioactive sources are in good agreement with GEANT4 based simulations. The total energy spectrum after the add-back of energy signals in phoswich components is also presented.

A parallel prefix-structured optimized Ladner Fischer adder was used to implement the Haar discrete wavelet transform. Since it is the most recent idea and a crucial option for balancing accuracy and parameter efficiency, we are thinking about the approximation topic in this instance. Prior to image processing and analysis, the image transformation is a crucial step. A low-complexity pre-processing filter appropriate for extremely energy-constrained image processing systems is the Haar discrete wavelet transform (HDWT). This paper provides an ideal HDWT hardware design based on the Ladner-Fisher algorithm for image processing at extremely high-performance efficiency.

The existing algorithms for approximation of DCT targets only on the DCT of small transform lengths, the main objective is reducing the power and calculation time. Multiplications are the operations in DCT which consumes majority of time and power and it is very complex to calculate the values of DCT. Approximation is needed in DCT for higher transform lengths as computational complication increases non-linearly with higher size lengths DCT. To offer lower circuit complexity and superior compression performance Multiplier-free approximate DCTs have been implemented which can be easily implemented in VLSI hardware by using only addition operation and subtraction operations. Thus, compared to integer and conventional DCTs, approximated DCTs result in reduction of the chip area as well as in power consumption. In this paper, here an algorithm is presented for approximation of DCT where an approximate DCT of length N could be derived from pair of DCTs of length (N/2) at cost of N additi...

Reconfigurable finite impulse response (FIR) filters whose filter coefficients and filter order change dynamically during run-time play an important role in the software defined radio (SDR) systems, multi-channel filters, and digital up/down converters. However, there are not many reports on such reconfigurable designs which can support dynamic variation of filter order and filter coefficients. The purpose of this paper is to provide an architectural solution for the FIR filters to support run-time variation of the filter order and filter coefficients. First, two straightforward designs, namely, (i) single-MAC based design and (ii) fullparallel design are presented. For large variation of the filter order, two designs based on (iii) folded structure and (iv) fast FIR algorithm are presented. Finally, we propose (v) high throughput design which provides significant advantage in terms of hardware and/or time complexities over the other designs. We compare complexities of all the five structures, and provide the synthesis results for verification.

Nowadays, Finite Impulse Response (FIR) filters are used to change the attributes of a signal in the time or frequency domain. Among FIR filters, a reconfigurable filter has the advantage of changing the coefficient in real-time, while performing the operation. In this paper, the Anti-Symmetric Product Coding (APC) and Odd Multiple Storage (OMS) modules are utilized to implement the reconfigurable FIR filter (RFIR–APC–OMS). Herein, the APC–OMS module is used to reduce the area of the RFIR architecture. The performance of the RFIR–APC–OMS is analyzed in terms of: area, power, delay, LUT, flip flop, slices, and frequency. RFIR–APC–OMS has reduced 3.44% of area compared to the existing RFIR architecture employing the Dynamic Reconfigurable Partial Product Generator (DRPPG) module.

In this paper, we have analyzed the register complexity of direct-form and transpose-form structures of FIR filter and explored the possibility of register reuse. We find that direct-form structure involves significantly less registers than the transpose-form structure, and it allows register reuse in parallel implementation. We analyze further the LUT consumption and other resources of DA-based parallel FIR filter structures, and find that the input delay unit, coefficient storage unit and partial product generation unit are also shared besides LUT words when multiple filter outputs are computed in parallel. Based on these finding, we propose a design approach, and used that to derive a DA-based architecture for reconfigurable block-based FIR filter, which is scalable for larger block-sizes and higher filter-lengths. Interestingly, the number of registers of the proposed structure does not increase proportionately with the block-size. This is a major advantage for area-delay and energy efficient high-throughput implementation of reconfigurable FIR filters of higher block-sizes. Theoretical comparison shows that the proposed structure for block-size 8 and filter-length 64 involves 60% more flip-flops, 6.2 times more adders, 3.5 times more AND-OR gates, and offers 8 times higher throughput. ASIC synthesis result shows that the proposed structure for block-size 8 and filter-length 64 involves 1.8 times less area-delay product (ADP) and energy per sample (EPS) than the existing design, and it can support 8 times higher throughput. At common throughput, the proposed structure for block sizes 4 and 8, respectively, consumes 38% and 50% less power than the exiting structure on average for different supply voltages.

The design of high performance Digital Signal Processing (DSP) Processors for Software Defined Radio (SDR) with high degree of flexibility and low power consumption has been a major challenge to the scientific community ever since its conception. The basic philosophy of SDR is to implement different modulation or demodulation schemes on the same underlying hardware. Currently available high performance DSP processors, optimized with 'Very Large Instruction Word (VLIW)' architecture and multiply and accumulate (MAC) units, are unable to meet the near real time speed requirements of Software Defined Radios (SDR) due to their inherent sequential execution of compute intensive signal processing algorithms. Moreover, their power dissipation is considerably high. Even though, Application Specific Integrated Circuits (ASIC) exhibit high performance, they are also not suitable because of their lack of flexibility. Various references on FPGA based implementations of reconfigurable architectures for SDRs are also available. However, the Look-up Table (LUT) based implementations of FPGAs are not optimum and therefore, cannot offer highest performance at low silicon cost. Keeping this view, this paper presents the design of a configurable communication processor for Software Defined Radio. The proposed scheme features the performance of an ASIC based design combined with the flexibility of software. Experimental results reveal that the proposed architecture has minimum hardware requirement, improved silicon area utilization and low power dissipation.

Implementing hardware design in Field Programmable Gate Arrays (FPGAs) is a formidable task. There is more than one way to implement the dsp design for digital FIR filter. The traditional approach is based on application of general purpose multipliers. However, multipliers implemented in FPGA architectures do not allow constructing economic Digital Filters. For this reason, multipliers are replaced by Lookup Tables and Adder Subs tractor, which use Bit-Serial Arithmetic.

The design of high performance Digital Signal Processing (DSP) Processors for Software Defined Radio (SDR) with high degree of flexibility and low power consumption has been a major challenge to the scientific community ever since its conception. The basic philosophy of SDR is to implement different modulation or demodulation schemes on the same underlying hardware. Currently available high performance DSP processors, optimized with ‘Very Large Instruction Word (VLIW)’ architecture and multiply and accumulate (MAC) units, are unable to meet the near real time speed requirements of Software Defined Radios (SDR) due to their inherent sequential execution of compute intensive signal processing algorithms. Moreover, their power dissipation is considerably high. Even though, Application Specific Integrated Circuits (ASIC) exhibit high performance, they are also not suitable because of their lack of flexibility. Various references on FPGA based implementations of reconfigurable architectu...

In this paper, a scheme for the design of area efficient and high speed pipeline VLSI architecture for the computation of fixed point 1-d discrete wavelet transform using lifting scheme is proposed. The main focus of the scheme is to reduce the number and period of clock cycles and efficient area with little or no overhead on hardware resources. The fixed point representation requires less hardware resources compared with floating point representation. The pipelining architecture speeds up the clock rate of DWT and reduced bit precision reduces the area required for implementation. The architecture has been coded in verilog HDL on Xilinx platform and the target FPGA device used is Virtex-II Pro family, XC2VP77board. The proposed scheme requires the least computing time for fixed point 1-D DWT and achieves the less area for implementation, compared with other architectures. So this architecture is realizable for real time processing of DWT computation applications.

— FIR Filter is a fundamental function in many applications, mainly in the field of Digital Signal Processing (DSP). The main problem of this function is its computational complexity, needed to process a signal. Currently, FPGAs are widely used for a variety of computationally complex applications. New generation of FPGAs contain not only basic configurable logic resources but also complex embedded resources. The FPGA implementation of FIR filters based on customary design & techniques utilizes extensive hardware resources, which does not comply circuit scale and system speed. In this paper we investigated the resource utilization and system speed of a new implementation of FIR Filter using DA architecture with and without use of embedded component like DSP units. The filter is designed and Co-simulated with the help of ‘filter design HDL Coder ’ and then synthesized using Xilinx ISE 13.3 Design suit. Result shows that DA based FIR filter design that utilizes basic logic resources g...

This paper presents efficient distributed arithmetic (DA)-based approaches for high-throughput reconfigurable implementation of finite impulse response (FIR) filters whose filter coefficients change during runtime. Conventionally, for reconfigurable DA-based implementation of FIR filter, the lookup tables (LUTs) are required to be implemented in RAM; and the RAM-based LUT is found to be costly for ASIC implementation. Therefore, a shared-LUT design is proposed to realize the DA computation. Instead of using separate registers to store the possible results of partial inner products for DA processing of different bit positions, registers are shared by the DA units for bit slices of different weightage. The proposed design has nearly 68% and 58% less area-delay product, and 78% and 59% less energy per sample than DA-based systolic structure and carry saved adder (CSA)-based structure, respectively for the ASIC implementation. A DRAM-based design is also proposed for the FPGA implementation of the reconfigurable FIR filter which supports up to 91 MHz input sampling frequency, and offers 54% and 29% less the number of slices than the systolic structure and the CSA-based structure, respectively when implemented in Xilinx Virtex-5 FPGA device (XC5VSX95T-1FF1136).

A 2-D discrete wavelet transform hardware design based on multiplier design based architecture is presented in this paper. We have proposed based on arithmetic for low complexity and efficient implementation of 2-D discrete wavelet transform. The multiplier design based technique has been applied to reduce the number of delay. This paper provides the clearcut idea in about the application of 8-multiplier and 6adder in one, two & three level of architecture This architecture is suitable for high speed on-line applications, the most important one being image processing, reduced the area and power in the discrete wavelet transform. With this architecture the speed of the 2-D discrete wavelet transform is increased. It has 100% hardware utilization efficiency KEYWORDS: 2-D Discrete wavelet transform (DWT), one level multiplier based design, two level multiplier based design, three level multiplier based design, multiplier based design scheme, Xilinx simulation. I.

This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DA-finite impulse response filter. This research paves a direction towards development of bio inspired computing architectures...

In this paper a module consisting of a Normalized Least Mean Square (NLMS) filter is modeled, implemented and verified on a digital signal processor (DSP) TMS320C7613 to eliminate acoustic noise, which is a problem in voice communications. However the acoustic noise cancellation (ANC) is modeled using digital signal processing technique especially Simulink Blocksets. The main scope of this paper is to implement the module onboard an autonomous DSK C6713 in real time, benefiting to the low computational cost and the easy implementation using Simulink programming. The needed DSP code is generated in code composer environment under Real Time Workshop. At the experimental level, implementation phase results verify that implemented module behavior is similar to Simulink model.

The aim of this paper is to design and simulate an AEC in order to enhance the quality of speech disturbed by echo phenomenon. Therefore, in order to design the normalized adaptive AEC, we have used digital signal processing techniques, especially Simulink embedded functions. Effectiveness of the suggested AEC using adaptive normalized algorithm was verified using Matlab/Simulink software. Finally, our AEC has been tested by using ERLE criteria and the analysis results show more efficiency according to ITU-T recommendation G.168.

Nowadays, in the field of communications, AEC (acoustic echo cancellation) is truly essential with respect to the quality of multimedia transmission. In this paper, we designed and developed an efficient AEC based on adaptive filters to improve quality of service in telecommunications against the phenomena of acoustic echo, which is indeed a problem in hands-free communications. The main advantage of the proposed algorithm is its capacity of tracking non-stationary signals such as acoustic echo. In this work the acoustic echo cancellation (AEC) is modeled using a digital signal processing technique especially Simulink Blocksets. The algorithm's code is generated in Matlab Simulink programming environment. At simulation level, results of simulink implementation prove that module behavior is realistic when it comes to cancellation of echo in hands free communication using adaptive algorithm. Results obtained with our algorithm in terms of ERLE criteria are confronted to IUT-T recommendation G.168.

Nowadays, in the field of communications, AEC (acoustic echo cancellation) is truly essential with respect to the quality of multimedia transmission. In this paper, we designed and developed an efficient AEC based on adaptive filters to improve quality of service in telecommunications against the phenomena of acoustic echo, which is indeed a problem in hands-free communications. The main advantage of the proposed algorithm is its capacity of tracking non-stationary signals such as acoustic echo. In this work the acoustic echo cancellation (AEC) is modeled using a digital signal processing technique especially Simulink Blocksets. The algorithm’s code is generated in Matlab Simulink programming environment. At simulation level, results of simulink implementation prove that module behavior is realistic when it comes to cancellation of echo in hands free communication using adaptive algorithm. Results obtained with our algorithm in terms of ERLE criteria are confronted to IUT-T recommen...

Very Large Scale Integration (VLSI) design is a technological advancement in electronics that has widely shortened the window from concept to a working prototype in any design. It has also made it possible to design and develop sophisticated and intelligent electronic systems which are easily adaptable to any field of human endeavor with relative ease. In this paper, the VLSI design of a processor system is presented, which implements two transforms i.e. the discrete wavelet packet, and the Hilbert transforms. The combination of these two transforms in a single processor makes it possible to have a system with enhanced subband frequency edge detection in a wideband signal and other specialized areas, which is very useful in such specialized areas of application as spectrum sensing in cognitive radio networks. The results obtained from the simulation and design verification of the processor system showed the effectiveness of the design methodology presented in this paper. As a matter...

Acoustic echo cancellation is a common occurrence in today's telecommunication systems. It occurs when an audio source and sink operate in full duplex mode; an example of this is a hands- free loudspeaker telephone. In this situation the received signal is output through the telephone loudspeaker (audio source), this audio signal is then reverberated through the physical environment and picked up by the systems microphone (audio sink). The effect is the return to the distant user of time delayed and attenuated images of their original speech signal. The signal interference caused by acoustic echo is distracting to both users and causes a reduction in the quality of the communication. This paper focuses on the use of RLS algorithm to reduce this unwanted echo, thus increasing communication quality.

Abstract-Acoustic echo cancellation is a common occurrence in today's telecommunication systems. It occurs when an audio source and sink operate in full duplex mode; an example of this is a hands-free loudspeaker telephone. In this situation the received signal is output ...

This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DA-finite impulse response filter. This research paves a direction towards development of bio inspired computing architectures...