Direct Digital Synthesis

This paper describes a fundamentally flexible low power transceiver implemented in 90 nm CMOS. Novel circuit architectures have been implemented to overcome problems that have encumbered wideband transceivers in the past. Flexible programming allows the RFIC to process signals of multiple wireless protocols from 100 MHz - 2.5 GHz with channel bandwidths from 8 KHz to 20 MHz. At 1.8 GHz the receiver noise figure is 7 dB with IP3 of -6 dBm and voltage gain of 48 dB. The transmitter has better than 40 dB carrier suppression, 35 dB sideband suppression, and EVM of 1% at 800 MHz. The frequency synthesizer uses direct digital synthesis to achieve instantaneous frequency switching and phase noise of -123 dBc/Hz at 25 KHz offset.

In the last thirty years, low power field programmable gate arrays (FPGAs) becoming more commonly used to implement a countless of applications in different electronics industry domains. Due to their flexible design, strong compatibility, parallel computing, and compared to the CPU architecture, FPGA accentuate computing efficiency and con sidered as one of the devices with the lowest application risk and the shortest development cycle among the variety of available programmable circuits families. This article details the design and implementation of a direct digital synthesis (DDS) signal generator using the Spartan-6 FPGA, focusing on highquality sine wave generation. The system utilizes look-up tables (LUTs) and Block RAM (BRAM) for efficient storage and retrieval of sine wave data, while an 8-bit DAC0808 digital-to-analog converter (DAC) ensures precise waveform output. The FPGA's reconfigurable architecture allows real-time adjustments of frequency and phase, making the design suitable for various signal processing applications and modulation techniques like binary phase shift keying (BPSK).

A low-complexity direct digital frequency synthesizer based on linear interpolation method is presented in this paper. The proposed architecture employs a new technique to derive the slope coefficients at the first sample of each segment's interval thereby eliminating the ROM which stores those values. ROM elimination has resulted in significant logic element saving and simplified the whole DDFS structure. The proposed DDFS has been analyzed using MATLAB and tested over entire Nyquist frequency range. The spurious free dynamic range (SFDR) of synthesized sinusoid achieved is 84 dBc. The resultant low complexity architecture along with high spectral purity synthesized signal meets the specifications of recent portable battery-driven products. Zastosowana technika pozwala na uzyskanie współczynnika pochyłości już z pierwszą próbką każdego z interwałów segmentów, przez co eliminowana jest konieczność użycia pamięci ROM. Przeprowadzono symulacje proponowanego rozwiązania w pełnym zakresie częstotliwości Niquist'a. Działanie metody zostało porównane z innymi znanymi architekturami. (Nowe podejście do projektowania bezpośredniego syntezatora cyfrowego o małej złożoności).

Multiplier is one of the most inevitable arithmetic circuit in digital signal design. Multipliers dissipate high power and occupy significant amount of the die area. In this paper, a low-error architecture design of the pretruncated parallel multiplier is presented. The coefficients word length has been truncated to reduce the multiplier size. This truncation scaled down the gate count and shortened the critical paths of partial product array. The statistical errors of the designed multiplier are calculated for different pre-truncate values and compared. The multiplier is implemented using Stratix III, FPGA device. The post fitting report is presented in this paper, which shows a saving of 36.9 % in resources usage, and a reduction of 17 % in propagation time delay.

The classical structure of linear interpolationbased phase-to-sine mapper (PSM) consists of at least two ROMs for polynomial coefficient storage. Other architectures may include extra ROM for storing residual errors. However, ROMs dissipate high power and occupy a significant amount of the die area. This study presents a new technique that eliminates the ROM by including the computation of segment initial coefficients in the hardware. Therefore, it becomes possible to trim down noticeable hardware resources. The proposed direct digital frequency synthesizer (DDFS) architecture has been encoded in VHDL and synthesized with Quartus II software. Post simulation results show that the proposed design is capable of achieving the theoretical spurious-free dynamic range (SFDR) upper bound when optimal polynomial coefficients are considered. For 32 piecewise linear segments, the SFDR of the synthesized sinusoid is 84.15 dBc. A ROM compression ratio of 597.3:1 was also achieved. The performance of the DDFS is compared with previously presented DDFS techniques and the results show that the proposed design has advantages of high ROM compression ratio and low hardware complexity.

A variety of nucleophiles provided by activated methylenes have been added on 3-(2-nitrovinyl)-1H-indole in very good to excellent yields, under sonication and solvent-free conditions, using solid potassium carbonate or sodium acetate as a base. Direct synthesis avoiding preliminary NH protection is reported and exemplified to 15 molecules.

The catalytic direct synthesis of hydrogen peroxide is a highly interesting alternative process to avoid the current anthraquinone route because implies significant sustainability improvements. Among all the peroxide applications, its use as electronic chemical requires very low metallic content. The employment of direct synthesis peroxide as raw material for ultrapurification process has not been investigated before, so its viability is still pending of evaluation.

This paper describes a fundamentally flexible low power transceiver implemented in 90 nm CMOS. Novel circuit architectures have been implemented to overcome problems that have encumbered wideband transceivers in the past. Flexible programming allows the RFIC to process signals of multiple wireless protocols from 100 MHz -2.5 GHz with channel bandwidths from 8 KHz to 20 MHz. At 1.8 GHz the receiver noise figure is 7 dB with IP3 of -6 dBm and voltage gain of 48 dB. The transmitter has better than 40 dB carrier suppression, 35 dB sideband suppression, and EVM of 1% at 800 MHz. The frequency synthesizer uses direct digital synthesis to achieve instantaneous frequency switching and phase noise of -123 dBc/Hz at 25 KHz offset.

1,2, 3,4 National Institute of Metrological Research, (INRiM) str. delle Cacce, 91 – 10135 (TURIN Italy) 1 Tel + 39 011 3919424, , fax +39011346384,[email protected]) 2 Tel + 39 011 3919336, , fax +390113919 334, [email protected]) 3 Tel + 39 011 3919424, fax +39011346384,[email protected]) 4 Tel + 39 011 3919425, Abstract-This paper describes a measurement circuit for the calibration of pico-ammeters in dc current. The system is based on a 100 MΩ Hamon network developed at INRIM to improve the traceability level of the maintained 1 GΩ standard. Besides the Hamon network, the measurement system, presented in this paper, consists of a precision dc voltage source and an electronic circuit used as voltage guard driver.

We report on the frequency performance of a low cost (~500$) radio-frequency sine wave generator, using direct digital synthesis (DDS) and a field-programmable gate array (FPGA). The output frequency of the device may be changed dynamically to any arbitrary value ranging from DC to 10 MHz without any phase slip. Sampling effects are substantially reduced by a high sample rate,

The synthesis of II-VI nanoplatelets has enabled virtually complete elimination of inhomogeneous spectral broadening and redefined the color purity of fluorescence emission achievable for colloidal nanomaterials. For a decade, a belief has risen that CdSe nanoplatelets cannot be directly synthesized with a thickness greater than 2.5 unit cells (~1.5 nm). In this work, we overcome this boundary by establishing a synthesis for six-monolayer-thick CdSe nanoplatelets. By simply introducing hydroxide or chloride ions in a standard CdSe nanoplatelet synthesis, six-monolayer thick nanoplatelets can be synthesized in high quality. We discuss the role of small ions on nanoplatelet nucleation and growth. This work demonstrates characteristics and possible applications of six-monolayer-thick CdSe nanoplatelets.

We investigate a novel ultrasonic motor which generates a stator trajectory in the form of a figure-of-eight by superimposing two resonant modes, with one double the frequency of the other. Topology optimization was used to design the stator structure. In contrast to traditional travelling wave ultrasonic motors, which require two modes to be driven 90° out of phase, only one amplifier is required to drive the proposed device. A prototype device was characterised experimentally and was used to drive a linear bearing at 14 mm/s reversibly and a force of 50 mN was developed by the motor.

A newly developed technique of synthesizing single-walled carbon nanotubes (SWNTs) directly on the surface of Si and quartz substrates is introduced in this report. This technique adopted a liquid-based dip-coating method to mount a very small amount of catalyst metals on the surface of substrates using Mo/Co bimetallic acetate solution. The merits of this approach lie in its easy, costless, and geometry-flexible nature compared with conventional sputtering and deposition approaches. We used the alcohol catalytic chemical vapor deposition (ACCVD) method that can produce relatively high-quality SWNTs even at low temperatures down to 600°C. This low-temperature process contributes to the prevention of the agglomeration of catalytic metals on the surface and chemical reaction between catalytic metal and silicon, which helps us to eliminate any kind of intermediating support materials. Thereby synthesized SWNTs on Si and quartz substrates under various CVD conditions are characterized by means of SEM, TEM, Raman scattering, and optical absorbance measurements. The underlying reasons our experimental procedure and choice of catalyst worked for the synthesis of SWNTs are discussed through comparative studies. At the end of this report, some possible applications of this technique are stated.

Everyone who is an amateur or student interested in electricity or electronics needs a signal generator that can produce different types of signals that must be located at the front edge. This requirement can often be met by equipment in the laboratories or signal generators received at high prices under the project. This study focuses on the design of a low cost signal generator having high accuracy and sensitivity. In previous studies, DDS (Direct Digital Synthesis) method was implemented with FPGA and other high cost microcontrollers. With this study, the design of the high-accuracy signal generator has been made simpler and more cost-effective thanks to the PIC microcontroller, which can be found easily in the market. The device designed in the study is a digital signal generator that produces sine, triangle and square wave which are created using decimal numbers in the microcontroller and converted to analog signal via DAC (Digital to Analog Converter). Also, the digital potentiometer on the device, which is used as feedback in the circuit, allows us to control the output signal. This study provides a solution for producing a low cost laboratory type signal generator having high sensitivity, however this solution is not a new method. Satisfactory results have been achieved from the implementation circuit.

This paper presents the development of a low-cost and portable interactive Sinusoidal signal generator which has been implemented on FPGA device. The sine wave is generated by using a Lookup Table method, where the sine values are precalculated and stored in the onboard memory. The frequency of the generated signal is modified by changing the value of the memory address incremental step. In addition, the implemented signal generator is serially connected to a graphical user interface (GUI) on a PC, which can be used to select the type of the desired signal to be generated and to set the signal frequency. The proposed design was successfully implemented in ALTERA Cyclone II DE0 FPGA Development Board, where the sine wave can be generated within the range of 1 kHz to 1 MHz, with 1 kHz frequency resolution.

This paper presents a low power, high speed SiGe DDS MMIC with 9-bit phase and 7-bit amplitude resolutions. This DDS MMIC is the first reported GHz range output DDS with direct digital frequency and phase modulation capabilities. Using more than eight thousand transistors, the DDS MMIC includes a 9-bit CLA accumulator for phase accumulation, a 9bit CLA adder for phase modulation and a 7-bit sine-weighted DAC. The core area of the DDS occupies 1.7×2.0 mm 2 . The DDS consumes low power of 2.0 W under a 3.3 V single power supply even with the added modulation blocks. The narrow band spurious-free-dynamic range (SFDR) is measured as 35dBc with the maximum update frequency of 2.9 GHz. The DDS MMIC is packaged and tested in an LCC-44 cavity.

This paper describes a 9-bit 6.2-GHz low power quadrature direct digital synthesizer (DDS) implemented in a 0.18-m SiGe BiCMOS technology. With a 9-bit pipeline accumulator and two 8-bit sine-weighted current steering DACs, this DDS is capable of generating quadrature sinusoidal waveforms up to 3.15 GHz with a maximum clock frequency of 6.2 GHz. Packed with more than 13 500 transistors, the quadrature DDS occupies an active area of 2.3 2.5 mm 2 and a total die area of 3.0 3.0 mm 2 . The measured spurious-free dynamic range is approximately 26 dBc at a clock frequency 6.2 GHz. At the maximum clock frequency, the power consumption of the DDS is 2.5 W with 3.3-and 4.0-V power supplies for the digital and analog parts, respectively. The DDS thus achieves a power efficiency figure-of-merit of 5.04 GHz/W/phase. The DDS chips were packaged with 48-pin ceramic leadless chip carriers and air cooling was used during the measurement.

Two low-power sine-output Direct Digital Frequency Synthesizers have been fabricated in 0.18 pm CMOS, tested and characterized. The first IC has a 16-bit phase accumulator and it generates a single phase sinusoidal digital sequence with 60 dBc of Spurious Free Dynamic Range. Core power consumption is as low as 15 pW/MHz. The second IC has a 32-bit phase accumulator and it generates quadrature sinusoidal digital sequences with 84 dBc of Spurious Free Dynamic Range. Its core consumes as little as 220 pW/MHz. Both ICs employ an efficient linear interpolation scheme for sinusoidal functions, developed by the authors.

Direct digital synthesis (DDS) technology is used to generate and modify high-quality waveforms in a broad range of applications in such diverse fields as medicine, industry, instrumentation, communications, and defense. This article provides an overview of the technology, describes its benefits and limitations, and takes a look at some application examples— and new products that make the technology more readily available.

This paper presents an implementation of Function Generator using Field Programmable Gate Array (FPGA).. The proposed Function Generator is first described in Very High Speed Integrated Circuit Hardware Description language (VHDL) and the description is verified using ModelSim SE 10.1 E from Model Tech. This function generator is built with same facilities which are available in function generator for practical implementation in lab. Which provide signals like Sine, square, triangular and ramp waveforms. This modified Function Generator is compact in size and re-configurable. This paper focuses on advantage of soft core over hard core by providing flexibility in modifying variation in frequency and waveform selection by using rotary switch button .

Wireless sensors networks can be deployed in remote locations due to they do not need a fixed infrastructure. Therefore, energy scavenging systems are really important to provide the energy necessary to the sensor nodes and thus maximize its lifetime. This work presents the modeling and assessing of an energy-aware power-supply system for the Iris platform sensor. Theoretical models have been developed in order to estimate the energy in the energy storage supercapacitor depending on the incoming and outgoing energy. These models can be used to verify that the power-supply system provides enough energy to the sensor node under the most adverse weather conditions, and thus assuring the perpetual operation of the sensor nodes without human intervention. Also, these models will be implemented in a software module that makes possible the estimation of the sensor nodes' lifetime in function of their actual state of energy. The theoretical results given by these models have been compared with the results obtained with the real circuit. The comparison between both proves that the theoretical models are valid for the prediction of the future estate of energy based on the actual estate of energy. i Table of Contents Chapter 1 Introduction .

In this paper is presented a specific realization of 2-axe hydraulic vibration exciter, i.e. hydraulic pulsator (vibrator), with the driving system based on hydraulic servo drive and high performances signal generator. This mechanical system presents a part of testing laboratory for vibration influence on a human body researching, with ride comfort point of view. Signal generator is based on Direct Digital Synthesis method (DDS), with possibility of choosing different excitation types (sine wave, triangular wave or stochastic signal) and frequency and amplitude fine tuning. Different signal generation, with frequency range (0.1-31.5) Hz and amplitude range (0-50) mm, is detailed presented. Experimental results of hydraulic platform displacement (oscilloscopic waveforms and spectrum in frequency domain) over both axes and real mass load for different excitation types from signal generator are presented too.

The problem of resource allocation to maximize the outage exponent over a fading relay channel using the decode-and-forward protocol with quantized channel state feedback (CSF) is studied. Three different scenarios are considered: relay-to-source, destination-to-relay, and destination-to-source-and-relay CSF. In the relay-to-source CSF scenario, it is found that using merely one bit of CSF to control the source transmit power is sufficient to achieve the multiantenna upper bound in a range of multiplexing gains. In the destination-to-relay CSF scenario, the systems slightly outperform dynamic decode-and-forward (DDF) at high multiplexing gains, even with only one bit of feedback. Finally, in the destination-to-source-and-relay CSF scenario, if the source-relay channel gain is unknown to the feedback quantizer at the destination, the diversity gain only grows linearly in the number of feedback levels, in sharp contrast to an exponential growth for multiantenna channels. In this last scenario, a simple scheme is shown to perform close to the corresponding upper bound. Index Terms-Cooperative communications, diversity methods, diversity-multiplexing tradeoff, fading channels, large-deviation analysis, power control, relay channels. I. INTRODUCTION M OTIVATED by the potential of having simple single-antenna communication nodes cooperate and approach the promising performance of multiantenna systems, there has been a renewed interest in the classical relay channels [1], [2], for example in the recent work [3]-[8]. Resource allocation for relay channels is known to enhance the performance significantly in many different scenarios [9]-[15]. Most previous work on resource allocation, however, assumed perfect network state information at both the source and the relay. In [16], power control

In the International System of Units, the impedance units can be realized from the quantum Hall effect, a macroscopic quantum phenomenon producing quantized resistance values. Established experiments employ individual GaAs devices [1], but novel materials such as graphene can be exploited to realize the units with relaxed experimental conditions. Furthermore, simple traceability chains can be implemented with novel digital impedance bridges. By combining novel digital impedance bridges and graphene quantum standards, an easy-to-operate and affordable impedance standard has been developed in the framework of the European EMPIR project 18SIB07 GIQS (Graphene Impedance Quantum Standards). An onsite comparison of an electronic and a Josephson impedance bridge developed at INRIM (Istituto Nazionale di Ricerca Metrologica, Italy) together with POLITO (Politecnico di Torino, Italy) and at PTB (Physikalisch-Technische Bundesanstalt, Germany), respectively, were organized for their mutual validation in the realization of the farad from graphene quantum standards. The result of the comparison and the last progresses of the GIQS project are here presented.

Cable modem specifications: Maxim Integrated Circuits (MAX5882). 2 Cellular base station specifications: Texas Instruments (DAC39J84). BW based on LTE 5x pre-distortion. 3 Satellite specifications: E2V (EV12DS130). BW based on C-band satellite. 4 Radar specifications: Maxim Integrated Circuits (MAX19693). BW based on X-band radio location.

This paper presents a novel algorithm and architecture for digital frequency synthesis (DFS). It is based on a simple difference equation. Simulation results show that the proposed DFS algorithm is preferable to the conventional phase-locked-loop frequency synthesizer and the direct digital frequency synthesizer in terms of the spurious-free dynamic range (SFDR) and the peak-signal-to-noise ratio (PSNR). Specifically, the results of SFDR and PSNR are more than 186.91 dBc and 127.74 dB, respectively. Moreover, an efficient DFS architecture for VLSI implementation is also proposed, which has the advantage of saving hardware cost and power consumption.

This paper presents a hybrid COordinate Rotation DIgital Computer (CORDIC) algorithm for designs and implementations of the direct digital frequency synthesizer (DDFS). The proposed multiplier-less architecture with small ROM (4 16 ×-bit) and pipelined data path provides a spurious free dynamic range (SFDR) of more than 84.4 dBc. A SoC (System on Chip) has been designed by m. μ 18 0 1P6M CMOS, and then emulated on the Xilinx FPGA. It is shown that the hybrid CORDIC-based architecture is suitable for VLSI implementations of the DDFS in terms of hardware cost, power consumption, and SFDR.

The current energy scenario suggests the need to search for and apply alternative energy sources to be used in addition to the electric energy supply system and contribute to the reduction of environmental impacts. This paper presents the sizing and the simulation of an autonomous led lighting system, composed of supercapacitors. The first block consists in a photovoltaic panel; a Buck DC/DC converter; supercapacitors and a MPPT controller, which has the main purpose of managing the functioning of the led lighting, using the algorithms of constant voltage in order to find the MPPT point of the photovoltaic panel; and the second block contains a Boost DC/DC converter; high efficiency led lights and a PWM controller. The aim of this paper consist of presenting the feasibility of the use of the supercapacitor as an energy storage element and the presentation of a new public lighting system, in order to achieve a better use of power supplied by a solar panel using a second Buck DC/DC converter. The results have been obtained by the use of the Matlab software, which led to a conclusion that the system is efficient, and it meets all the needs proposed before.

Swrm ARCHITECTURE The low level rf control system for the 23 MHz, 1MW rf A simplified block diagram of the system is shown in drive of the TRIUMF cyclotron is being completely Figure 1. redesigned using state-of&t hardware and software. " Frequency control using direct digital synthesis provides good frequency resolution, as well as allowing rapid changes in frequency. Digital signal processors (DSPs) are used in the amplitude and phase regulators. This permits adaptive control of feedback parameters, and eliminates drift due to component aging. The entire system is housed in a single c.::~-- VXI mainframe, which provides a low noise environment for feedbDck the feedback control circuitry. Functional modularity is provided by different plug-in modules. Local intelligence in the VXI controller automates the logically intensive routines such as power-up sequencing. It also provides supervisory . controls to the rest of the modules and communicates with the site-wide control syste...

A new ultrasound digital transcranial Doppler system (digiTDS) is introduced. The digiTDS enables the diagnosis of intracranial vessels and the assessment of the blood flow. The device can display a color map of flow velocities in time-depth domain and a spectrogram of Doppler signal obtained at a selected depth. The system offers the multigate processing which allows to display simultaneously a number of spectrograms and to reconstruct a flow velocity profile. The digital signal processing in the digiTDS is divided between hardware and software. The hardware part, based on the FPGA, executes a signal demodulation and reduces the data stream. The software part, executed on the PC, performs the Doppler processing and the visualization. The hardware-software partitioning enables building of a flexible Doppler platform at a relatively low cost. The detailed description of the system internals and the algorithm optimization are presented. The digiTDS is a new useful tool for transcrania...

A signal generator, also known variously as function generator or frequency generator is an electronic device that generates repeating or non-repeating electronic signals. The objective is to build a Sine/Square wave generator based on the Analogue Devices AD9832 Direct Digital Synthesis (DDS) Generator chip which is capable of generating high accuracy waveforms. The controller chip is a Microchip PIC16F877A. Going digital allows to set the output frequency exactly from 0,1Hz to 1MHz in 0,1Hz resolution steps, and there is effectively no drift with temperature or time as the output frequency is crystal locked.

This paper presents a novel, memoryless, read-only memory (ROM) design architecture for a direct digital frequency synthesizer (DDFS). A pipelining technique is proposed to increase the phase accumulator (PA) throughput. However, this technique increases the number of registers as the pipeline stages increase. The shifted clocking technique is used to reduce the pipelined PA registers. The wave symmetry technique is applied to store (0: π /2) of the sine wave. The ROM is partitioned into three four-bit sub-ROMs based on the angular decomposition technique and trigonometric identity. A novel approach of memoryless ROM design technique is proposed and implemented in the design of a 24bit DDFS system that replaces the conventional ROM. Replacing the memoryless sub-ROM circuits, instead of the conventional 12-bit ROM, reduces power consumption and area dimension. As a result, compared to the conventional ROM circuit, the values of area dimension and dynamic power are reduced by 15% and 14.8%, respectively.

An 8-bit fully digital synthesizer is proposed in this paper. Utilizing a phase to sinusoidal code interface is the outstanding difference of this structure versus its other counterparts. In order to achieve higher operation speed an 8 bit pipeline accumulator is used in proposed structure. The phase to sinusoidal interface along with linear DAC makes the Direct Digital Synthesizer (DDS) needless of conventionally used ROM look up table memory. Meanwhile the ASIC sine weighted DAC which requires specifically handled dynamic element matching (DEM) procedure and sophisticated layout techniques to enhance the resolution in accordance with the DDS specifications is eliminated. The intrinsic thermometric nature of the utilized phase to sinusoidal converter makes the system needless of binary to thermometer block required for segmented DACs. While simplifying the DDS overall configuration, the proposed structure makes it also possible to use the sinusoidal digital codes to be compared wit...

A general, mild, and versatile synthesis of the challenging α-aryl-β-ketosulfoxonium ylides has been developed for the first time, substituting traditional methods starting from diazo compounds. The arylation of easily accessible βketosulfoxonium ylides using aryne chemistry allowed the preparation of a large scope of the pro-chiral ylides in very good yields (40 examples; up to 85%). As applications, these ylides were smoothly converted into α-aryl ketones after desulfurization in good yields (up to 98%) as well as in other important derivatives.

This paper presents the development of a low-cost and portable interactive Sinusoidal signal generator which has been implemented on FPGA device. The sine wave is generated by using a Lookup Table method, where the sine values are precalculated and stored in the onboard memory. The frequency of the generated signal is modified by changing the value of the memory address incremental step. In addition, the implemented signal generator is serially connected to a graphical user interface (GUI) on a PC, which can be used to select the type of the desired signal to be generated and to set the signal frequency. The proposed design was successfully implemented in ALTERA Cyclone II DE0 FPGA Development Board, where the sine wave can be generated within the range of 1 kHz to 1 MHz, with 1 kHz frequency resolution.

The main goal of this paper is to present a novel ROM-less direct digital frequency synthesizer for sweep instrumentation systems. It provides a main sweep channel for frequency analysis and a reference channel for phase and amplitude measurement block operating at constant frequency. For phase to amplitude converter, we propose a new trigonometric approximation technique based on a set of reference angles. In addition, we present the design of the proposed synthesizer and its evaluation in Matlab-Simulink environment. The simulation results illustrate the performances and demonstrate the effectiveness of our proposed circuit.

This paper presents a digital signal processing system specially designed for eddy currents non-destructive testing. This new system has a Field Programmable Gate Array based processing core, several communication interfaces, data conversion and analog devices to interface the probes. Communication with personal computers is ensured by Ethernet 10/100 and USB 2.0 High Speed interfaces. The proposed architecture enables to set several combinations of peripherals cards to generate or acquire probe signals. Also, the new system allows the digital generation and analysis of the probe signals through multiple digital signal processing algorithms. Two different peripheral cards have been developed to meet the needs for the new IOnic concept of eddy currents probe. The IOnic acquisition card is composed by a programmable gain amplifier and a high speed analog to digital converter. The current stimulus generation is achieved with a digital to analog converter and a high output current transconductance amplifier. Together, the two peripherals are able to operate the probe from 10 kHz up to 10 MHz. An additional peripheral card to interface stepper motors was designed and used for sensor positioning.

In this paper a new non-destructive testing (NDT) system focusing on micro size superficial defects in metals is presented. The innovative system is composed by a new type of eddy currents probe, electronic devices for signal generation, conditioning and conversion, automated mechanized scanning and analysis software. The key original aspect of this system is the new type of eddy currents probe. This new IOnic probe provides enhanced lift-off immunity and improved sensitivity for micro size imperfections. The probe concept was studied using a Finite Element Modeling (FEM) tool and experimental verified using a standard defect. The testing results on some Friction Stir Welding (FSW) specimens clearly show that the system is able to detect cracks about 50 µm depth, which significantly increases the actual state of the art in NDT reliability for micro imperfections detection. The system can be applied to a broad range of industries which include manufacturing, maintenance and engineering companies.

In this paper, a new method for equivalent circuit modeling of a traveling wave ultrasonic motor is presented. The free stator of the motor is modeled by an equivalent circuit containing complex circuit elements. A systematic approach for identifying the elements of the equivalent circuit is suggested. The Levenberg-Marquardt parameter estimation algorithm is used to model the alteration of the admittance after placing the rotor on the stator. Thereafter, theoretical assessments and experimental measurements are used to account for the speed reduction that is caused by placing the rotor on the stator and applying the load torque. Finally, the effects of temperature changes and the resultant response of the motor are computed. Results of the experiments and measurements are used to verify and validate the precision of the new modeling method.

In this paper, a novel design approach for a phase to sinusoid amplitude converter (PSAC) has been investigated. Two segments have been used to approximate the first sine quadrant. A first linear segment is used to fit the region near the zero point, while a second fourth-order parabolic segment is used to approximate the rest of the sine curve. The phase sample, where the polynomial changed, was chosen in such a way as to achieve the maximum spurious free dynamic range (SFDR). The invented direct digital frequency synthesizer (DDFS) has been encoded in VHDL and post simulation was carried out. The synthesized architecture exhibits a promising result of 90 dBc SFDR. The targeted structure is expected to show advantages for perceptible reduction of hardware resources and power consumption as well as high clock speeds.

This paper deals with the design & implementation of a Digital Modulator based on the FPGA. The design is implemented using the Enhanced Direct Digital Synthesis (DDS) Technology. The basic DDS architecture is enhanced with the minimum hardware to facilitate the complete system level support for different kinds of Modulations with minimal FPGA resources. The size of the ROM look up is reduced by using the mapping logic. The Design meets the present Software Define Radio (SDR) requirements and provides the user selection for desired modulation technique to be used. The VHDL programming language is used for modeling the hardware blocks for powerful and flexible programming and to avoid VHDL code generation tools. The design is simulated in the ModelSim Simulation Tool and Synthesized using the Xilinx ISE Synthesis Tool. The architecture is implemented on the SPARTAN-3A FPGA from Xilinx Family in the SPARTAN-3A evaluation board. The experimental results obtained demonstrate the usefulness of the proposed system in terms of the system resources, its capabilities for design, validation and practical implementation purposes.

This paper deals with the design & implementation of a Digital Modulator based on the FPGA. The design is implemented using the Enhanced Direct Digital Synthesis (DDS) Technology. The basic DDS architecture is enhanced with the minimum hardware to facilitate the complete system level support for different kinds of Modulations with minimal FPGA resources. The size of the ROM look up is reduced by using the mapping logic. The Design meets the present Software Define Radio (SDR) requirements and provides the user selection for desired modulation technique to be used. The VHDL programming language is used for modeling the hardware blocks for powerful and flexible programming and to avoid VHDL code generation tools. The design is simulated in the Model Sim Simulation Tool and Synthesized using the Xilinx ISE Synthesis Tool. The architecture is implemented on the SPARTAN-3A FPGA from Xilinx Family in the SPARTAN-3A evaluation board. The experimental results obtained demonstrate the useful...

A concise, one-step route to indazolones from primary alkyl amines and o-nitrobenzyl alcohols is reported. The key step in this readily scalable indazolone forming process involves base-mediated in situ o-nitrobenzyl alcohol → onitrosobenzaldehyde conversion. Although this functional group interconversion is known to be useful for 2H-indazole synthesis, its reactivity was modulated for indazolone formation.