LOOP FILTER

In this paper we have designed and implemented two all-digital phase-locked loop models one with an XOR gate as phase detector and the other with edge triggered JK flip flop as Phase Detector. The proposed models are implemented by using Very High Speed Integrated Circuit Hardware Description Language. The simulation has been performed in ISE Xilinx 14.2 software platform to study the power consumptions and synthesis characteristics of the models. The power consumptions of the models are evaluated from Xilinx Power Estimator. It is observed that the power consumption of the model with XOR gate and with edge triggered JK FF phase detector are recorded to be 15 mW and 21 mW respectively at ambient temperature of 25° C.

Control Parameters design of a three-phase synchronous reference frame phase locked loop (SRF-PLL) with a pre-filtering stage (acting as the sequence separator) is not a trivial task. The conventional way to deal with this problem is to neglect the interaction between the SRF-PLL and pre-filtering stage, and treat them as two separate systems. This approach, although very simple, is not optimum as the pre-filtering stage and the SRF-PLL may have comparable dynamics. The aim of this paper is to develop a systematic and efficient approach to design the control parameters of a SRF-PLL with pre-filtering stage. To this end, the paper first optimizes the performance of the filtering stage in detection of the sequence components. The paper then proceeds to reduce the interaction between the filtering stage and SRF-PLL, which is achieved by employing a derivative-filtered proportional-integral-derivative controller as the loop filter (instead of the commonly adopted proportionalintegral controller) and arranging a pole-zero cancellation. The suggested method is simple and efficient, and is applicable to the joint operation of different sequence separation techniques and the SRF-PLL. The effectiveness of the suggested design approach is confirmed through extensive experimental results.

This paper introduces a design aspects of low power phase locked loop using VLSI technology.The phase locked loop is designed using latest 45nm process technology parameters, which in turn offers high speed performance at low power. The main quality related to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnect dielectric described.

In this paper fast locking CMOS phase locked loop is proposed. It is designed using Cadence virtuoso gpdk 45nm CMOS technology. It is used 1 volt power supply for operation of the circuit. This proposed circuit will be very useful in clock generation in microprocessor, frequency synthesizer for cell phone, fast locking in digital aid circuits.

All Digital Phase Lock Loop (ADPLL) is contributing in advancement in digital communication and control system since 1980. In this paper “High speed ADPLL for FM application” is proposed. The ADPLL is designed using phase detector, digital loop filter and increment-decrement counter. Here the speed of ADPLL is increased by using novel multiplexer based increment– decrement counter. The ADPLL using these blocks are simulated by using Xilinx 14.5. It is observed that the delay of proposed ADPLL is less compare to existing ADPLL [1]. Further, the proposed ADPLL is used to generate FM modulation by using interpolator method.

All Digital Phase Lock Loop (ADPLL) is contributing in advancement in digital communication and control system since 1980. In this paper “High speed ADPLL for FM application” is proposed. The ADPLL is designed using phase detector, digital loop filter and increment-decrement counter. Here the speed of ADPLL is increased by using novel multiplexer based increment– decrement counter. The ADPLL using these blocks are simulated by using Xilinx 14.5. It is observed that the delay of proposed ADPLL is less compare to existing ADPLL [1]. Further, the proposed ADPLL is used to generate FM modulation by using interpolator method.

Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8V . It has power consumption of 1.39 mW at 125 MHz center frequency with locking range from 0.5 MHz to 250 MHz.

Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8V. It has power consumption of 1.39 mW at 125 MHzcenter frequency with locking range from 0.5 MHzto 250 MHz. 1. INTRODUCTION In the era of recent development in deep submicron technologies, requires high operating frequency of VLSI systems and subsystems. High speed ICsrequiresproperlysynchronized on-chip clock signals for their operation. For clock synchronization operation in microprocessors and memory ICs, delay locked loop (DLL) and phase locked loop (PLL) are used to diminish the effect of jitter and skews of clock signals [1]. In DLL, VCDL is used in place of VCO which makes it differ from PLL. If frequency multiplier operation is not needed then a DLL is preferred over PLL because of high stability, less locking time and no jitter accumulation [2],[3]. DLL has a wide number of applications such as clock generators in DRAM ICs, microprocessors, clock de-skewing circuits [4],[5]. Locking time, lock range and jitter performance, static phase error, low power consumption and immunity against process voltage temperature loading (PVTL) variations are the most important metrics of a DLL. A DLL can be realized by a number of architectures; analog and digital DLLs are the two most important types among them [6]. Analog DLLs have better performance in terms of jitter, layout area, power supply rejection ratio, power consumption and clock skew. This paper introduces a mixed mode DLL in which single ended differential pair based VCDL is used which provides high stability against temperature and power supply variations. The proposed circuit depicts superior performance in terms of speed, power consumption, and locking range. The organization of remaning four sections are starting with architecture of basic DLL followed by analysis of different blocks, simulation results and conclusion.

In This Paper, We Propose A Novel Design Of Adpll Which Should Operate In Synchronous With Dual Clock Memory. The Main Blocks Of Adpll Such As Digital Controlled Oscillators Are Implemented With A New Method In Digital Domain For Better Performance. The Digital Controlled Oscillator Is Designed Using Modified Counters Which Reduce The Delay Compared To Traditional Methods. The Increment Decrement Counter Is Modified From Previous Work And Is Designed Using Mux. 200 Hz Is The Central Frequency And Operational Frequency Range Is 997.0089 Hz To 1008.64 Hz Which Is The Lock Range Of The Design. Further The Adpll Is Designed Using Vhdl Language, Synthesized Using Xilinx Ise 14.5 And Implemented Using Xilinx System Generator For Data Serialization Using Spartan 6 Lx45 Fpga Board.

This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 10.1 Simulator is used for simulating Verilog Code.This paper gives details of the basic blocks of an ADPLL. In this paper, implementation of ADPLL is described in detail. Its simulation results using Xilinx are also discussed. It also presents the FPGA implementation of ADPLL design on Xilinx vertex5 xc5vlx110t chip and its results. The ADPLL is designed of 200 kHz central frequency. The operational frequency range of ADPLL is 189 Hz to 215 kHz, which is lock range of the design.