Leakage Current

Both in electrodialysis and in reverse electrodialysis ionic shortcut currents through feed and drain channels cause a considerable loss in efficiency. Model calculations based on an equivalent electric system of a reverse electrodialysis stack reveal that the effect of these salt bridges could be reduced via a proper stack design. The critical parameters which are to be optimized are ρ/r and R/r, where ρ is the lateral resistance along the spacers, R is the resistance of the feed and drain channels between two adjacent cells, and r is the internal resistance of a cell. Because these two parameters are dimensionless, different stacks can be easily compared. The model is validated with two experimental stacks differing in membrane type and spacer thickness, one with large ionic shortcut currents and one where this effect is less. The loss in efficiency decreased from 25 to 5% for a well-designed stack. The loss of efficiency in reverse electrodialysis and in electrodialysis can be reduced with the aid of the design parameters

This paper presents the design and optical gain analysis of a Ga₀.₄₅In₀.₅₅P/AlGaInP nanoscale quantum well heterostructure for visible-light-emitting applications. The proposed structure consists of a 4 nm GaInP quantum well and 10 nm AlGaInP barrier layers grown on a GaAs substrate. The electronic band structure and carrier wave functions are analyzed using the k•p method to investigate carrier confinement and optical transition characteristics. The results confirm the formation of a type-I heterostructure, providing efficient confinement of electrons and holes within the active region. The optical gain spectrum exhibits a peak gain of approximately 4850 cm⁻¹ at 625 nm (1.985 eV), corresponding to the red region of the visible spectrum. The enhanced gain is attributed to strong quantum confinement and improved electron-hole recombination within the quantum well. The obtained results demonstrate the potential of the proposed GaInP/AlGaInP heterostructure for high-efficiency visible-light emitters, semiconductor lasers, and integrated photonic devices.

The potential model has been obtained from analytical solution of 2-D Poisson's equation under depletion approximation. The 2-D Poisson's equation has been solved with boundary conditions specific to the structure. Here the boundary conditions are the electrostatic potentials and electric field at the source end and at the drain end for longitudinal direction and the electrostatic potentials at the gate oxide-semiconductor boundary and middle of the channel along transverse direction. In the source and drain region the effective oxide thickness variation due to the geometric shape of the spacer has also been determined and presented in the paper. The mathematical model thus obtained is validated by the comparison of the potential profile of the device obtained from model and TCAD simulations. Both longitudinal and transverse potential profiles of the device for various gate dielectrics, doping concentration, gate oxide thickness and drain voltages have been obtained from the model as well as from TCAD numerical simulations have been compared. The close agreement of the analytical model with numerical simulations ensures the validity of the model.

Efficient atomistic simulators are required for full band treatments in strongly quantum confined systems, and for simulation of transport in emerging materials and devices such as graphene. Here we present an efficient transmission matrix based approach to ballistic quantum transport calculation for full three-dimensional, nearest-neighbor tight-binding based atomistic simulations. The method is then used to demonstrate how band-to-band tunneling increases the leakage current in OFF state in field-effect transistors with low band gap semiconductors such as InSb as channel material.

An amorphous-silicon thin-film transistor (TFT) process with a 180 • C maximum temperature using plasmaenhanced chemical vapor deposition has been developed on both novel clear polymer and glass substrates. The gate leakage current, threshold voltage, mobility, and on/off ratio of the TFTs are comparable with those of standard TFTs on glass with deposition temperature of 300 • C-350 • C. Active-matrix pixel circuits for organic light-emitting displays (LEDs) on both glass and clear plastic substrates were fabricated with these TFTs. Leakage current in the switching TFT is low enough to allow data storage for video graphics array timings. The pixels provide suitable drive current for bright displays at a modest drive voltage. Test active matrices with integrated polymer LEDs on glass showed good pixel uniformity, behaved electrically as expected for the TFT characteristics, and were as bright as 1500 cd/m 2 .

WHAT IS A CAPACITOR? A capacitor is a fundamental passive electronic component designed to store electrical energy within an electric field. It achieves this energy storage by accumulating opposite electrical charges on two separate, closely positioned conductive plates that are completely isolated from one another by an insulating material known as a dielectric. Unlike chemical batteries, capacitors can discharge their stored electrical energy rapidly, making them indispensable for power conditioning, signal filtering, and high-frequency timing circuits.

Made by Mahammad Mammadov, Fikrat Gurbanov, Murad Shirinov, Emil Rozenberg

Checked by Physics Teacher Telman Askeraliyev

We report on temperature, time, and voltage dependent resistive hysteresis measurements of BaTiO3-ZnO heterostructures grown on (001) Si substrates by pulsed laser deposition. We observe a diodelike behavior and cycling-voltage dependent hysteresis formation under forward bias. We explain these effects with depletion layer formation between the ZnO and BaTiO3 layers, an additional barrier due to the spontaneous polarization of ZnO and the ferroelectric nature of BaTiO3. The disappearance of the resistive hysteresis above the ferroelectric-paraelectric phase transition temperature of BaTiO3 conformed that the hysteresis is related to the ferroelectricity of BaTiO3. Time dependent resistance measurements reveal memory effects.

We present a new accumulation-mode structure for silicon carbide laterally diffused MOSFET. Key parameters that alter the device performance have been optimized using the device simulator MINIMOS-NT. The relationship between blocking and driving capability of the structure has been analyzed. Excellent I-V characteristics with significant improvement on the reduction of the gate bias voltage has been achieved. A blocking voltage of 1460 V with a small leakage current, a considerably lower specific on resistance of 93 mΩ • cm 2 and a fairly large advantage on electrical performance and device reliability were achieved.

We demonstrate an approach for probing nonlinear electromechanical responses in BiFeO 3 thin film nanocapacitors using half-harmonic band excitation piezoresponse force microscopy (PFM). Nonlinear PFM images of nanocapacitor arrays show clearly visible clusters of capacitors associated with variations of local leakage current through the BiFeO 3 film. Strain spectroscopy measurements and finite element modeling point to significance of the Joule heating and show that the thermal effects caused by the Joule heating can provide nontrivial contributions to the nonlinear electromechanical responses in ferroic nanostructures. This approach can be further extended to unambiguous mapping of electrostatic signal contributions to PFM and related techniques.

We have developed a test structure for evaluating the quality of Al2O3 gate dielectrics grown on graphene for graphene field effect transistors on flexible substrates. The test structure consists of a metal/dielectric/ graphene stack on a PET substrate and requires only one lithography step for the patterning of the topside metal electrodes. Results from measurements of leakage current, capacitance and loss tangent are presented.

We have developed a test structure for evaluating the quality of Al2O3 gate dielectrics grown on graphene for graphene field effect transistors on flexible substrates. The test structure consists of a metal/dielectric/ graphene stack on a PET substrate and requires only one lithography step for the patterning of the topside metal electrodes. Results from measurements of leakage current, capacitance and loss tangent are presented.

A novel high voltage rectifier, called the Trench Oxide PiN Schottky (TOPS) rectifier, is described in this paper. The TOPS rectifier is a synergistic combination of a Schottky rectifier and a P +iN diode, using a trench oxide structure to achieve high aspect ratio P+ regions, which permits a superior trade-off between forward voltage drop and switching characteristics, as compared

We report the fabrication process as well as material and electrical characterization of ultra thin body (UTB) thin film transistors (TFTs) for stackable nonvolatile memories by using in situ phosphorous doped low-temperature polysilicon followed by the chemical mechanical polishing (CMP) process. The resulting polysilicon film is about 13 nm thick with approximately 10 19 cm À3 doping. Root mean square surface roughness below 1 nm is achieved. Metal nanocrystals and high-k dielectric are selected for storage nodes and tunneling barriers to achieve low operating voltages. The number density and average diameter of nanocrystals embedded in the gate stack are 7.5 Â 10 11 cm À2 and 5.8 nm, respectively. Furthermore, scanning transmission electron microscopy (STEM), convergent beam electron diffraction (CBED) and electron energy loss spectroscopy (EELS) are performed for material characterization. The dielectric constant of the (Ti, Dy) x O y film is 35, and the off-state leakage current at À1 V bias and 2.8 nm equivalent oxide thickness is 5 Â 10 À7 A/cm 2 . We obtain a memory window of about 0.95 V with ±6 V program/erase voltages. Our results show that UTB TFT is a promising candidate for the three-dimensional integration in high-density nonvolatile memory applications.

A study, based on MATLAB, of Zn1-xMgxO/ZnO High Electron Mobility Transistors (HEMT) is presented. In this work, we have focused on the sheet density (ns) of the two-dimensional electron gas (2DEG) versus gate-source bias (Vgs) for different Mg fractions and the characteristics Ids-Vds at various gate-source biases taking into consideration both spontaneous and piezoelectric polarization contributions to interfacial charge. Results show that increasing Mg content enhances 2DEG density up to practical limits. The I-V curves exhibit the expected linear to saturation behavior and clear transconductance roll off at low Vgs. These findings offer clear design guidelines for optimizing Zn1-xMgxO/ZnO HEMTs in power and RF applications.

We report on a 275-425-GHz tunerless waveguide receiver with a 3.5-8-GHz IF. As the mixing element, we employ a high-current-density Nb-AlN-Nb superconducting-insulatingsuperconducting (SIS) tunnel junction. Thanks to the combined use of AlN-barrier SIS technology and a broad bandwidth waveguide to thin-film microstrip transition, we are able to achieve an unprecedented 43% instantaneous bandwidth, limited by the receiver's corrugated feedhorn. The measured double-sideband (DSB) receiver noise temperature, uncorrected for optics loss, ranges from 55 K at 275 GHz, 48 K at 345 GHz, to 72 K at 425 GHz. In this frequency range, the mixer has a DSB conversion loss of 2.3 1 dB. The intrinsic mixer noise is found to vary between 17-19 K, of which 9 K is attributed to shot noise associated with leakage current below the gap. To improve reliability, the IF circuit and bias injection are entirely planar by design. The instrument was successfully installed at the Caltech Submillimeter Observatory (CSO),

Transformerless inverters are increasingly favored in grid-connected photovoltaic (PV) systems due to their higher efficiency, reduced size, and lower cost. This paper presents a novel transformerless inverter topology that integrates buck boost conversion with an advanced fuzzy logic controller (FLC) to enhance energy extraction and power quality under dynamically changing solar conditions. The proposed system employs a sine triangle pulse width modulation (PWM) scheme in conjunction with the FLC to improve waveform quality and system responsiveness. By dynamically adapting to variations in irradiance and load, the control strategy reduces the total harmonic distortion (THD) from 36.51% to 1.51%, significantly enhancing compliance with international grid standards. Additionally, a novel grounding technique is implemented to mitigate common mode leakage currents, a typical issue in transformerless systems, without the need for galvanic isolation. Comprehensive MATLAB/Simulink simulations validate the inverter's performance, demonstrating superior dynamic behavior, harmonic suppression, and overall reliability. The proposed architecture offers a compact, cost effective, and high performance solution for next generation grid integrated solar PV systems.

In this work we report on the characteristics of a (Ni/Au)/AlGaN/GaN/SiC Schottky barrier diode (SBD). A variety of electrical techniques, such as gate current-voltage (I-V), capacitance-voltage (C-V), and deep level transient spectroscopy (DLTS) measurements have been used to characterize the diode. The behavior study of the series resistance, RS, the ideality factor, n, the effective barrier height, Φb, and the leakage current with the temperature have emphasized an inhomogeneity of the barrier height and a tunneling mechanism assisted by traps in the SBD. Hence, C-V measurements successively sweeping up and down the voltage have demonstrate a hysteresis phenomenon which is more pronounced in the temperature range of 240 to 320 K, with a maximum at ∼300 K. This parasitic effect can be attributed to the presence of traps activated at the same range of temperature in the SBD. Using the DLTS technique, we have detected one hole trap having an activation energy and a capture cross-sec...

B 12 As 2 / SiC  pn heterojunction diodes based on the radiation-hard B12As2 deposited on (0001) n-type 4H–SiC via chemical vapor deposition were demonstrated. The diodes exhibit good rectifying behavior with an ideality factor of 1.8 and a leakage current as low as 9.4×10−6 A/cm2. Capacitance-voltage measurements using a two-frequency technique showed a hole concentration of ∼1.8–2.0×1017 cm−3 in B12As2 with a slight increase near the interface due to the presence of an interfacial layer to accommodate lattice mismatch. Band offsets between the B12As2 and SiC were estimated to be ∼1.06 eV and 1.12 eV for conduction band and valance band, respectively.

This article features a comprehensive methodology for analyzing and optimizing PWM dead time in automotive traction inverters, applicable to a wide range of power devices, including Si IGBT/Diodes, SiC MOSFETs, and Si/SiC Fusion switches. The proposed methodology enables a systematic comparison of dead time characteristics, focusing on part-to-part tolerances and operating point-dependent influence factors. Three traction inverter systems, each in the 200-300 kW class at 470 V, were built up utilizing Si IGBT/Diode, SiC MOSFET, and Si/SiC Fusion switches from the latest automotive-released technology. The impact of PWM dead times on power losses was experimentally investigated for all three inverter systems, supporting the analytical model. Key findings from the experimental data include: (1) PWM dead times can account for more than 10% of the total inverter power losses in high current density SiC MOSFET inverter designs operating at typical automotive switching frequencies of 10 kHz; (2) Optimizing PWM dead times in Si/SiC Fusion power modules leads to up to a 5% reduction in total inverter power losses and improved current sharing, resulting in lower thermal stress-This was evaluated using thermal infrared measurements from the Si/SiC Fusion inverter prototype; 3) Optimized PWM dead times can reduce total harmonic distortion at light load conditions by up to 2%-3% for IGBT/Diode and up to 4%-5% for SiC MOSFET and Si/SiC Fusion inverter systems; (4) A sensitivity study in addition revealed that Si/SiC Fusion switches exhibit the most stable dead time settings under parameter variations. The benefit of optimized versus conventional 2 μs PWM dead times would result in an annual energy saving of approximately 6 GWh per 1 million vehicles. This highlights the significance of optimized PWM dead times in automotive traction inverters operating at typical switching frequencies of 10 kHz. The goal of this investigation is to support the development of reliable and efficient automotive traction inverters, with the methods presented being applicable to other applications as well. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

The post-breakdown leakage current in MOS p-silicon devices cannot be modeled with a single-diode and a series resistance for the complete range because of the complex shape of its logarithmic plot. For low voltage, the current can be described by a single-diode model and a series resistance, and for high voltage a different singlediode model and a resistance can be used. These two regional single-diode models are combined in a double diode model with two resistances.