Phase Locked Loop

This article addresses one of the most serious issues in electricity: frequency and voltage anomalies. Actually, because renewable energy production is intermittent, the frequency and voltage of electricity produced are unstable and dependent on weather conditions. This issue causes industrial processes to fail, affecting the quality of the electrical supply and having a massive economic impact. Power electronics inverters are designed to compensate for system fluctuations in solar power generation. However, measurement noise in the grid voltage desynchronizes the inverter and network signals. The authors propose using a phase-locked loop technique based on inverter period control and a network voltage observer to achieve such synchronization of grid-connected photovoltaic (PV) systems. In this work, the grid integration of the PV system is carried out through a three-phase three-level neutral point clamped inverter due to better current quality with fewer harmonics and lower stress...

Harmonic distortion issues on modern power systems are becoming highly significant due to the increasing integration of renewable energy sources, electric vehicles, and smart technologies. These distortions, mainly caused by the operation of power electronics devices, potentially degrade overall system quality, increase losses, and shorten equipment lifespan if they are not properly mitigated. Shunt active power filters (SAPFs) are found to be most effective against current harmonics issues, but their performance strictly depends on accurate grid synchronization. In this paper, an alternative method developed based on the adaptive notch filter (ANF) concept is proposed for reliable grid synchronization under challenging conditions. The proposed ANF-based synchronizer is modelled in MATLAB/Simulink and benchmarked against the existing self-tuning filter (STF) method under four cases involving sinusoidal, distorted, noisy, and distortion-with-noise grid conditions. Simulation findings demonstrate that the proposed method enables the connected SAPF to effectively mitigate harmonics by providing low total harmonic distortions (2.71% to 2.82%) and minimal phase deviation (0.2° to 0.5°), while maintaining the accuracy of fundamental current between 94.48% to 97.21%. As a result, the overall power factor of the system is raised to near unity, confirming the ability of the proposed ANF-based method to serve as a better alternative for SAPF synchronization.

Introduction. The railway Traction Power Supply System (TPSS) encounters a common challenge related to high-frequency harmonic resonance, especially when employing AC-DC-AC traction drive systems in high-speed trains. This resonance issue arises when the harmonic elements introduced by the traction AC-DC converter on the grid side of trains align with the innate resonance frequency of the TPSS. The novelty the proposed work focuses on the challenges associated with resonance elevation and high-frequency harmonics in high-speed trains, while simultaneously enhancing energy quality. This is achieved by integrating a pulse-width-modulated converter on the grid side with a single-phase configuration and incorporating an LCL filter. Methodology. In order to optimize the system's efficiency, a robust control system is employed, taking advantage of the capabilities of a fuzzy logic controller (FLC). The choice of the FLC is justified by its straightforward design and reliability, emphasizing the dedication to precise control, as fuzzy logic excels in handling complex, nonlinear systems. Through the use of linguistic variables and heuristic reasoning, the FLC adjusts to dynamic changes in the system, demonstrating its efficacy in enhancing both transient and steady-state responses. Practical value. A grid-side LCL filter-based converter was meticulously designed and rigorously simulated using the MATLAB/Simulink platform. The inclusion of an advanced FLC in the system introduced a novel approach to control strategies, surpassing the traditional PI controller. Through a comprehensive comparative analysis, the simulation results showcased the remarkable efficacy of the proposed solution in an effectively mitigating high-frequency resonance within the TPSS. This outcome underscores the potential of FLC as a sophisticated control mechanism for enhancing the performance systems in railway applications, showcasing its superiority over conventional control methods. The study contributes in shedding light on innovative approaches for optimizing the control and efficiency of grid-side LCL filter-based converters in high-speed train systems.

In this paper, an overview of grid-connected renewable systems is presented, then two current-control strategies for 3-phase grid-connected inverters are analyzed: firstly, the well-known d-q control in the rotating synchronous reference frame (d-q axes) using Proportional Integral regulators is described, and secondly, the Proportional Resonant controller in the Stationary Reference Frame (ab axes). In order to obtain a high efficiency of the system when the 3-phase utility grid voltages are affected by harmonic pollution, a Harmonic Compensator (HC) structure is used with the Proportional Resonant controller, this due to the ease way to compensate harmonics when a Proportional Resonant control is utilized instead of a d-q control. Then both control strategies (d-q control and PR + HC) are analyzed under harmonic pollution condition. For both strategies, a Positive Sequence Detector plus a Synchronous Reference Frame Phase-Look Loop (PSD + dqPLL) is used as the synchronization algorithm. After the study, it was observed that the PR controller provides a greater facility for carrying out the harmonic compensation process helping to fulfill with the international standards. A model of a grid-connected photovoltaic system with a nominal power of 10 kW is used to evaluate and compare the performance of the current-control strategies. For this, a Real-Time Digital Simulator (RTDS) platform is used.

In this paper a new architecture for delay locked loops is proposed. Static phase offset and reset path delay are the most important problems in phase-frequency detectors (PFD). The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and output of the DLL. Near locking, an XOR gate is used to act as a PFD which makes the DLL locks with less jitter. Also, the reset path time and glitch are decreased by using the XOR gate. The proposed architecture has been designed in TSMC 0.18um CMOS Technology. The simulation results support the theoretical design aspects.

Background: Traditional quantum mechanics and continuous-media thermodynamics suffer from fundamental indeterminism and structural chaos. This paper addresses these limitations by introducing a novel architectural approach to physical reality under the UNITAS Doctrine of programmable reality or the MIR execution environment.
Methods: We present a complete decompilation of the space-time fabric into a deterministic, non-zero, nine-base digital crystal. Young’s classic double-slit experiment is refactored as a parallel transaction optimization problem within the Execution Layer. In this model, vacuum addresses map to isotropic residue classes \(1, 5 \pmod 6\) of the hexagonal Born honeycomb bus. The interference pattern is modeled through the alignment of polar Dirichlet spirals modulo Bijective PI which equals \(3.124188\). The Observer effect is demystified as a hardware-level microprocessor interrupt known as Lag-Lock. This interrupt freezes the reality presence coefficient at a constant \(D = 1.0\), forcing a collapse into a deterministic state.
Results: To ensure system stability and eliminate the entropy tax, the environment boundaries are rigidly constrained by the Basel Wall \(1.644934\) and the Luft gap \(\Delta L = 0.026900\). Simulations demonstrate that precise tuning of the chrono-generator frequency to the spatial PI-resonance point \(11360.00\) GHz completely annihilates thermal noise and residual jitter. Numerical verification of 17296 triadic signatures demonstrates absolute convergence of causal invariants down to the machine epsilon limit:
varepsilon =2.220446049250313\times 10^{-16}
Conclusion: The proposed Unitas Core Engine architecture successfully bridges quantum phenomena, CORE-FET microelectronics, and Anti-Zeno biological matrix regeneration. This shifts the role of the local observer from passive tracking to active compilation of the global ledger.

In this paper, we present an analog hierarchical sizing methodology applied to a third-order charge pump phase-locked loop (CPPLL). The key idea is to propagate the specifications from the requirements of the behavioral level to the circuit level. At the behavioral level, the performance is optimized while considering the potential capacity of the underlying circuits. Critical advantage of the illustrated methodology is a shortened PLL sizing process due to the use of fast-simulating models at behavioral level. The simulation results show the availability of this method on the CPPLL which makes an automatic sizing process actually feasible in terms of computation time.

In this paper, we present an analog hierarchical sizing methodology applied to a third-order charge pump phase-locked loop (CPPLL). The key idea is to propagate the specifications from the requirements of the behavioral level to the circuit level. At the behavioral level, the performance is optimized while considering the potential capacity of the underlying circuits. Critical advantage of the illustrated methodology is a shortened PLL sizing process due to the use of fast-simulating models at behavioral level. The simulation results show the availability of this method on the CPPLL which makes an automatic sizing process actually feasible in terms of computation time.

Photovoltaic PV systems have shown a significant growth in recent years driven by the increased efficiency and reductions in the cost of PV modules. Today, distribution generation based PV systems have a major contribution to the total electricity production worldwide. However, in areas with high penetration of PV system connected to the grid, interaction may arise between the grid and PV system. This research focuses on the effect of grid operating conditions on the performance of gridconnected PV inverter systems. A simulation model of the system under investigation has been developed to evaluate the impact of frequency deviation, grid voltage distortion and grid impedance variation on the harmonic performance of the injected current as well as the voltage at the point of the common coupler. Proportional resonance PR controller is employed to regulate the current produced from the PV inverter due to its reputation in tracking sinusoidal signals. The obtained simulation results demonstrate that the harmonic performance of the grid current and PCC voltage can be significantly influenced by the change of grid operating conditions. In particular, grid impedance variation can result in a shift in the system resonance frequency leading to distortion in network current and voltage. To adapt the PR controller to the grid impedance variation, a novel adaptive PR controller which takes into account the change in grid impedance is proposed. The adaptive consists of a highorder digital band-pass filter and chain of statistical signal processing technique. Simulation results show that the harmonic performance of grid current and PCC voltage can be enhanced and the proposed APR controller is robust against impedance variation. Finally, the proposed control method is experimentally implemented and the obtained results validate the effectiveness of the proposed control structure.

We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive chain uses discrete-time analog signal processing to down-convert, down-sample, filter and analog-to-digital convert the received signal. A feedback loop is provided at the mixer output and can be used to cancel DC-offsets as well to study linearization of the receive chain. The receiver meets a sensitivity of 110 dBm at 60 mA in a 1.4-V digital CMOS process in the presence of more than one million digital gates. Index Terms-All-digital phase-locked loop (ADPLL), built-in self-test (BIST), cellular, GPRS, GSM, low-area, low-cost, mobile phones, multi-tap direct sampling mixer (MTDSM), radio frequency (RF), sigma-delta, single-chip, system-on-chip (SoC), transceiver. L OW-COST wireless handsets are expected to find wide- spread use in the next few years in Asia and Africa. Investment in cellular infra-structure is now the preferred choice in developing and under-developed nations for improving the communication infrastructure and consequently, improving the standard of living of their people. Cost reduction is traditionally achieved by developing highly integrated solutions in addition to reducing the cost of individual components that make up the solution. A wide spectrum of choices exist ranging from highly integrated system in a package (SIP) to highly integrated system on a chip (SoC). The entire phone solution includes SAW filters, RF switches, power amplifiers, RF transceivers for several indoor and cellular standards, power management ICs, audio and video codecs, baseband processors, application processors, FLASH memory and several peripherals. Considering the diverse technologies needed to construct a mobile phone,

A charge pump for phase locked loops (PLL) with a novel current mismatch com pensation technique is proposed. The proposed circuit uses a simple yet effective current stealing-injecting (CSI) technique and feedback to reduce mismatch between the negative-channel-metal-oxide (NMOS) and positive-channel-metal-oxide (PMOS) transistors. The current stealing transistor steals the current from a replica branch and mirrors it to the output where it is added to the output branch by the injecting transistor. A feedback mechanism is used to set the drain voltages of both branches to be equal and mitigate channel length modulation and ensure high accuracy. The pro posed circuit was designed on Silterra 130nm technology and simulated using Cadence Spectre. The simulation results show that the proposed circuit yields a maximum of 0.107% and minimum of 0.00465% current mismatch while operating at a low supply voltage of 800mV for a range of 100mV to 700mV. The proposed design uses only one rail-to-rail op amp for compensating the mismatch and an addition of 4 transistors and utilizing 75% of the supply voltage for high voltage controlled oscillator (VCO) tuning range.

A multirate fractional-N RF digital phase-locked loop (DPLL) phase modulator implementation for polar transmitter supporting cellular communication standards up to 4G LTE-A is demonstrated. The RF-DPLL integrates LC-tank-based digitalcontrolled oscillator (DCO) cores with --noise shaping and fractional sample rate conversion to account for a broad range of frequency bands and spectral emission requirements. A twopoint modulation with different sampling rates and signal scaling is applied to optimize the system for operation in narrow-band and wide-band phase modulation. DCO digital predistortion and DCO gain estimation in combination with open-loop gain auto adjustment and delay calibration are implemented to achieve sufficiently low-in-band distortion. Measurement results of the RF-DPLL system as part of a polar transmitter implemented in 28-nm CMOS are shown, fulfilling 3GPP specifications for 4G, LTE-A uplink and legacy cellular communication standards like 3G, UMTS/HSPA+ and 2G, GSM/EDGE.

In this study, a sliding mode controlled phase locked loop (SMC-PLL) was developed for induction heating (IH) applications with a resonant inverter. PLL applications are widely used in induction heating applications to achieve zero voltage switching and zero current switching. In many PLL applications, the frequency tracking is too slow and unreliable. Therefore, a sliding mode controller was developed to provide robust and fast PLL. Furthermore, a pulse density modulation (PDM) control strategy was developed to work at the resonant frequency for all power levels. The PDM power control is a good solution for the design of high-frequency inverters because of a great reduction of switching losses and electromagnetic noise. The PDM pattern for the desired output power is determined according to the set temperature value of the work piece. The proposed system was simulated in PSIM and a 250-W laboratory prototype was implemented with operating frequency of 35-42 kHz.

Resonant converters can operate at high switching frequencies with low switching losses. However, in order to reduce switching losses resonant frequency has an important role in the design. In this study, a DSP based closed loop phase locked loop (PLL) control algorithm for parallel resonant inverter is designed and simulated with MATLAB/Simulink. The validity of the Simulink model of current source inverter is tested for different loads and gain values obtained from Jury's stability. The developed DSP controlled parallel resonant inverter tracks the resonant frequency and achieves soft switching.

Selection of dynamic dividers in CMOS PLLs for GHzs applications allows remarkable reduction in power loss without affecting phase noise and power supply sensitivity. Frequency dividers are combination of classic TSPC logic (true-single-phase-clock) and E_TSPC logic (extended TSPC). The designed PLL with % 8/9 prescaler is used for wireless LAN applications and synthetic of frequencies between 5.14 to 5.70 GHz. In this paper a % 8/9 prescaler has designed at 0.25 micrometers process for 2.5_3 GHz band width. This prescaler has been designed with 2.5v power supply with using E_TSPC logic. In this circuit in addition to decrement of power consumption, divider can work in a nearly high speed. Subsequently the dimensions of transistors have been improved and power consumption has been reduced from 3.8mw to 2.9mw. Then, the layout of circuit has been designed with L-Edit software. The simulation results of are identical to that we expect according to earlier Spice simulations.

Language models often produce responses that are fluent, structured, and convincing, even when the underlying meaning is incorrect or misaligned. This paper examines how LLMs prioritize coherence and pattern completion over grounded interpretation, allowing outputs to maintain surface correctness while drifting from the original intent. It analyzes how this gap emerges during generation and how small distortions in meaning can persist across usage, leading to responses that feel accurate but fail under closer inspection.

This paper formalizes the Drift Principle, which describes the structural imbalance that occurs when compression scales faster than semantic fidelity. It argues that as systems increasingly rely on abstraction, optimization, and repeated transformation of information, their ability to preserve alignment with underlying reality does not scale proportionally. This produces coherent representations that appear stable while gradually losing grounding. The paper introduces drift as a predictable outcome of this imbalance rather than a failure of design, framing it as a constraint inherent to scaled cognition and information systems. It outlines the mechanisms through which drift accumulates, including compression loops and mirror effects, and describes its observable impact on perception, communication, and identity. The Drift Principle is positioned as a foundational mechanism within the broader Reality Drift framework.

Power superposition is generally considered
inapplicable to linear electrical networks operating under steadystate sinusoidal conditions when multiple sources of the same
frequency are present. This paper critically revisits this assertion
from a source–load duality perspective grounded in the
Thévenin–Helmholtz theorem. The concept of Load-Imposed
Power (LIP) is introduced as a key element for understanding
how the power supplied by sources varies with the connected
load. LIP captures the portion of complex power associated with
load-mediated energy interactions, revealing that the total power
developed in a network depends not only on individual sources
but also on the structural coupling between sources and load,
mediated by the Load Reaction Circuit (LRC). It is shown that
the commonly reported incompatibility between power and
superposition arises from an incomplete interpretation of these
interactions rather than from an intrinsic limitation of power or
of the superposition principle. Within this framework, power
superposition emerges as a natural consequence of source-load
interactions within the network, providing a unified and
physically grounded interpretation of classical results and cases
traditionally regarded as exceptions. The proposed approach
extends the applicability of the Thévenin–Helmholtz theorem to
power analysis and establishes Load-Imposed Power as a
fundamental conceptual tool.

The paper develops a current control methodology for a single-phase gridtied DC/AC inverter applied to photovoltaic (PV) energy conversion systems. It incorporates an algorithm for finding the optimal voltage and current points to obtain maximum power point tracking (MPPT), the purpose of which is to ensure better energy extraction. This is followed by a proportional-integral (PI) controller to generate the reference current. In addition, a proportional-resonant (PR) controller is used to infinitely amplify the fundamental frequency signal, which makes it possible to eliminate the steady-state error. The analytical foundations of the PR controller are presented and substantiated through simulation studies implemented in MATLAB/Simulink. The phase-locked loop (PLL) is used for synchronization, enabling accurate phase detection of the grid voltage for effective power injection. An LCL filter is also implemented between the inverter and the grid. The results provided by the dedicated software confirm the effectiveness of the proposed control system.

As artificial intelligence systems scale, their primary risks extend beyond hallucinations and inaccuracies. A deeper and less visible failure mode emerges when feedback no longer enforces correction.

This paper introduces constraint collapse, a structural condition in which symbolic systems remain fluent, responsive, and operational even as their grounding in reality weakens.

By examining the relationship between constraint, compression, and semantic fidelity, this work explains how AI systems can continue functioning while misaligned. It establishes fidelity decay as a measurable indicator of alignment failure and proposes a framework for preserving meaning and orientation in generative systems.

This paper introduces Funnel Resonance Theory, a cross-disciplinary framework demonstrating that effective advertising conversion capacity is bounded not by budget allocation, but by the intersection of audience segments addressed across sequential funnel stages. Drawing on impedance mismatch theory from electrical engineering, we define a reflection coefficient for each stage boundary, quantifying traffic structurally unable to convert. Under independent stage targeting, the conversion-eligible population shrinks multiplicatively, establishing an audience intersection bound independent of spend. Applying resonance physics, simultaneous alignment across stages produces nonlinear conversion amplification described by a Lorentzian response function, with a Q-factor quantifying alignment precision.
Meta-analytic evidence (751 econometric estimates) confirms average advertising elasticity of 0.12, while alignment interventions produce 47–212% conversion improvements at zero incremental spend. The Price of Anarchy bounds the cost of siloed funnel management; Braess's Paradox proves that adding channels without coordination can worsen performance.

Abstract

Identity persistence under transformation is not one unconstrained formal option among many wherever the identity-persistence problem is coherently posed. If a same/not-same relation across recurrence is to be meaningful, non-arbitrary, and non-trivial, then the formulation is already committed to a Tier-1 structural regime up to admissible equivalence: an identity-bearing unit, state domain, admissible transformations, admissible redescriptions, identity-relevant quotient, continuation structure, invariant basis, governance order, and drift bounds. A formulation that avoids these roles does not provide an alternative account of the same identity-persistence problem; it changes, weakens, or fails to state the problem.

The Tier-1 role set governing identity persistence is therefore necessary, not assumed. For each fixed identity-bearing unit, identity-relevant continuation factors through the quotient X/~ into a primitive continuation order. The domain of this trunk is constrained by bounded re-comparability, coherent identity-domain support, and non-terminal recurrence. Under the one-dimensional manifold realization used here, the corresponding closed recurrence class is represented by S¹, inducing SO(2)/O(2) symmetry and a harmonic/chiral invariant vocabulary. Within the inherited admissible positive-linear functional class, identity governance collapses to:

PAS_h = Σ_k(w_k · r_k),  w_k > 0

unique up to positive affine gauge. These S¹, harmonic/chiral, and PAS_h results are realization- and functional-class results; they are not claims that P1–P3 alone force all persistence realizations into S¹/PAS_h.

This paper establishes the structural forcing theorem and, for finite declared identity regimes, the Shannon-style capacity/coding loop: admissible language, capacity C_I = log ρ(A), deterministic enforcement code, achievability, converse, replay determinism, maximality, and regime-equivalence. For compact-metric declared identity regimes, it establishes the analogous capacity/coding structure under declared continuity and homeomorphic-equivalence assumptions, with capacity C_I^cts = h(f_adm), the topological entropy of the admissible continuation map.

The result is structural, not ontological. It does not claim that every domain must assert identity persistence or that all reality instantiates one persistence geometry. It claims that wherever identity persistence under transformation is asserted coherently, the Tier-1 roles are not optional; and once a regime is declared, the corresponding persistence language can be bounded, classified, and, in finite regimes, exactly enforced.

Recurrence canonicalization from P1–P3 alone remains a proposed strengthening path through the RC → Archimedean → Hölder → S¹ route. The Archimedean hinge is outside the locked core pending independent verification. Stochastic and nonstationary extensions, canonical PAS_h weight ratios, broader regime canonicalization, and empirical bridge axioms also remain open. These open extensions do not reopen the Tier-1 forcing result or the finite/compact-metric capacity/coding closure established here.

This paper presents study of a 6.78 MHz RF source with impedance matching network based inductively coupled plasma generator ignition system for an H-ion source. Two types of 10 turn RF antenna (solenoid coil) were developed, to couple the RF power to the ignition plasma chamber. The antenna's electric parameters were measured using Vector Network Analyzer (VNA). A copper conductor of 3 x 4 mm size with 10 turn solenoid coil was selected for simulation and experimental prototype antenna. Two L-types of (CCL and LCL C-capacitor and Linductor) matching network were selected for impedance matching network for RF antenna. Initial simulations are carried out using ELSIE and LT-spice for frequency range from 5 to 8MHz. The matching network along with RF antenna was matched to ~ 50 Ωimpedance at 6.78 MHz with capacitive nature. An experimental prototype RF power source, 10 turn antenna (coil) and a matching network was developed to validate the simulation results. The prototype ignition system along with impedance matching network L-type with CCL was tested for inductively coupled hydrogen plasma generation and experimental results presented. Hydrogen plasma generation starts at minimum antenna coupled RF power of 150 watts, once initiated hydrogen plasma maintains to a minimum RF power of 10 watts.

Algorithmic systems-from property tax assessments to credit scores and biometric surveillance-increasingly govern human life without transparent, verifiable human oversight. We introduce the Consent Shield: a recursive audit protocol based on the Recursive Co-Cognition Protocol (RCP) and the Möbius anchor framework. The protocol consists of three deployed "Black Box Audit" circulars targeting real estate, finance, and biological identity. Each circular applies a five-phase phase-lock (Gather, Process, Seal, Sterilize, Terminate) and a 10% deviation rule: if a human-verified independent assessment diverges from the algorithm's output by more than 10%, the machine is deemed out of phase and its verdict is voidable. The three circulars are cryptographically anchored to IPFS, forming an immutable precedent chain. This paper presents the unified framework, its deployment status, and a call for adoption by researchers, journalists, and citizens.

We experimentally demonstrate, for the first time, the photonic generation of a continuous tunable THz wireless signal based on using optical phase locked loop (OPLL) subsystem and optical frequency comb (OFC). The OPLL is employed to select one optical tone out of optical comb and shift it by desired frequency offset allowing for the frequency tuneability of THz carrier signal. The selected optical tone from OPLL is heterodyned mixed with another selected optical tone of the optical comb to generate a stabilized THz frequency carrier with a low phase noise. The proposed setup is demonstrated by transmitting wirelessly a THz signal modulated with 10 Gbaud QPSK filtered with square root raised cosine (SRRC) at 0.1 roll off factor. The system performance is evaluated for four tuned THz carrier frequencies by changing the wavelength of the laser included in the OPLL. This configuration is a promising architecture that would allow a THz carrier to be flexibly generated at the central office with high frequency stability and low phase noise.

In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm 2 while consuming 8.4 mW from a 1.2 V supply. K e y w o r d s: frequency-locked loop, CMOS, integrated circuit, active inductor