Key research themes
1. How can state-space representations optimize the construction and decoding of product convolutional codes?
This research area investigates the algebraic and system-theoretical frameworks for product convolutional codes using minimal state-space representations. The motivation is to achieve systematic constructions of product codes that are minimal, reachable, and observable, facilitating efficient encoding and decoding operations. The state-space approach provides a foundation to extend known results from block product codes to convolutional codes, potentially enhancing error correction and burst error handling.
2. What design principles enable high-performance serial and parallel concatenated convolutional codes with optimized error correction?
This theme covers the analysis, design, and performance optimization of serially and parallelly concatenated convolutional codes (SCCCs and PCCCs), including their rate-compatible and turbo decoding variants. The focus lies on the choice of constituent convolutional codes, interleaver design, puncturing patterns (including inner code systematic and parity bits), and their impact on free distance, error floors, and decoding thresholds. Understanding the interplay between these parameters is crucial for approaching Shannon capacity limits and tailoring codes for various communication channel conditions.
3. How can low-density parity-check codes and convolutional code constraints be integrated and optimized for enhanced decoding thresholds and complexity tradeoffs?
This line of research explores generalized LDPC codes with convolutional code component constraints (CC-GLDPC), their irregularity, threshold improvements, encoding complexity, and their comparison to classical LDPC codes. Emphasis is placed on designing codes for efficient belief propagation decoding with strong component codes represented as trellis constraints, enabling spatial coupling and tailored performance-to-complexity ratios in modern communication systems such as 5G. The research also includes FPGA performance comparisons of turbo and LDPC codes under different hardware constraints.