Turbo Decoder

This paper begins with an investigation of the optimization of binary turbo code through good interleaver design. For this purpose, different types of interleaver have designed here and have evaluated their performance. Basically the performances of the turbo code using block interleaver, helical interleaver, random interleaver and odd-even interleaver have evaluated. From this investigation it has been seen that for small code length the performance of the block interleaver is superior in non-puncturing case and the performance of the odd-even interleaver is superior in puncturing case, but for large code length the performance of the random interleaver is better in both of puncturing and non-puncturing condition. In this paper, it has investigated that the performance of the odd-even interleaver (block interleaver with odd number of rows and columns) significantly increased in puncturing conditions. Index terms— Turbo encoder; Turbo decoder; Interleaver; code rate; Puncturing; Non...

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-La multiplication des standards de communication sans fils introduit le besoin de récepteurs multi-standards reconfigurables. Afin d'adresser cette problématique et faire face à la demande croissante en débit des applications sur les terminaux mobiles, des architectures multi-ASIP ont été développées ces dernières années. De plus, l'évolution dynamique des paramètres de communication ainsi que la réduction du délai entre deux trames de données imposent la mise en oeuvre de mécanismes de reconfiguration optimisés. Dans ce contexte, nous proposons d'optimiser un turbo-décodeur multi-ASIP multi-mode et multi-standard dans un but d'optimisation globale des mécanismes de reconfiguration. Les résultats présentés montrent que les optimisations apportées à l'ASIP engendrent un faible surcoût en surface (0.004 mm 2 pour une technologie CMOS 65 nm) et permettent de réduire significativement la quantité de données nécessaire à la reconfiguration de la plateforme. En effet, pour une plateforme implémentant 8 ASIP, la quantité de données devant être diffusée aux ASIP lors d'un changement de configuration est divisée par 10 grâce aux optimisations proposées couplées à une infrastructure de configuration efficace.

HAL is a multidisciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

Dynamic reconfiguration of multiprocessor platforms is an important challenge for System-on-Chip designers. Addressing this issue is mandatory in order to manage the increasing number of applications and execution conditions that multiprocessor platforms have to face. In this paper, a novel configuration infrastructure for the UDec multi-ASIP turbo decoder architecture is presented. Our approach leads to split the interconnection architecture in two subsets, one dedicated for data and another dedicated for configuration. Indeed both types of communication do not have the same requirements. Our novel configuration infrastructure, which proposes an area efficient and low latency solution, has been validated through a two-step approach. First a SystemC/VHDL mixed simulation model has been developed to perform an early performance evaluation, second a hardware FPGA prototype has been built. Results show that up to 64 processing elements can be dynamically configured in 5.352 µs.

The multiplication of wireless standards is introducing the need of flexible and reconfigurable multistandard baseband receivers. At the physical layer, multiprocessor turbo decoders have been recently developed in order to provide an answer to the increasing throughput requirement of emerging standards. However these solutions do not sufficiently address reconfiguration performance issues which can be a limiting factor in the future. This work focuses on the design of a reconfigurable multiprocessor architecture for turbo decoding achieving very fast reconfiguration without compromising decoding performances. Dynamic reconfiguration can be performed within a single frame decoding duration opening new perspective for reconfigurable multistandard baseband receivers. For that purpose, optimizations at the processing element level and a novel bus-based configuration infrastructure are proposed. Results show that up to 64 processings elements can be dynamically configured in 5.352 μs. This low configuration latency corresponds to a single frame decoding duration when performing 6 decoding iterations for a throughput up to 666 Mbps.

In this paper, we demonstrate how the development of parallel hardware architectures for turbo decoding can be continued to achieve a throughput of more than 100 Gb/s. A new, fully pipelined architecture shows better error correcting performance for high code rates than the fully parallel approaches known from the literature. This is demonstrated by comparing both architectures for a frame size K = 128 LTE turbo code and a frame size K = 128 turbo code with parity puncture constrained interleaving. To the best of our knowledge, an investigation of the error correcting performance at high code rates of fully parallel decoders is missing from the literature. Moreover, place & route results for a case study implementation of the new architecture on 28 nm technology show a throughput of 102.4 Gb/s and an area efficiency of 4.34 Gb/s making it superior to reported implementations of other parallel decoder hardware architectures.

In the wireless transmission of multimedia information, the achievable transmission throughput and latency may be limited by the processing throughput and latency associated with source and channel coding. Ultra-high throughput and ultra-low latency processing of source and channel coding are required by the emerging new video transmission applications, such as the first-person remote control of unmanned vehicles. The recently proposed unary error correction (UEC) code facilitates the joint source and channel coding (JSCC) of video information at transmission throughputs that approach the capacity of the wireless channel. In this paper, we propose the first hardware implementation of the UEC code that achieves the high processing throughputs as well as ultra-low processing latencies required. This is achieved by extending the application of the recently proposed fully parallel turbo decoder (FPTD) from pure stand-alone channel coding to JSCC. This paper also proposes several novel improvements to the FPTD, in order to increase its hardware efficiency and supported frame length. We demonstrate the application of these improvements to both the long term evolution turbo code and the UEC code. We synthesize the proposed fully parallel design on a mid-range field programmable gate array, achieving a throughput of 450 Mbps, as well as a factor of 2.4 hardware efficiency improvement over previous implementations of the FPTD. INDEX TERMS Turbo codes, combined source-channel coding, channel coding, decoding, field programmable gate arrays, throughput, wireless communication.

This paper presents a low complexity interleaver design that facilitates high throughput Turbo decoding required for next generation wireless systems. When a parallel decoder structure is considered, interleaver design is the most important issue. In such parallel decoder, the contention problem occurs when more than one extrinsic value references to the same memory block for read or write purpose. This paper focuses on the alternate method for QPP interleaver which shows improved BER performance for large frame size. Bit reversed indexing is used to generate interleaved addresses. A counter is used to generate sequential address as well as interleaved address. The number of address lines of memory which stores data , depends upon frame size of data. In this paper, a comparison is made between best proved interleaver and proposed interleaver on the basis of BER performance for different number of iterations, different frame size and different decoding algorithms. General Terms Inter...

This paper presents a low complexity interleaver design that facilitates high throughput Turbo decoding required for next generation wireless systems. When a parallel decoder structure is considered, interleaver design is the most important issue. In such parallel decoder, the contention problem occurs when more than one extrinsic value references to the same memory block for read or write purpose. This paper focuses on the alternate method for QPP interleaver which shows improved BER performance for large frame size. Bit reversed indexing is used to generate interleaved addresses. A counter is used to generate sequential address as well as interleaved address. The number of address lines of memory which stores data , depends upon frame size of data. In this paper, a comparison is made between best proved interleaver and proposed interleaver on the basis of BER performance for different number of iterations, different frame size and different decoding algorithms. General Terms Inter...

The wireless communication has two significant blocks across transmitter and receivers are encoders and decoders. This work focuses on the design and implementation of turbo decoder in hardware description language (HDL) in verilog version. The turbo codes are very efficient in channel coding and are reaching the Shannon limit. The proposed design for turbo decoder uses the max-log algorithms instead of using max-log-MAP algorithm which computes on approximation. The design reduces the fixed number of iteration and performs the early termination which greatly reduces the power consumption utilized even after the decoding is completed. For early termination, the Sign Difference Ratio (SDR) is considered and across the hardware coding clock gating is introduced to avoid the unnecessary clock supply to achieve the power efficiency. The entire design has been implemented on vertex 4 and vertex 5 of Xilinx FPGAs. The power analysis is made and compared with recent existing technologies.

Turbo codes facilitate near-capacity transmission throughputs by achieving a reliable iterative forward error correction. However, owing to the serial data dependence imposed by the logarithmic Bahl-Cocke-Jelinek-Raviv algorithm, the limited processing throughputs of the conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time communication schemes. Motivated by this, we recently proposed a floating-point fully parallel turbo decoder (FPTD) algorithm, which eliminates the serial data dependence, allowing parallel processing and hence significantly reducing the number of clock cycles required. In this paper, we conceive a technique for reducing the critical datapath of the FPTD, and we propose a novel fixed-point version as well as its very large scale integration (VLSI) implementation. We also propose a novel technique, which allows the FPTD to also decode shorter frames employing compatible interleaver patterns. We strike beneficial tradeoffs amongst the latency, core area, and energy consumption by investigating the minimum bit widths and techniques for message log-likelihood ratio scaling and state metric normalization. Accordingly, the design flow and design tradeoffs considered in this paper are also applicable to other fixed-point implementations of error correction decoders. We demonstrate that upon using Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm low-power technology for decoding the longest long-term evolution frames (6144 b) received over an additive white Gaussian noise channel having E b /N 0 = 1 dB, the proposed fixed-point FPTD VLSI achieves a processing throughput of 21.9 Gb/s and a processing latency of 0.28 µs. These results are 17.1 times superior to those of the state-of-the-art benchmarker. Furthermore, the proposed fixed-point FPTD VLSI achieves an energy consumption of 2.69 µJ/frame and a normalized core area of 5 mm 2 /Gb/s, which are 34% and 23% lower than those of the benchmarker, respectively.

Due to their computational complexity, iterative decoder components such as source and channel decoders are usually implemented using specialized dedicated hardware. This leads to the scenario where each different iterative decoder component of the receiver requires its own hardware. Owing to their relatively high complexity, many capacity-approaching techniques proposed in the literature have not yet been invoked in Wireless Sensor Network (WSN) applications, despite their potential benefits of facilitating a reduced transmission power or extended communication range. Against this background, we propose an energy-efficient architecture comprised of multiple Computation Units (CUs), which is sufficiently flexible for accommodating different iterative decoder components using the same hardware. In this work, the flexible architecture is applied to Joint Source and Channel Coding (JSCC), comprising the Unary Error Correction (UEC) code, a turbo code, and an iterative demodulator. We conceive a flexible technique for controlling the hardware, which supports a high hardwareexploitation ratio for the CUs, reaching a utilization of 88%, compared to 68% achieved in similar solutions reported in the open literature.

The increasing requirements of high data rates and quality of service (QoS) in fourth-generation (4G) wireless communication require the implementation of practical capacity approaching codes. In this chapter, the application of Turbo coding schemes that have recently been adopted in the IEEE 802.16e WiMax standard and 3GPP Long Term Evolution (LTE) standard are reviewed. In order to process several 4G wireless standards with a common hardware module, a reconfigurable and scalable Turbo decoder architecture is presented. A parallel Turbo decoding scheme with scalable parallelism tailored to the target throughput is applied to support high data rates in 4G applications. High-level decoding parallelism is achieved by employing contention-free interleavers. A multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. A new on-line address generation technique is introduced to support multiple Turbo interleaving patterns, which avoids the interleaver address memory that is typically necessary in the traditional designs. Design trade-offs in terms of area and power efficiency are analyzed for different parallelism and clock frequency goals.

Iterative decoder implementation for turbo codes is an
demanding assignment. Several algorithms have been projected
to facilitate the implementation of iterative decoder for turbo
codes. This paper examines the implementation of an iterative
decoder for turbo codes using the MAX−LOG−MAP algorithm
and Fully parallel turbo decoding algorithm (FPTD). Despite the
fact that the MAX-LOG-MAP practices turbo encoded bits in a
serial forward-backward style, the proposed algorithm functions
in a fully-parallel behaviour, processing all bits in both
components of the turbo code at the same time. The FPTD
algorithm is attuned with all turbo codes, including those of the
LTE and WiMAX standards. BER performance among these
two algorithms is envisaged.

This paper considers detection and error control coding for the two-dimensional magnetic recording (TDMR) channel modeled by the two-dimensional (2D) four-rectangulargrain model proposed by Kavcic, Huang et. al. in 2010. This simple model captures the effects of different 2D grain sizes and shapes, as well as the TDMR grain overwrite effect: grains large enough to be written by successive bits retain the polarity of only the last bit written. We construct a row-by-row BCJR detection algorithm that considers outputs from two rows at a time over two adjacent columns, thereby enabling consideration of more grain and data states than previously proposed algorithms that scan only one row at a time. The proposed algorithm employs soft-decision feedback of grain states from previous rows to aid the estimation of current data bits and grain states. Simulation results using the same average coded bit density and serially concatenated convolutional code (SCCC) as a previous paper by Pan, Ryan, et. al. show gains in user bits/grain of up to 6.7% over the previous work when no iteration is performed between the TDMR BCJR and the SCCC, and gains of up to 13.4% when the detector and the decoder iteratively exchange soft information.