Wide band code division multiple access

The idea of codes (VITERBI) is broadly utilized as a part of the wireless communication system as a result of their less complex nature in the decoding of transmitted message. This paper attempts to develop a performance analysis of the decoder by methods for bit error rate (BER) examination. The Galois fieldbased decoder calculation is only utilized as a part of the communication systems. The decoder calculation-based Viterbi based decoder is carried out using field programmable gate arrays (FPGA) and MATLAB. This paper looks at the execution examination of both the calculations. The reconfigurable processor called Microblaze on the Spartan 3E FPGA is utilized for this purpose. MAT-LAB based code is used to see the BER analysis after the FPGA implementation output.

In this article we present the results of partitioning the OFDM baseband processing of a DRM receiver into smaller independent processes. Furthermore, we give a short introduction into the relevant parts of the DRM standard. Based on the number of ...

Power amplifiers are important elements in communication systems but they are inherently nonlinear. This nonlinearity shows itself in the form of amplitude and phase distortion. One way to get rid of this nonlinear behaviour is to apply backoff which means to operate the amplifier at an output power smaller than its saturated output power. As the backoff is increased, the amplifier will behave more linearly. But this will also reduce the efficiency of the amplifier, which is undesirable. This tradeoff between efficiency and linearity is solved by linearization techniques. By using linearization techniques, the amplifier can be operated near to saturation with good efficiency and linearity. This thesis focuses on polar polynomial predistortion and polar look-up table predistortion, which are popular linearization techniques. A polar polynomial predistorter and a polar look-up table predistorter are implemented and tested with simulations in software. The implementation and testing is done by using IT++ which is a C++ library of mathematical, signal processing, speech processing, and communications classes and functions. The testing of the predistorters is done by using a baseband system model which consists of a 16-QAM modulator, an upsampler, a raised cosine filter, the predistorter and a baseband iii behavioural amplifier model. The performance of the predistorters is evaluated in terms of adjacent channel power ratio, AM/AM & AM/PM responses and BER under AWGN. Simulation results show that the predistorters have good performance. In the simulations, the polar polynomial predistorter achieved 20 dB reduction and the polar look-up table predistorter achieved 25 dB reduction in adjacent channel power ratio. The effect of polynomial order and table size on the performance of the predistorters is investigated. Furthermore, the effect of lowpass filtering on the performance of the predistorters is also investigated by placing a lowpass filter after the predistorters in the system model. It is observed that as the ratio of the bandwidth of the lowpass filter to the bandwidth of the raised cosine filter decreases, the negative effect of the lowpass filter on the performance of the predistorters increases.

— In this article we present the results of partitioning the OFDM baseband processing of a DRM receiver into smaller independent processes. Furthermore, we give a short introduction into the relevant parts of the DRM standard. Based on the number of multiplications and additions we can map individual processes on a heterogeneous multi-tile architecture. This architecture can meet both the computational demands as well as the restricted energy budget.

The design, implementation and characterization of four Low Noise Amplifier architectures in a double poly, four metal layers, 0.35 µm CMOS technology from AMS AG biased at 1.2 V with a power consumption as low as 2.73 mW operating in a frequency band ranging from 1.94 to 2.58 GHz with Noise Figure around 1.3 dB and input intercept point up to 10 dBm are presented. With the performance exhibited by the proposed topologies, it is demonstrated that the use of the Flipped Voltage Follower structure is feasible to realize amplifiers at radio frequencies with low noise figure and good linearity performance preserving its characteristic low power consumption.

The complexity of wireless communication integrated circuits is increasing day by day due to the trend of multifunction and multistandard support. This has not only increased the production cost of these RFICs but the testing cost is also increased significantly, as ...

In this paper, we propose a Frequency Domain Equalizer (FDE) without inserting the Guard Interval (GI) at the transmitter which is applicable to the Wide-band Code Division Multiple Access (WCDMA) and Orthogonal Frequency-Division Multiplexing (OFDM) systems. The proposed FDE adopts the Overlap-Cut (OC) method to avoid the Inter-Block Interference (IBI) and exploits the decision feedback structure to improve the Bit Error Rate (BER) performance. Without inserting the GI, the proposed FDE will be compatible to the frame format of the current High Speed Downlink Packet Access (HSDPA). Besides, it can improve the BER performance and bandwidth utilization when the GI is less than the channel length of the OFDM system.

This paper presents an alg simultaneous linearization and cancellation harmonics of broadband power amplifiers (PA relies on a joint system identification of the nonl effects and group delay of both the main cancellation channels using a recently reported c The filter-less cancellation of the modulated har the method of predistortion and feedforw synchronized PA linearization relies sol predistortion. Experimental verification with yields a reduction of 31 dB of the third harmoni the main channel. Simultaneously the lineariza dB NMSE and 49.5 and 50 dBc ACPR at frequency. Index Terms — Harmonic cancellation, P digital predistortion, cubic spline, concurrent m

One of the main challenges when implementing the future mobile multimedia networks is the cost-effective network evolution from second-to third-generation systems. This evolution path may include the use of different technologies at the same frequency band. The performance of the wide-band code-division multiple-access (WCDMA) downlink is studied in this paper in the case when there are narrow-band (NB) interference sources at the adjacent frequencies. A simple, analytical method to calculate the downlink capacity reduction of the WCDMA macrocell in this case is presented. The analysis takes into account different downlink interference mechanisms: wide-band noise from the transmitter as well as adjacent channel interference, intermodulation, and cross-modulation originating in the mobile receiver. The effect of each interference component to the capacity of the WCDMA macrocellular network has been evaluated with numerical examples. The analysis shows that capacity per cell is sensitive to the cell size, and therefore very careful network planning is needed in order to operate the WCDMA networks efficiently. Results of this paper can be utilized when implementing the WCDMA system to the same band with existing narrow-band systems, for instance, with the PCS 1900 band in United States and GSM 1800 band in Europe.

The Universal Mobile Telecommunications System, wide band code-division multiple access (W-CDMA) radio interface is characterized by great¯exibility and a variety of dierent physical and logical channel types: for example, on the downlink the dedicated channels (DCH) oers circuit switching, the downlink shared channel (DSCH) and forward access channel use packet switching, the former with closed loop power control. Furthermore, several user rates and protections are possible, by choosing suitable parameters, such as spreading factors (SFs), code rates and automatic repeat request (ARQ) schemes. In this paper we present the results, obtained by a detailed simulation, about the eect of several parameters and system alternatives on the capacity of the downlink segment of the W-CDMA interface with packet service. In particular, we investigate the eect of the SF, the code rate, the ARQ and the power control on the DSCH capacity and delay-throughput performance.

The wide band code division multiple access (W-CDMA) receiver combined with adaptive array antenna (AAA) technique is developed and used to measure the bit error rate (BER) performances in indoor line of sight (LOS) and non line of sight (NLOS) environments. Since the BER changes with the orientation of the receiving antenna in indoor environment, the mean BER is proposed

Power amplification in software defined radio needs reconfigurabilty as well as optimum performance in terms of linearity and efficiency to handle different modulation standards (and hence carrier and modulation bandwidth). Since digital predistortion is now widely accepted as highly suitable solutions for linearization in a reconfigurable perspective. Hence, this technique in conjunction with multi-band Doherty power amplifiers finds a potential solution for reconfigurable-multi-band software defined radio transmitter. This paper demonstrates the current state-of art for such transmitters, including a brief discussion about the available design methodology for the dual-band Doherty power amplifier.

This paper presents the 2.4-GHz front-end and the first downconversion section of a fully integrated low-IF receiver. The dual-conversion receiver and rejects the image repeatably by 60 dB using integrated polyphase filters without calibration or tuning. The gain of the RF mixer and IF amplifier is switchable to slide the available dynamic range of the following stages based on the conditions of the input signal. The front-end and downconversion sections drain 35 mA on average from a 3.3-V supply. Minimum cascade noise figure is 7.2 dB, and maximum cascade IIP3 is 3.4 dBm.

Flexible baseband receivers gain the interest of many research efforts to enable the design of future multi-modes multistandards terminals. A main challenge in this domain is to provide this flexibility with minimum overhead in terms of area, speed, and energy. In this regard, heterogeneous multiprocessor platforms are emerging as a promising implementation solution. However, the heterogeneity of such platforms makes it complex to find the required number of processors supporting a specific configuration (i.e. requirements level). This paper investigates, in this context, the significant optimization potential both at design-time and at run-time regarding the selection of the most appropriate hardware configuration of a multiprocessor platform for iterative demapping and channel decoding. A formal representation of the architectural solution space which allows designers to find the minimum hardware configuration is proposed. The proposed approach is illustrated through a flexible multi-ASIP hardware platform for iterative demapping and channel decoding.

A fully integrated SAW-less direct conversion CDMA receiver with single-ended LNA and modified singlebalanced passive mixer is manufactured in a 65 nm digital CMOS process. The measured receiver gain at 1.96 GHz was 37 dB, NF was 3 dB, IIP2 was +62 dBm, and cross-modulation triple beat (TB) was 65 dB.

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In this paper, an ultra low-power CMOS low noise amplifier (LNA) with a new input matching topology will be proposed and analyzed. The LNA design is based on the capacitive feedback in conjunction with a 1t-match network. The proposed LNA saves on chip area by using only one inductor for the input matching. The 1t-match network introduces an additional degree of design freedom and allows the LNA to achieve higher gain. The LNA is designed for 2.4 GHz ISM band in a 130 nm RF-CMOS process. It achieves a gain of 25.2 dB with an Sll of-14 dB while consuming only 0.6 mW. The noise figure (NF) is 3.8 dB. I.

In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by using a novel dynamically reconfigurable accelerator. Conventional microprocessors consume a large amount of power for memory access, in registers, and for the control of the processor itself rather than computation; this decreases the energy efficiency. Dynamically reconfigurable accelerators reduce such redundant power by computing in parallel on reconfigurable switches and processing element arrays (often consisting of an arithmetic logic unit (ALU) and registers). We propose a novel dynamically reconfigurable accelerator "DYNaSTA" composed of a dynamically reconfigurable data path and static ALU arrays. The static ALU arrays process instructions in parallel without registers and improve energy efficiency. The dynamically reconfigurable data path includes registers and many switches dynamically reconfigured to resolve operand dependencies between instructions mapped on the static ALU array, and forwards appropriate operands to the static ALU array. Therefore, the DYNaSTA accelerator has more flexibility while improving the energy efficiency compared with the conventional dynamically reconfigurable accelerators. We simulated the power consumption of the proposed DYNaSTA accelerator and measured the fabricated chip. As a result, the power consumption was reduced by 69% to 86%, and the energy efficiency improved 4.5 to 13 times compared to a general RISC microprocessor.

This paper presents a methodology to compute the distortion output of a class of third-order nonlinear dynamic systems from only standard two-tone test results. Closed-form expressions are presented to compute the distortion output and metrics as adjacent channel power ratio and co-channel power ratio/noise power ratio for an arbitrary multisine with tones. The impact of memory effects in a multisine excitation is also addressed, improving the design of RF components by a careful understanding of memory effects mechanism in real modulated signals. An experimental validation is presented to prove the proposed theory.

This paper describes a power amplifier, employing parallel-connected laterally diffused metal-oxide semiconductor (LDMOS) devices with optimized channel widths and bias offsets to approximate ideal square-law behavior of the overall transconductance in class-AB operation. The proposed method results in a significant linearity improvement over a large dynamic range in comparison to a conventional amplifier in class-A or class-AB operation. Measurements demonstrate an improvement of 20 dB in third-order intermodulation distortion and 10 dB in adjacent channel power ratio for wide-band code-division multiple access at 12-dB output power backoff from the 1-dB gain compression point. Consequently, this amplifier can be operated more toward the compression region with better linearity and drain efficiency compared to a conventional LDMOS power-amplifier design.

In this paper, an ultra low-power CMOS low noise amplifier (LNA) with a new input matching topology will be proposed and analyzed. The LNA design is based on the capacitive feedback in conjunction with a 1t-match network. The proposed LNA saves on chip area by using only one inductor for the input matching. The 1t-match network introduces an additional degree of design freedom and allows the LNA to achieve higher gain. The LNA is designed for 2.4 GHz ISM band in a 130 nm RF-CMOS process. It achieves a gain of 25.2 dB with an Sll of-14 dB while consuming only 0.6 mW. The noise figure (NF) is 3.8 dB. I.

The wide-band code division multiple access (WCDMA) based 3G and beyond cellular mobile wireless networks are expected to provide a diverse range of multimedia services to mobile users with guaranteed quality of service (QoS). Call admission control is a very important measure in WCDMA system to guarantee the quality of the communicating links. Two throughput-based admission control strategy with multi-services, referred to herein as the complete partitioning CAC (CP-CAC) and the queuing priority CAC (QP-CAC), are analyzed and compared. The main contribution of this paper is the development of an analytical model for the QP-CAC algorithm which can be easily extended and used for CP-CAC. We also develop a simulation tool to test and verify our results. Finally, we present numerical examples to demonstrate the performance of the proposed CAC algorithms and we show that analytical and simulation results are in total agreement.

This paper presents a fully integrated CMOS receiver front-end based on a direct conversion architecture for UMTS/802. 11b-g and a low-IF architecture at 100 kHz for DCS1800. The two key building blocks are a multiband low-noise amplifier (LNA) that uses positive feedback to improve its gain and a highly linear mixer. The front-end, integrated in a 0.13 m CMOS process, exhibits a minimum noise figure of 5.2 dB, a programmable gain that can be varied from 13.5 to 28.5 dB, an IIP3 of more than 7.5 dBm and an IIP2 better than 50 dBm. The total current consumption is 20 mA from a 1.2 V supply.

Third generation communication schemes, mainly based on W-CDMA access technique, are replacing the second generation ones both in US and in EU coutries. CDMA makes possible simultaneous communications, spreading the user's information over a large frequency range by the means of orthogonal codes. One of the main problems of this type of communications is the need for exact alignment between the received sequence and the locally despreading code. The Early-Late block is devoted to maintain this alignment using a Delay Locked Loop, providing that the first alignment will be performed by the synchronizer block. In this paper a reconfigurable Early-Late tracking loop architecture, for SDR implementation, is proposed. Very promising results have been obtained from logical synthesis and from physical implementation on a Xilinx XCV100E (48.7 Mhz, 616 FFs, 719 LUTs).

A S CMOS technologies continue to enjoy the bene ts of aggressive scaling, they become increasingly attractive for use in wireless receivers. Peak device f T 's on the order of 15GHz are available with 0.5m CMOS devices, making possible CMOS implementations of radio receivers in the 1-2GHz frequency range. One wireless system in this range that is particularly amenable to integration is a Global Positioning System GPS, whose signals are at 1.57542GHz. vii Finally, I must reserve the most special thanks for my friends and family, who have enriched my life in so many w a ys. I thank my undergraduate advisor, Dr. John Choma, Jr. of USC for his mentorship and his encouragement to pursue graduate work. I thank my many friends at Stanford and elsewhere for their support and friendship. Among those that I have not already mentioned are