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carrier synchronization

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Carrier synchronization refers to the process of aligning the phase and frequency of a carrier signal with a reference signal in communication systems. This is essential for accurate demodulation and transmission of information, ensuring that the receiver can correctly interpret the transmitted data.
lightbulbAbout this topic
Carrier synchronization refers to the process of aligning the phase and frequency of a carrier signal with a reference signal in communication systems. This is essential for accurate demodulation and transmission of information, ensuring that the receiver can correctly interpret the transmitted data.

Key research themes

1. How can carrier synchronization be achieved and optimized in wireless communication systems with multipath fading and interference?

Carrier synchronization in wireless systems entails adapting the receiver's local oscillator frequency and phase to that of the received signal, which is complicated by multipath fading, Doppler shifts, interference, and hardware imperfections. This theme focuses on algorithmic and system-level techniques—including pilot-assisted methods, Kalman filter approaches, phase-locked loops, and multi-antenna system adaptations—to achieve accurate synchronization under challenging radio conditions for various wireless standards and architectures.

Key finding: Comprehensively surveys recent synchronization techniques for timing and carrier recovery in SISO, MIMO, cooperative relaying, and multiuser/multicell interference systems. It highlights pilot-assisted modulation and joint... Read more
Key finding: Reinforces and extends the classification of carrier synchronization methods across single-carrier and multi-carrier systems, detailing system model assumptions and synchronization challenges. It identifies the role of system... Read more
Key finding: Demonstrates that Kalman filter (KF)-based carrier synchronization techniques surpass traditional phase-locked loop (PLL) methods in scenarios of harsh propagation conditions with high dynamics and severe fading. The paper... Read more
Key finding: Presents the FPGA implementation of carrier synchronization using QPSK Costas loops and timing recovery using differential matched filters within software-defined radios (SDRs). Empirical FPGA resource usage and performance... Read more
Key finding: Analyzes synchronization challenges in diverse wireless systems, including narrowband, ultra-wideband, and multicarrier communications. It identifies the inefficiency of classical correlation methods under low SNR and phase... Read more

2. What are effective approaches to synchronize distributed clocks and compensate clock offsets in networked systems including industrial automation and telecommunication networks?

This theme covers distributed and networked clock synchronization methods essential for coordinated operations in industrial automation (e.g., factory floor devices), telecommunications networks, and embedded distributed systems. Challenges include asymmetric packet delays, fault tolerance, clock drift, propagation delay variations, and maintaining nanosecond-level accuracy across vast or heterogeneous networks. Approaches range from inband synchronization protocols, global distributed clocks, correction algorithms for asymmetric links, to practical network synchronization architectures.

Key finding: Details the 5G standard's capabilities integrated with IEEE 802.1 TSN for supporting industrial-grade time synchronization in factory automation, achieving microsecond-level accuracy necessary for synchronous control of... Read more
Key finding: Introduces an inband signaling clock synthesis method that creates a distributed global clock for interactive teleconferencing and circuit emulation, frequency-locking all nodes to the slowest clock in the network. This... Read more
Key finding: Extends the inband clock distribution methodology demonstrating robustness against network failures by synthesizing a global reference clock from neighboring node signals. The frequency locking scheme guarantees operation... Read more
Key finding: Proposes a novel clock offset estimation framework that models and compensates for asymmetric packet delays by defining asymmetry variations as a linear differential equation. Implemented within the IEEE 1588 Precision Time... Read more
Key finding: Presents a comprehensive synchronization framework addressing timing and frequency alignment across network nodes, focusing on digital transmission and switching systems (PDH, SDH/SONET, ATM, cellular). Introduces... Read more

3. How can distributed synchronous clocking and phase alignment be achieved in hardware and low-power wireless networks to enable robust, scalable synchronization?

This theme investigates hardware-level clock distribution strategies and their application in low-power wireless sensor networks and large synchronous computing systems. Key challenges include reducing clock skew, improving reliability without centralized clock sources, overcoming oscillator instability, and maintaining synchronization robustness against temperature variations and hardware imperfections. Solutions include distributed synchronous clocking algorithms, in-network phase alignment mechanisms, and on-the-fly hardware clock offset compensation.

Key finding: Proposes replacing centralized clock distribution with a network of independent oscillators synchronized via distributed error correction that uses local oscillator phase comparisons to achieve global phase alignment. The... Read more
Key finding: Demonstrates a real-time clock frequency offset compensation technique (Flock) using the radio's high-stability clock as a reference to correct free-running DCO oscillator drifts in low-power wireless nodes. Implemented... Read more
Key finding: Examines clock synchronization challenges specific to Controller Area Network (CAN) embedded distributed systems, emphasizing methods addressing the lack of inherent clock synchronization in CAN. Explores protocol layering... Read more

All papers in carrier synchronization

This paper addresses the carrier-phase estimation problem under low SNR conditions as are typical of turbo-and LDPC-coded applications. In previous publications by the first author, closed-loop carrier synchronization schemes for... more
This paper addresses the carrier-phase estimation problem under low SNR conditions as are typical of turboand LDPC-coded applications. In [1], [2] closed-loop carrier synchronization schemes for error-correction coded BPSK and QPSK... more
In traditional receiver architectures, symbol acquisition and tracking are performed using phase lock techniques that are independent of the channel-code decoding process. In [1] feedback from the constraint-node side of a bi-partite... more
In traditional receiver architectures, symbol acquisition and tracking are performed using phase lock techniques that are independent of the channel-code decoding process. In [1] feedback from the constraint-node side of a bi-partite... more
Timing and carrier synchronization is a fundamental requirement for any wireless communication system to work properly. Timing synchronization is the process by which a receiver node determines the correct instants of time at which to... more