Calculate the volumetric density of either dram or nand. You'll realize that you are mistaken. Cells have actually been getting larger over time.
This information is very difficult to find for laypeople. Can you link some data, because your position doesn't line up with the general concept of shrinking transistor size?
Planar NAND was actually the smallest NAND ever got, back in 2013 or so. They did multipatterning to make absolute tiny cells. They were terrible, unreliable and expensive because small cells leak charge like crazy. Since then, 3D NAND took off, which uses (by comparison) absolutely enormous cells which are grown epitaxially, layer by layer and patterned using cheaper, lower resolution single patterning. The fact that the cells are larger hasn't stopped an incredible reduction in the cost of NAND memory since then since it turns out that epitaxy is cheaper than patterning silicon, so it makes sense to make the cells bigger.
DRAM went 3D even before NAND, simply because making a DRAM cell smaller while still retaining the same capacitance requires either better dielectrics (same resistance from thinner materials) or higher dielectric constants (more charge per thickness). Both reached fundamental limits some time ago (maybe ten years back? I forget), so making the cells smaller stopped being possible. We now keep the internal volume of cells constant (to maintain the same capacitance), but increase their aspect ratio (so they become thicker and narrower). In terms of volume consumed, they actually get slightly larger over time since more and more of the cell ends up being the spacer to keep charge from leaking between adjacent cells.
Logic is in a similar situation, where Intel's 10nm process actually make the transistors taller faster than it made them narrower, so volumetrically the actual active area of the transistor got bigger (although volume decreased slightly anyway since they were able to get rid of more dead space between fins):
https://images.anandtech.com/doci/13405/CLD%2010.jpg
That is why these arguments are so circular. Moore's law is different because transistors keep getting smaller. And I know that transistors keep getting smaller because GBs keep getting cheaper, so I must be getting more of them in a small area, right? But of course no one actually bothers to look up how big a memory cell actually is. If they did, they're realize that transistors get cheaper the same way as batteries, cars, airplanes, TVs, and everything else does: not by squeezing more of them into less silicon, but by exploiting larger and larger economies of scale to make each unit cheaper than before. Often (and going forward, more often than not) that actually means making things like transistors or memory cells physically larger, so long as they can be made more efficiently.