Publications by Ayan Kumar Biswas
Physically equivalent magneto-electric nanoarchitecture for probabilistic reasoning
Probabilistic machine intelligence paradigms such as Bayesian Networks (BNs) are widely used in c... more Probabilistic machine intelligence paradigms such as Bayesian Networks (BNs) are widely used in critical real world applications. However they cannot be employed efficiently for large problems on conventional computing systems due to inefficiencies resulting from layers of abstraction and separation of logic and memory. We present an unconventional nanoscale magneto-electric machine paradigm, architected with the principle of physical equivalence to efficiently implement causal inference in BNs. It leverages emerging straintronic magneto tunneling junctions in a novel mixed-signal circuit framework for direct computations on probabilities, while blurring the
boundary between memory and computation. Initial evaluations, based on extensive bottom-up simulations, indicate up to four orders of magnitude inference run time speedup vs. best-case performance of 100-core microprocessors, for BNs with a million random variables. These could be the target applications for emerging magneto-electric devices to enable capabilities for leapfrogging beyond present day computing.
Energy-efficient hybrid spintronic-straintronic reconfigurable bit comparator
We propose a reconfigurable bit comparator implemented with a nanowire spin valve whose contacts ... more We propose a reconfigurable bit comparator implemented with a nanowire spin valve whose contacts are
magnetostrictive and possess bistable magnetization. Reference and input bits are “written” into the magnetization
states of the two contacts with electrically generated strain and the spin-valve’s resistance is lowered
if the bits match. Multiple comparators can be interfaced in parallel with a magneto-tunneling junction to
determine if an N-bit input stream matches an N-bit reference stream bit by bit. The system is robust against
thermal noise at room temperature and a 16-bit comparator can operate at ∼294 MHz while dissipating at
most ∼19 fJ per cycle.
Straintronic spin-neuron
In artificial neural networks, neurons are usually implemented with
highly dissipative CMOS-base... more In artificial neural networks, neurons are usually implemented with
highly dissipative CMOS-based operational amplifiers. A more energy-efficient
implementation is a “spin-neuron” realized with a magneto-tunneling junction (MTJ)
that is switched with a spin-polarized current (representing weighted sum of input
currents) that either delivers a spin transfer torque or induces domain wall motion in
the soft layer of the MTJ. Here, we propose and analyze a different type of spin-neuron
in which the soft layer of the MTJ is switched with mechanical strain generated by a
voltage (representing weighted sum of input voltages) and term it straintronic spinneuron.
It dissipates orders of magnitude less energy in threshold operations than the
traditional current-driven spin neuron at 0 K temperature and may even be faster. We
have also studied the room-temperature firing behaviors of both types of spin neurons
and find that thermal noise degrades the performance of both types, but the currentdriven
type is degraded much more than the straintronic type if both are optimized
for maximum energy-efficiency. On the other hand, if both are designed to have the
same level of thermal degradation, then the current-driven version will dissipate orders
of magnitude more energy than the straintronic version. Thus, the straintronic spinneuron
is superior to current-driven spin neurons.
Self-similar Magneto-electric Nanocircuit Technology for Probabilistic Inference Engines
Probabilistic graphical models are powerful mathematical formalisms for
machine learning and reas... more Probabilistic graphical models are powerful mathematical formalisms for
machine learning and reasoning under uncertainty that are widely used for
cognitive computing. However they cannot be employed efficiently for large
problems (with variables in the order of 100K or larger) on conventional
systems, due to inefficiencies resulting from layers of abstraction and
separation of logic and memory in CMOS implementations. In this paper, we
present a magneto-electric probabilistic technology framework for implementing
probabilistic reasoning functions. The technology leverages Straintronic
Magneto-Tunneling Junction (S-MTJ) devices in a novel mixed-signal circuit
framework for direct computations on probabilities while enabling in-memory
computations with persistence. Initial evaluations of the Bayesian likelihood
estimation operation occurring during Bayesian Network inference indicate up to
127x lower area, 214x lower active power, and 70x lower latency compared to an
equivalent 45nm CMOS Boolean implementation.
An error-resilient non-volatile magneto-elastic universal logic gate with ultralow energy-delay product
Scientific Reports, Dec 23, 2014
Complete magnetization reversal in a magnetostrictive nanomagnet with voltage-generated stress: A reliable energy-efficient non-volatile magneto-elastic memory
Appl. Phys. Lett., Aug 18, 2014
Energy-efficient magnetoelastic non-volatile memory
Appl. Phys. Lett., Jun 10, 2014
Acoustically assisted spin-transfer-torque switching of nanomagnets: An energy-efficient hybrid writing scheme for non-volatile memory
Appl. Phys. Lett. , Dec 2, 2013
Design of a Fiber-optic Sensing Mosquito Trap
IEEE Sensors Journal
Multiple-Valued Logic …
We realize square operation for quantum ternary logic using basic quantum ternary gates. With the... more We realize square operation for quantum ternary logic using basic quantum ternary gates. With the aid of this square operation, we develop a square-multiplier unit. We further develop a cost measurement technique of the square operation and square multiplication operation through general expressions.
We present a method of synthesizing Ternary GaloisField (GF(3)) based reversible/quantum logic ci... more We present a method of synthesizing Ternary GaloisField (GF(3)) based reversible/quantum logic circuits without any ancillary trits/qutrits and hence without any garbage outputs. We realize multi input ternary Toffoli gate and square functions of GF(3) variables using linear ion trap realizable Muthukrishnan-Stroud (M-S) gates and shift gates in the absence of ancillary qutrits. Then based on the Galois Field Sum of Products (GFSOP)expression of a multi-variable GF(3) function, we synthesize the corresponding circuit
We present the design of quaternary quantum version of reversible circuits such as Toffoli gate, ... more We present the design of quaternary quantum version of reversible circuits such as Toffoli gate, modified Fredkin gate, mux, demux, encoder-decoder using linear ion realizable quaternary Muthukrishnan-Stroud gates. Our realization of quaternary Toffoli gate is more efficient than the previous realization and other quaternary circuits are realized for the time in literature.
Links by Ayan Kumar Biswas
Billionaire Paul Allen sets up new medical institute to discover how living cells actually work
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Jaguar concept car has transparent pillars, windshield HUD with Mario Kart-like ‘ghost’ mode
The world’s most advanced particle accelerator is just 12 inches long and sits on a lab bench in the US
Tesla unveils dual-motor autopilot Model S – new P85D has 691 hp, 0-60 mph in 3.2s
Non-volatile memory improves energy efficiency by two orders of magnitude
IBM cracks open a new era of computing with brain-like chip: 4096 cores, 1 million neurons, 5.4 billion transistors
Western Digital’s HGST division creates new phase-change SSD that’s orders of magnitude faster than any NAND flash drive on the market
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Publications by Ayan Kumar Biswas
boundary between memory and computation. Initial evaluations, based on extensive bottom-up simulations, indicate up to four orders of magnitude inference run time speedup vs. best-case performance of 100-core microprocessors, for BNs with a million random variables. These could be the target applications for emerging magneto-electric devices to enable capabilities for leapfrogging beyond present day computing.
magnetostrictive and possess bistable magnetization. Reference and input bits are “written” into the magnetization
states of the two contacts with electrically generated strain and the spin-valve’s resistance is lowered
if the bits match. Multiple comparators can be interfaced in parallel with a magneto-tunneling junction to
determine if an N-bit input stream matches an N-bit reference stream bit by bit. The system is robust against
thermal noise at room temperature and a 16-bit comparator can operate at ∼294 MHz while dissipating at
most ∼19 fJ per cycle.
highly dissipative CMOS-based operational amplifiers. A more energy-efficient
implementation is a “spin-neuron” realized with a magneto-tunneling junction (MTJ)
that is switched with a spin-polarized current (representing weighted sum of input
currents) that either delivers a spin transfer torque or induces domain wall motion in
the soft layer of the MTJ. Here, we propose and analyze a different type of spin-neuron
in which the soft layer of the MTJ is switched with mechanical strain generated by a
voltage (representing weighted sum of input voltages) and term it straintronic spinneuron.
It dissipates orders of magnitude less energy in threshold operations than the
traditional current-driven spin neuron at 0 K temperature and may even be faster. We
have also studied the room-temperature firing behaviors of both types of spin neurons
and find that thermal noise degrades the performance of both types, but the currentdriven
type is degraded much more than the straintronic type if both are optimized
for maximum energy-efficiency. On the other hand, if both are designed to have the
same level of thermal degradation, then the current-driven version will dissipate orders
of magnitude more energy than the straintronic version. Thus, the straintronic spinneuron
is superior to current-driven spin neurons.
machine learning and reasoning under uncertainty that are widely used for
cognitive computing. However they cannot be employed efficiently for large
problems (with variables in the order of 100K or larger) on conventional
systems, due to inefficiencies resulting from layers of abstraction and
separation of logic and memory in CMOS implementations. In this paper, we
present a magneto-electric probabilistic technology framework for implementing
probabilistic reasoning functions. The technology leverages Straintronic
Magneto-Tunneling Junction (S-MTJ) devices in a novel mixed-signal circuit
framework for direct computations on probabilities while enabling in-memory
computations with persistence. Initial evaluations of the Bayesian likelihood
estimation operation occurring during Bayesian Network inference indicate up to
127x lower area, 214x lower active power, and 70x lower latency compared to an
equivalent 45nm CMOS Boolean implementation.
Links by Ayan Kumar Biswas