Papers by Giuseppe Scotti
International Journal of Circuit Theory and Applications, Nov 11, 2015
A continuous-time complementary metal-oxide-semiconductor differential pair that does not require... more A continuous-time complementary metal-oxide-semiconductor differential pair that does not require the traditional tail current source as a way to control the direct current and common-mode current is presented. Compared with a p-channel long-tailed pair, the proposed non-tailed solution operates under a higher maximum input common-mode voltage that includes (V DD + V SS)/2 even under low supply voltages. Experimental measurements on a prototype fabricated in a 0.35-μm technology (with metal-oxide-semiconductor thresholds greater than 0.6 V) confirm this behavior for supply voltages as low as 1.2 V, whereas the long-tailed pair with the same technology offers the same capability only for supplies higher than 1.6 V.
0.9-V Class-AB Miller OTA in 0.35- $\mu \text{m}$ CMOS With Threshold-Lowered Non-Tailed Differential Pair
IEEE Transactions on Circuits and Systems I-regular Papers, Jul 1, 2017
This paper presents a CMOS operational transconductance amplifier (OTA), suitable for sub-1-V sup... more This paper presents a CMOS operational transconductance amplifier (OTA), suitable for sub-1-V supply applications, whose (input) common-mode voltage can be set to (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {\mathbf {DD}}}+V_{\mathrm {\mathbf {SS}}})$ </tex-math></inline-formula>/2 thanks to two combined techniques applied to the differential pair, namely, threshold voltage lowering and elimination of the tail current generator. Both techniques are implemented through a single common-mode feedback loop, which embeds the shared bulk terminal of the pair. In contrast to other low-voltage approaches employing bulk driving, the proposed OTA is driven from the gate terminals and exploits only MOS transistors in strong inversion. Therefore, effective values of dc gain, gain bandwidth, and noise are found, suitable for high-accuracy switched-capacitor applications. Using a standard 0.35-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> technology with nominal MOS transistors threshold around 0.7 V, a 0.9-V OTA with 0.45-V analog ground was designed and successfully tested. The measured gain and unity gain frequency were 65 dB and 1 MHz with phase margin of 60° for a capacitive load of 10 pF.
Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding ... more Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits in order to prevent Power Analysis (PA) attacks. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions, which allows to design a PA-resistant circuit without routing constraints. In this work we present a fair comparison between SABL, a well-known state of the art transistor level countermeasure which is sensitive to the capacitive mismatches on the complementary lines and requires a customized routing procedure, and DDPL. After having provided a power model for describing the leakage sources for the above mentioned logics, a simple cryptographic circuit has been designed for both SABL and DDPL, and a CPA attack has been mounted. Simulations results show that when capacitive load unbalances are considered, DDPL strongly outperforms SABL in terms of number of traces required for disclose the secret key.
IEEE Transactions on Emerging Topics in Computing, Jul 1, 2017
In this work we focus on Power Analysis Attacks (PAAs) which exploit the dependence of the static... more In this work we focus on Power Analysis Attacks (PAAs) which exploit the dependence of the static current of sub-50nm CMOS integrated circuits on the internally processed data. Spice simulations of static power have been carried out to show that the coefficient of variation of nanometer logic gates is increasing with the scaling of CMOS technology. We demonstrate that it is possible to recover the secret key of a cryptographic core by exploiting this data dependence by means of different statistical distinguishers. For the first time in the literature we formulate the Attack Exploiting Static Power (AESP) as a univariate attack by using the mutual information approach to quantify the information that leaks through the static power side channel independently from the adopted leakage model. This analysis shows that countermeasures conceived to protect cryptographic hardware from attacks based on dynamic power consumption (e.g. WDDL, MDPL, SABL) still exhibit a leakage through the static power side channel. Finally, we show that the Time Enclosed Logic (TEL) concept does not leak information through the static power and is suitable to be used as a countermeasure against both attacks explointig dynamic power and attacks exploiting static power.
Delay-based Dual-rail Pre-charge Logic (DDPL) has been introduced for counteracting power analysi... more Delay-based Dual-rail Pre-charge Logic (DDPL) has been introduced for counteracting power analysis attacks. Basically DDPL allows to achieve a constant power consumption for each data transition even in presence of capacitive load mismatches, thanks to an asynchronous two-phases evaluation. Unlikely other secure logic styles, in DDPL the clock frequency does not fix the security level since it depends on the value of the delay Δ between the complementary signals, which can be designed to be lower than 1ns using current CMOS technologies. However no works exist in which the DPA-resistance of DDPL is tested in presence of early evaluation, due to the different arrival times of the signals. The aim of this work is to provide and validate through transistor level simulations a theoretical model of the variations of the delay Δ during the evaluation phase for each possible data configuration in order to assess the effect of the early evaluation in DDPL, and to design early evaluation free DDPL gates. Moreover a case study crypto-core implemented both with basic and optimized DDPL gates has been designed in which a Correlation Frequency Power Analysis (CFPA) attack is mounted so to detect any leakage on simulated current traces.
IEEE Transactions on Very Large Scale Integration Systems, Jul 1, 2018
Power analysis attacks (PAAs), a class of sidechannel attacks based on power consumption measurem... more Power analysis attacks (PAAs), a class of sidechannel attacks based on power consumption measurements, are a major concern in the protection of secret data stored in cryptographic devices. In this paper, we introduce the secure double rate registers (SDRRs) as a registertransfer level (RTL) countermeasure to increase the security of cryptographic devices against PAAs. We exploit the SDRR in a conventional advanced encryption standard (AES)-128 architecture, improving the immunity of the cryptographic hardware to the state-of-the-art PAAs. In the AES-128 exploiting SDRR, the combinational path evaluates random data throughout the entire clock cycle, and the interleaved processing of random and real data ensures the protection of both combinational and sequential logics. Our technique does not require the duplication of the combinational path to process the random data, thus limiting area overhead, unlike previous RTL countermeasures. The proposed approach is validated by means of PAAs based on real measurements on a field-programmable gate array implementation and on a 65-nm CMOS prototype chip. The protected implementation shows a strongly reduced correlation coefficient for the correct key, and more than three orders of magnitude increase in the measurements to disclosure with respect to the unprotected AES-128. Index Terms-Advanced encryption standard (AES), CMOS, correlation power analysis (CPA), differential power analysis (DPA), Internet of Things (IoT), mutual information (MI), power analysis attack (PAA), register-transfer level (RTL) countermeasure, side-channel attack (SCA).
A Power-Balanced Sequential Element for the Delay-based Dual-Rail Precharge Logic Style
IEEE Transactions on Circuits and Systems I: Regular Papers
Nonlinear calibration allows enhancing the performance of analog and radiofrequency circuits by d... more Nonlinear calibration allows enhancing the performance of analog and radiofrequency circuits by digitally correcting nonlinearities. Often, calibration is performed in the complex baseband domain, and Volterra models are used. These models have hundreds of coefficients, and easily become computationally unfeasible. This is worse in complex Volterra models, because high-order Volterra terms require summing multiple products of the input signal. We propose a generalized complex Volterra model based on one relaxation of Volterra theory: all the nonlinear monomial terms in the model are considered separately, even if they correspond to a single real coefficient in complex Volterra theory. This produces more accurate models, though with a larger number of coefficients. We thus extensively prune the model by means of OMP and OBS techniques. The resulting models have fewer coefficients and/or better accuracy than conventional Volterra models, resulting in a significantly improved accuracy-complexity tradeoff. These results are validated in the experimental calibration of a commercial IF amplifier. The resulting model achieves the same accuracy, with 9 free parameters and 34 multiplications, as the standard Volterra model with 12 parameters and 266 multiplications, resulting in a 25% reduction in the number of parameters, and an 87% reduction in the number of multipliers.
IEEE Transactions on Circuits and Systems I: Regular Papers
The Switched-Resistor (S-R) technique is becoming more and more interesting to implement low-volt... more The Switched-Resistor (S-R) technique is becoming more and more interesting to implement low-voltage low-power active-RC filters with high tuning range and front-end amplifiers for biomedical circuits and systems. This approach exploits MOS switches driven by a duty-cycle-controlled clock signal to achieve tunability of the equivalent resistance and, hence, of the RC time constant. Since S-R circuits can be considered as linear periodically time variant (LPTV) systems with sampled outputs, we exploit the theory of the adjoint (inter-reciprocal) network in order to develop a detailed model of the cyclostationary noise involved in this kind of circuits. The proposed model allows to gain insight into the different noise sources and transfer functions involved, highlighting the circuit parameters on which the cyclostationary noise depends. Validation of the proposed model has been carried out by comparing analytical results against periodic noise simulations referring to a commercial 130nm CMOS process. The validation activity has confirmed the good accuracy of the proposed noise model and provided some useful design guidelines to optimize the noise performance of S-R circuits.
Electronics
In this work, an ultra-low-voltage (ULV) technique to improve body-driven current mirrors is prop... more In this work, an ultra-low-voltage (ULV) technique to improve body-driven current mirrors is proposed. The proposed technique is employed to improve the performance of conventional differential-to-single-ended (D2S) converters which at these low voltages suffer from a low common-mode rejection ratio (CMRR). In addition, the technique aims to improve the performance of the conventional D2S also under a large signal swing and with respect to the process, voltage and temperature (PVT) variations, resulting in a very low distortion, high current mirror accuracy and robust performance. An enhanced body-driven current mirror was designed in a 130nm CMOS technology from STMicroelectronics and an exhaustive campaign of simulations was conducted to confirm the effectiveness of the strategy and the robustness of the results. The enhanced D2S was also employed to design a ULV operational transconductance amplifier (OTA) and a comparison with an OTA based on a conventional D2S was provided. The...
IEEE Access
This paper presents an efficient solution to reduce the power consumption of the popular linear f... more This paper presents an efficient solution to reduce the power consumption of the popular linear feedback shift register by exploiting the gated clock approach. The power reduction with respect to other gated clock schemes is obtained by an efficient implementation of the logic gates and properly reducing the number of XOR gates in the feedback network. Transistor level simulations are performed by using standard cells in a 28-nm FD-SOI CMOS technology and a 300-MHz clock. Simulation results show a power reduction with respect to traditional implementations, which reaches values higher than 30%.
IEEE Access
For the design of inverter-based OTAs with differential input and single-ended output, the differ... more For the design of inverter-based OTAs with differential input and single-ended output, the differential to single-ended (D2S) converter is a key building block. In fact, the performance of the D2S strongly affects the overall common-mode rejection ratio (CMRR) and input common-mode range (ICMR) of the whole OTA. In recent literature, inverter-based OTAs rely on a D2S topology based on an inverter driving another inverter with the input and output tight together which behaves as a ''diode'' connected device to implement a voltage gain approximately equal to −1. However, since this approach is based on the matching of the inverters, the performance of this D2S results sensitive to PVT variations if the bias point of the inverters is not properly stabilized. In this paper we present a novel topology of inverterbased D2S converter, exploiting an auxiliary, standard-cell-based, error amplifier and a local feedback loop. The proposed D2S, compared to the conventional one, exhibits higher CMRR, improved ICMR and better robustness with respect to PVT variations. We present also an ULV, standard-cell-based OTA, which exploits the proposed D2S converter and shows excellent performance figures of merit with low area footprint. 13 INDEX TERMS Standard-cell, ultra-low-voltage (ULV), inverter-based, fully synthesizable. I. INTRODUCTION 14 The era of the Internet-of-Things (IoT) has paved the way 15 to a plenty of new trends in electronic and communication 16 fields, strongly motivating the whole researchers' community 17 to rethink the way in which electronic circuits are designed 18 [1], [2]. The stringent requirements imposed by portable and 19 wearable devices have driven integrated circuits designers 20 to speed up the design time and to drastically reduce the 21 area usage to cut costs [2]. Furthermore, due to the fact that 22 many IoT circuits require energy harvested architectures [1], 23 [2], the design of Ultra-Low-Voltage (ULV) analog building 24 blocks suitable to operate with supply voltages as low as 0.3V, 25
IEEE Micro, 2021
Convolutional computation kernels are fundamental to today's edge computing applications. Interle... more Convolutional computation kernels are fundamental to today's edge computing applications. Interleaved-Multi-Threading (IMT) processor cores are an interesting approach to pursue the highest energy efficiency and lowest hardware cost in edge computing systems, yet they need hardware acceleration schemes to deal with heavy computational workloads like convolutional algorithms. Following a vector approach to accelerate convolutions, this study explores possible alternatives to implement vector coprocessing units in IMT cores, showing the application-dependence of the optimal balance among the hardware architecture parameters.
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher
2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014
ABSTRACT In this work the effectiveness of Leakage Power Analysis (LPA), a new class of side-chan... more ABSTRACT In this work the effectiveness of Leakage Power Analysis (LPA), a new class of side-channel attacks against cryptographic circuits, has been demonstrated on a case study. LPA attacks have been mounted against a bit slice implementation of the Serpent block cipher. After having measured the leakage contribution of a bit slice unit inside the processor, chosen as selection function for LPA attacks, an adequate power model has been identified. In order to consider the on-chip noise due to the static consumption of the other logics inside the processor, an estimation of the SNR has been provided according to the count of equivalent gates. The bit slice sub-block has been designed in a 65nm CMOS technology node for different logic styles, i.e. CMOS, WDDL, MDPL, and SABL. Simulations show that for each logic implementation the correct key of the algorithm has been recovered with a maximum of 50.000 measurements, demonstrating that LPA attack can be successfully carried out against a wide range of logic styles, even if they efficiently thwart standard DPA and CPA attacks. Static power is expected to become greater in downscaled technologies, and thus LPA must be considered a serious threat for the security of cryptographic VLSI circuits.
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2013
Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding ... more Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits in order to prevent Power Analysis (PA) attacks. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions, which allows to design a PA-resistant circuit without routing constraints. In this work we present a fair comparison between SABL, a well-known state of the art transistor level countermeasure which is sensitive to the capacitive mismatches on the complementary lines and requires a customized routing procedure, and DDPL. After having provided a power model for describing the leakage sources for the above mentioned logics, a simple cryptographic circuit has been designed for both SABL and DDPL, and a CPA attack has been mounted. Simulations results show that when capacitive load unbalances are considered, DDPL strongly outperforms SABL in terms of number of traces required for disclose the secret key.
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations
IEEE Transactions on Circuits and Systems I: Regular Papers, 2014
ABSTRACT In this paper, the effectiveness of the recently proposed Leakage Power Analysis (LPA) a... more ABSTRACT In this paper, the effectiveness of the recently proposed Leakage Power Analysis (LPA) attacks to cryptographic circuits is analyzed in the presence of process variations. Reference circuits (e.g., S-BOX, crypto core) were designed in various logic styles, and their robustness against LPA attacks was comparatively evaluated through Monte Carlo simulations in 65 nm. Analysis allowed for better understanding the impact that process variations have on the outcome of LPA attacks, which is an aspect that is not understood currently. Results show that LPA attacks are rather effective also under die-to-die and within-die process variations. Moreover, the comparison between different logic styles showed that standard CMOS logic circuits are extremely vulnerable to LPA attacks. Other logic styles that are robust against traditional Differential Power Analysis (DPA) attacks were also compared. Interestingly, analysis showed that these logic styles are still vulnerable to LPA attacks. Hence, LPA attacks are an even greater threat to Smart Cards information security, compared to DPA attacks. Moreover, traditional methods to protect Smart Cards against DPA attacks are ineffective in counteracting LPA attacks, thereby showing that a significant research effort will be needed to counteract LPA attacks with suitable solutions that ensure high security standards.
International Journal of Circuit Theory and Applications, 2015
A continuous-time complementary metal-oxide-semiconductor differential pair that does not require... more A continuous-time complementary metal-oxide-semiconductor differential pair that does not require the traditional tail current source as a way to control the direct current and common-mode current is presented. Compared with a p-channel long-tailed pair, the proposed non-tailed solution operates under a higher maximum input common-mode voltage that includes (V DD + V SS)/2 even under low supply voltages. Experimental measurements on a prototype fabricated in a 0.35-μm technology (with metal-oxide-semiconductor thresholds greater than 0.6 V) confirm this behavior for supply voltages as low as 1.2 V, whereas the long-tailed pair with the same technology offers the same capability only for supplies higher than 1.6 V.
Journal of Low Power Electronics and Applications
A current-controlled CMOS ring oscillator topology, which exploits the bulk voltages of the inver... more A current-controlled CMOS ring oscillator topology, which exploits the bulk voltages of the inverter stages as control terminals to tune the oscillation frequency, is proposed and analyzed. The solution can be adopted in sub-1 V applications, as it exploits MOSFETS in the subthreshold regime. Oscillators made up of 3, 5, and 7 stages designed in a standard 28-nm technology and supplied by 0.5 V, were simulated. By exploiting a programmable capacitor array, it allows a very large range of oscillation frequencies to be set, from 1 MHz to about 1 GHz, with a limited current consumption. Considering, for example, the five-stage topology, a nominal oscillation frequency of 516 MHz is obtained with an average power dissipation of about 29 µW. The solution provides a tuneable oscillation frequency, which can be adjusted from 360 to 640 MHz by controlling the bias current with a sensitivity of 0.43 MHz/nA.
IEEE Access
This paper presents an approach to design analog building blocks for nanometer systems on a chip ... more This paper presents an approach to design analog building blocks for nanometer systems on a chip (SoCs) that are based on digital standard cells. The proposed approach guarantees that all the CMOS inverters, taken from a standard-cell library, operate with well-defined quiescent current and output voltage, thus allowing the implementation of analog circuits with good robustness against PVT variations. The approach is based on an Analog Body Bias Generator (ABBG) reusable block, similar to the ones adopted in digital applications to cope with process variations, and exploits the bulk terminals of both the p-channel and n-channel MOS transistors of the standard-cell inverter as current and voltage control inputs. The bulk voltages generated by the ABBG are routed to all the standard-cell inverters used for analog functions and allow to set the quiescent current of each cell to a multiple of a reference current and the static output voltage of each cell to half the supply voltage. The full custom design of the ABBG is presented, as well as the design flow to allow the automatic place and route of the proposed standard-cell based analog building blocks. We finally give an example of application to the design of a fully synthesizable four-stage-gain lowpower operational transconductance amplifier (OTA). Both the body bias generator and the OTA have been implemented in a 65-nm CMOS technology. The OTA nominal current consumption is 1.75 A with 0.41-A standard deviation. Good robustness against supply and temperature variations is also found. INDEX TERMS Standard-cell analog circuits, body bias, low voltage, low power, four-stage OTA.
Journal of Low Power Electronics and Applications
In this paper, we introduce a novel tree-based architecture which allows the implementation of Ul... more In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performan...
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Papers by Giuseppe Scotti