Joy Chowdhury

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Numerical investigation of optimized CZTSSe based solar cell in Wx-Amps environment

The CZTSSe is the modified version of CZTS with selenium infusion. It shows maximum efficiency in... more The CZTSSe is the modified version of CZTS with selenium infusion. It shows maximum efficiency in the band gap from 1 to 1.4 eV. In our present work CZTSSe based solar cell is investigated using Wx-Amps tool. The Mo layer, absorber layer, CdS layer, i-ZnO [4]and Al-ZnO layers with their electrical, optical and material parameters are fitted in the tool. The vital parameters such as carrier density, thickness of the CZTSSe absorber layer, operating temperature, CdS buffer layer thickness and its carrier density on the cell interpretation are calculated. From[4] the simulation results it is apparent that the optimal absorber layer varies from 2.9 µm to 3.7 µm. The temperature variation has a strong influence on the efficiency of the cell. An optimal efficiency of 22% (With Jsc=33 mA/cm2, Voc=0.98 V, and fill factor= 68%) are attained. These results will give some insight for makeing higher efficiency CZTSSe based solar cell.The CZTSSe is the modified version of CZTS with selenium infusion. It shows maximum efficiency in the band gap from 1 to 1.4 eV. In our present work CZTSSe based solar cell is investigated using Wx-Amps tool. The Mo layer, absorber layer, CdS layer, i-ZnO [4]and Al-ZnO layers with their electrical, optical and material parameters are fitted in the tool. The vital parameters such as carrier density, thickness of the CZTSSe absorber layer, operating temperature, CdS buffer layer thickness and its carrier density on the cell interpretation are calculated. From[4] the simulation results it is apparent that the optimal absorber layer varies from 2.9 µm to 3.7 µm. The temperature variation has a strong influence on the efficiency of the cell. An optimal efficiency of 22% (With Jsc=33 mA/cm2, Voc=0.98 V, and fill factor= 68%) are attained. These results will give some insight for makeing higher efficiency CZTSSe based solar cell.

Novel Threshold Voltage Model Incorporating Band-to-Band Tunneling in Heterostructure p-MOSFET

2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2019

Threshold voltage (with and without body bias) for heterostructure pMOSFET is analytically explor... more Threshold voltage (with and without body bias) for heterostructure pMOSFET is analytically explored as a function of applied bias for Si-SixGe1-x material system in presence of band-to-band tunneling. Threshold voltage for given device structure is calculated in the light of body effect for different structural parameters, and mole fraction of Ge is chosen as 0.28 for that operating point where 2DEG is yet to be formed, and thus making it apposite for estimating subthreshold conduction. Using this optimum structure, BTBT effect is incorporated to quantity the variation of threshold voltage over a range of source-to-gate voltages (VSG). The results accord with available experimental data for very low and higher values of source-to-drain voltage (VSD). Result is also computed in absence of tunneling effect, and drastic variation is observed which speaks in favor of our proposed model of subthreshold conduction which can be further extended for modeling of sub-threshold drain current characteristics of HFETs.

Analytical modeling of dielectrically modulated broken-gate tunnel FET biosensor considering partial hybridization effect

Computers & Electrical Engineering, 2022

Analytical study of double gate MOSFET: A design and performance perspective

2018 2nd International Conference on Inventive Systems and Control (ICISC), 2018

This paper presents an in depth study and analysis which shows that the Double gate MOSFET has em... more This paper presents an in depth study and analysis which shows that the Double gate MOSFET has emerged as one of the most favorable devices due to short channel effect immunity, off-current reduction ability and more scaling possibility. The devices with less than 0.1 μm gate length can maintain near ideal subthreshold factor. This paper also presents some new modifications in the existing devices, in order to keep up with the performance improvements, such as Asymmetric Undoped Double gate MOSFET, Symmetric and Asymmetric Underlap Double gate MOSFET, high K TMDG MOSFET, high K Spacer Asymmetric Underlap Double gate MOSFET, Graded Channel Double gate MOSFET and Dual-insulator Double gate MOSFET.

Analytical Drain Current Model for Super-Threshold Region of Double Gate Tunnel FET

2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 2020

To support miniaturization and low power demands of the electronic systems market, the essential ... more To support miniaturization and low power demands of the electronic systems market, the essential scaling laws are marred due to performance degradation by Short Channel Effects. The recently developed TFETs follow interband tunneling (BTBT) as their current injection mechanism and have better subthreshold swing (below 60mV/dec) compared to the conventional SOI MOSFETs. This article presents an analytical model for drain current in the super threshold region. The parabolic potential approach is used including the effect of fringing fields and mobile charges in the channel. This model predicts the surface potential, electric field and BTBT current with reasonable accuracy, thus reflecting most of the physical device phenomena.

Delay and Power Optimization of Memristor based basic Sequential Circuit Element

International journal of engineering research and technology, 2018

The invention and successful fabrication of the memristor forced nano scale designs to start thin... more The invention and successful fabrication of the memristor forced nano scale designs to start thinking beyond the scope of the conventional MOSFETS or rather the use of transistors as a whole. Memristors have a history mechanism which enables storage operations along with the inherent bipolar resistive switching property. Various existing mathematical models give shape to a implementable prototype of memristors which can be further implemented and tested in suitable circuits thus determining some crucial circuit parameters and how they differ from the traditional transistor based designs. In this paper Dflip flop has been proposed with the aid of Memristors using MRL(Memristor Ratioed Logic)and a few critical parameters such as delay, power, gate count etc have been calculated and studied. The simulations were run using Verilog-AMS and Virtuoso IC6.1.6 simulator.

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Adiabatic approach for charge restoration in low power digital circuits

2018 2nd International Conference on Inventive Systems and Control (ICISC), 2018

The main idea dominating the current trends in VLSI circuits is to offer large scale integration ... more The main idea dominating the current trends in VLSI circuits is to offer large scale integration coupled with extensive power reduction solutions, even with newer devices and topologies[1]-[2]. However the significant increase in the gate switching energy results in higher power dissipation and costly heat sinks. At that point, to constrain the dissipation of power, elective arrangements at various level of deliberation are suggested. The power dissipation is significantly reduced by the adiabatic logic structure at the expense of circuit complexity to accomplish low power dissipation, switching procedures are used. Adiabatic logic discussed here provides an approach to use the energy repeatedly that is put away in the load capacitors. This paper briefs some of the adiabatic logic families such as PFAL and SAL. It aims at comparing the effectiveness of adiabatic logic with respect to power dissipation and delay. The implementation of the 4 bit CLA validates the credibility of the logic. A graph has been plotted to show the effect of temperature on sub threshold adiabatic logic based 4 bit CLA. The simulation results obtained from the vituoso environment of cadence tool suggests three folds power reduction in the ECRL topology as compared to the other existing topology.

Novel center potential based analytical sub-threshold model for dual metal broken gate TFET

Circuit World, 2020

Purpose The purpose of this paper is to present an improved model based on center potential inste... more Purpose The purpose of this paper is to present an improved model based on center potential instead of surface potential which is physically more relevant and accurate. Also, additional analytic insights have been provided to make the model independent and robust so that it can be extended to a full range compact model. Design/methodology/approach The design methodology used is center potential based analytical modeling using Psuedo-2D Poisson equation, with ingeniously developed boundary conditions, which help achieve reasonably accurate results. Also, the depletion width calculation has been suitably remodeled, to account for proper physical insights and accuracy. Findings The proposed model has considerable accuracy and is able to correctly predict most of the physical phenomena occurring inside the broken gate Tunnel FET structure. Also, a good match has been observed between the modeled data and the simulation results. Ion/Iambipolar ratio of 10^(−8) has been achieved which is ...

Design and stability analysis of CNTFET based SRAM Cell

2016 IEEE Students' Conference on Electrical, Electronics and Computer Science (SCEECS), 2016

Static Random Access Memory (SRAM) is one of the most crucial and critical memory devices used in... more Static Random Access Memory (SRAM) is one of the most crucial and critical memory devices used in today's technological environment. The continuous scaling of CMOS technology significantly limits the performance of 6T SRAM cell in terms of leakage power and stability. With remote chances to further improve the MOSFET technology in future, Carbon Nanotube Field Effect Transistors (CNTFETs) are being widely studied as the possible alternatives. In this paper, the conventional 6T SRAM cell is compared with CNTFET based SRAM cell. The conventional 6T SRAM cell is designed using Cadence Virtuoso Tool in 180nm and 45nm Technology. The Verilog-A code of CNTFET for replacing nMOS and pMOS are separately simulated in Cadence Virtuoso Tool. The CNTFET based SRAM cell is technology independent. The performances are evaluated in terms of leakage power, delay and stability to show that the CNTFET based SRAM cell can successfully replace the CMOS based SRAM cell.

ADC and DAC for biomedical application

In the present era, there is tremendous need for digitization of medical data, which are collecte... more In the present era, there is tremendous need for digitization of medical data, which are collected from animals and human beings, etc. For this purpose, the collected samples are converted into digital format for proper analog-to-digital converters (ADCs). After the required preprocessing, these can be used, and for analysis, these data are again converted back into readable format using suitable digital-to-analog converters (DACs). In medical electronics, suitable sensors are used for data acquisition, and much attention is directed toward biomedical sensors integrated with a suitable data converter architecture. These integrated medical tools (or systems) are generally used for online diagnosis and monitoring without incurring heavy expenditure. This chapter will give brief emphasis on the coding and quantizing, data converter parameters, ADC and DAC architecture, and a few applications of ADC and DAC in biomedical. In this chapter, there are sections: Section 1 gives a brief intr...

Concise Review: Bone Marrow for the Treatment of Spinal Cord Injury: Mechanisms and Clinical Applications

STEM CELLS, 2011

Transplantation of bone marrow stem cells into spinal cord lesions enhances axonal regeneration a... more Transplantation of bone marrow stem cells into spinal cord lesions enhances axonal regeneration and promotes functional recovery in animal studies. There are two types of adult bone marrow stem cell; hematopoietic stem cells (HSCs), and mesenchymal stem cells (MSCs). The mechanisms by which HSCs and MSCs might promote spinal cord repair following transplantation have been extensively investigated. The objective of this review is to discuss these mechanisms; we briefly consider the contro-versial topic of HSC and MSC transdifferentiation into central nervous system cells but focus on the neurotrophic, tissue sparing, and reparative action of MSC grafts in the context of the spinal cord injury (SCI) milieu. We then discuss some of the specific issues related to the translation of HSC and MSC therapies for patients with SCI and present a comprehensive critique of the current bone marrow cell clinical trials for the treatment of SCI to date.

format_quoteIntravenous MSC delivery resulted in 2.3% and 1.6% engraftment, while lumbar puncture delivery increased engraftment to 4.1% and 3.4%.format_quote

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From the age of the pyramids to the superfast world-what has changed in the management of spinal injuries?

Clinical Medicine, 2012

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Implementing trigonometric nonlinearity in linear ion-drift memristor model

2015 International Conference on Industrial Instrumentation and Control (ICIC), 2015

Trigonometric Window Functions for Memristive Device Modeling

by Joy Chowdhury and N. Rout

2015 Fifth International Conference on Advanced Computing & Communication Technologies, 2015

After the fourth passive circuit element(Memristor) came to existence in 2008 its tremendous pote... more After the fourth passive circuit element(Memristor) came to existence in 2008 its tremendous potential to be used as a replacement for MOSFETS made its mathematical modeling very imperative. Various device models for the memristor had been proposed earlier such as the linear ion drift model, non linear ion drift model, tunnel barrier model, and a recently proposed TEAM model. In case of linear ion drift model a window function is needed to restrict the state variable within device bounds. In this paper we propose a modified window function which accounts for greater non linearity than the existing windows such as the Jogelkar, Biolek or Prodromakis windows.

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Design and Stability Analysis of CNTFET based SRAM Cell

by Tannu Newar, Joy Chowdhury, and mohita singh

—Static Random Access Memory (SRAM) is one of the most crucial and critical memory devices used i... more —Static Random Access Memory (SRAM) is one of the most crucial and critical memory devices used in today's technological environment. The continuous scaling of CMOS technology significantly limits the performance of 6T SRAM cell in terms of leakage power and stability. With remote chances to further improve the MOSFET technology in future, Carbon Nanotube Field Effect Transistors (CNTFETs) are being widely studied as the possible alternatives. In this paper, the conventional 6T SRAM cell is compared with CNTFET based SRAM cell. The conventional 6T SRAM cell is designed using Cadence Virtuoso Tool in 180nm and 45nm Technology. The Verilog-A code of CNTFET for replacing nMOS and pMOS are separately simulated in Cadence Virtuoso Tool. The CNTFET based SRAM cell is technology independent. The performances are evaluated in terms of leakage power, delay and stability to show that the CNTFET based SRAM cell can successfully replace the CMOS based SRAM cell.

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