Marius Neag

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Associate Professor at Technical University of Cluj-Napoca, Romania (TUC-N). Marius Neag received the Electronic Engineer Diploma from the TUC-N, in 1991 and was awarded the PhD degree by the University of Limerick, Ireland, in 1999. After working several years in Ireland and the US as a senior designer of RF, analog and mixed-signal ICs he returned to the TUC-N. He co-founded the “Digitally-Enhanced RF and Analog IC" Research Group. He is the co-author of 3 patents, 3 books and 150 scientific papers. Besides IC design his research interests include circuit theory and its applications in acoustics.

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電気-熱シミュレーションを用いたLDO電圧調整器の過熱保護のための設計方法論【Powered by NICT】

IEEE Conference Proceedings, 2016

Over-Temperature Protection for a Switched-Capacitor DC-DC Converter with Controlled Charging Current

2018 International Semiconductor Conference (CAS), Sinaia, 10-12 Oct. 2018, Oct 1, 2018

This paper presents an over-temperature protection (OTP) circuit for a DC-DC converter based on s... more This paper presents an over-temperature protection (OTP) circuit for a DC-DC converter based on switching capacitors (SC DC-DC). The circuit was designed by using a two-step approach that encompasses running both electrical and electro-thermal simulations. The die temperature distribution was analyzed for two critical operational scenarios in order to identify the worst case and to provide design data for implementing a robust and precise OTP. Finally, a design example of a SC DC-DC with OTP is presented in some detail, complete with the key electrical and electro-thermal simulation results.

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Capacitor Multiplier with One Transconductor Cell

by Marius Neag and Paul Coste

2019 International Semiconductor Conference (CAS), Sinaia, 9-11 Oct. 2019, Oct 1, 2019

A new programmable capacitance multiplier implementation is presented in this paper. It is based ... more A new programmable capacitance multiplier implementation is presented in this paper. It is based on a fairly known architecture, but the proposed circuit employs only one linear transconductor (Gm cell). The mathematical analysis of the new capacitance multiplier is presented along with simulations performoed on a circuit implemented in standard 0.18-μm CMOS process. Two applications are also presented: a triangular waveform generator and afully differential lossy integrator, both with emulated capacitances programmable over three octaves.

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New ways to generate stimuli for measurements on sensitivity to supply variations

2020 IEEE International Semiconductor Conference (CAS2020), Sinaia, Romania, 7-9 Oct. 2020, Oct 7, 2020

This paper presents three novel solutions for generating voltage stimuli necessary to assess the ... more This paper presents three novel solutions for generating voltage stimuli necessary to assess the sensitivity of analog circuits to supply variations by performing laboratory measurements. The resulting test setups replicate the real-life operating conditions of the device-under-test (DUT), including the decoupling capacitors it may require. All three solutions are based on voltage regulators, both integrated and implemented with discrete devices. The setups can be realized by using only commercially-available devices, standard arbitrary function generators and oscilloscopes. Simulation and measurement results demonstrate that the proposed circuits can supply the DUT signals with user-defined shape and amplitude, and frequencies up to tens of MHz, added to the required DC voltage level.

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Design options for implementing in standard CMOS drivers for MEMS body biasing

Microelectronics Journal, Mar 1, 2020

This is a PDF file of an article that has undergone enhancements after acceptance, such as the ad... more This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

format_quoteThe paper proposes circuit solutions for implementing multi-purpose drivers for MEMS body biasing, validated through simulation.format_quote

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Design methodology for over-temperature and over-current protection of an LDO voltage regulator by using electro-thermal simulations

Microelectronics Reliability, Dec 1, 2017

This paper presents a methodology for designing over-temperature and over-current protection (OTP... more This paper presents a methodology for designing over-temperature and over-current protection (OTP and OCP) circuits for low drop-out voltage regulators (LDOs). The OTP monitors the die temperature developed within the LDO and disables its output stage when the temperature reaches a certain, user-defined, level (the OTP activation point). If the LDO output current reaches a set threshold (the OCP activation point), the OCP takes control of it, keeping the current value to an acceptable level. The proposed methodology involves running iteratively electrical, thermal and electro-thermal simulations. It addresses three major issues: first, it allows the designer to identify the suitable layout placement of the OTP and OCP sensors, based on the temperature distribution within the LDO power-stage. Second, the OTP and OCP activation points can be set accurately by taking into account coupled electro-thermal phenomena and the unavoidable differences between the temperature and current sensed by the protection circuits and those developed within the worst-case LDO section. Finally, the LDO design can be fine-tuned considering complex scenarios of real-life operation and test requirements. An LDO was designed using this methodology and the paper provides a direct comparison between the expected (simulated) results and measurements performed on the silicon implementation.

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Full-Wave Current Sensor for Automotive Synchronous Buck Converter

This paper presents a novel current sensor suitable for fully integrated synchronous buck convert... more This paper presents a novel current sensor suitable for fully integrated synchronous buck converters that operate over a wide range of input voltages, such as those used in automotive applications. Its topology was derived by addressing shortcomings of a solution published previously. A design example validates the proposal: the sensor implemented in a High-V 180nm CMOS process can operate with input voltages up to 45V, over a wide range off duty cycle values – between 10% and 70% - with errors smaller than 3% for inductor currents larger than 200mA.

I/Q Imbalance Compensation Algorithm based on Neural Networks

Journal of Automation Mobile …, 2009

1. Introduction In the last two decades, increased consumer interest in wireless communication de... more

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Modelling Thermally-Induced Mechanical Faults in Power Integrated Circuits Assemblies

2020 IEEE 26th International Symposium for Design and Technology in Electronic Packaging (SIITME)

The structure of a Double Diffused Metal-Oxide-Semiconductor (DMOS) device is complex and consist... more The structure of a Double Diffused Metal-Oxide-Semiconductor (DMOS) device is complex and consists of multiple routing metallization layers interconnected through vias embedded in Silico Dioxide (SiO2). The predominant failure mechanisms that occur after a large number (e.g. 106) of active cycles are the crack formation between two adjacent signal metal lines and/or delamination of power metal plates from the SiO2 layer. Numerical simulation of power IC's based on finite element analysis is one of the most used simulation tools for the defect risk assessment. A novel subdivision method combined with the homogenization and nonconformal mesh of computational structure is applied to the model to efficiently simulate the complex IC structures. Results are assessed on a commonly DMOS layout substructure.

Digital Dual Mode control VCM-Burst of DC-DC Buck Converter Operating Over Wide Ranges of Input Voltages and Load Currents

2023 International Semiconductor Conference (CAS)

LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients

IEEE Transactions on Circuits and Systems I-regular Papers, Nov 1, 2020

This article proposes an LDO with fast response to load transients that can handle any practical ... more This article proposes an LDO with fast response to load transients that can handle any practical capacitive loads. These features are mainly due to a novel frequency compensation circuit tailored for its error amplifier, which is based on an improved version of the popular common gate amplifier. A simple yet effective approach to the small-signal analysis of LDO with multiple feedback loops is employed to analyse intuitively the LDO and derive key design constraints. Simulation and measurement results performed on a test chip implemented in standard 130nm CMOS process validated the proposed LDO. It requires only 0.7µA quiescent current but exhibits an excellent response to load transients: when the load current jumps from 0A to 100mA in 1µs the output voltage presents an undershoot of 76mV and an overshoot of 198mV, without decoupling capacitors. It compares well against seven LDOs designed with common gate error amplifiers for similar levels of supply voltage, output voltage and current and against seven fast LDOs employing different error amplifiers. A figureof-merit that considers the quiescent current, the maximum load current and capacitance, as well as the output voltage deviation, yielded a value for our LDO 39.8 times better than for the nearer competitor that employs common gate amplifier and 6 times better than the one employing a different error amplifier. When considering edge time and process scaling the performance of the proposed LDO is 4.8, respectively 4.5, times better than the second best in both comparisons.

$Fig. 7. Frequency characteristics of transfer ratios described by (7) & (9) and return ratio described by (10) for large values of IL. The expression of |77vNER\|max Gepends on the position of the dominant pole, @,. In turn, @ is set by the loading conditions. RpCy, < RgC, for large load currents or if the output capacitor has a small value. In these conditions, the dominant pole of 7T7yner is given by a, = RC which translates (19) into:$

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A Capacitor-less LDO with High PSR over a wide frequency range

This paper presents a capacitor-less low dropout (LDO) voltage PMOS regulator with high power sup... more This paper presents a capacitor-less low dropout (LDO) voltage PMOS regulator with high power supply rejection (PSR). The proposed LDO combines into a single core two differential stages: a primary one - as error amplifier for the negative feedback loop - and a secondary one, used to create a feedforward cancellation path from the supply to the gate of the pass transistor. With this arrangement the LDO can provide a PSR of -43dB at 1MHz for the maximum load current of 50mA. This performance is achieved with only 20µA quiescent current and a load capacitor of 100pF. The LDO is designed in a 0.18µm standard CMOS process.

Current-mode quadrature ring oscillator for bioimpedance applications

A tunable frequency current-mode quadrature ring oscillator for bioimpedance spectroscopy applica... more A tunable frequency current-mode quadrature ring oscillator for bioimpedance spectroscopy applications is presented. It consists of four cross-coupled differential delay cells implemented using log domain circuits. The oscillation frequency can be fine-tuned using the bias current of the delay cells and coarse tuned by modifying the capacitors of the delay cells. The ring oscillator output current can be used for bioimpedance measurements as a current stimulus via a current buffer. Two quadrature output currents are converted using current-input comparators to in-phase and quadrature square voltages needed for demodulation on the bioimpedance readout side. The ring oscillator was implemented in a standard 180nm CMOS technology using MOS transistors operating in weak inversion. The oscillation frequency can be modified from 7.27kHz to 15.13MHz, while consuming from 1.05mA to 1.23mA from a 2V supply voltage.

Precise and robust enable control circuitry for LDO voltage regulators

by Marius Neag and Cosmin-Sorin Plesa

International Semiconductor Conference CAS 2015, Sinaia, Romania, 12-14 October 2015, Oct 1, 2015

This paper presents novel circuit solutions for two issues related to the Enable control of low-d... more This paper presents novel circuit solutions for two issues related to the Enable control of low-dropout (LDO) voltage regulators: setting precise voltage thresholds for the ON/OFF states of the LDO and ensuring that in the OFF state the LDO output is not affected by fast variations of the supply voltage. First, an Enable circuit with hysteresis and temperature compensated thresholds is described: the accuracy of its threshold voltages - including their low temperature coefficients - are predicted by analytical analysis and validated by measurements performed on a silicon implementation. Second, a simple yet effective comparator is proposed, able to significantly reduce the effect the supply voltage variations have on the output voltage when the regulator is in OFF state. Simulation results show that, when the supply voltage varies from 0 to 28V in 28μs, the overshoot of the output voltage is reduced from 5.5V to under 200mV, that is by a factor of 35.

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Design Options for Current Limit and Power Limit Circuit Protections for LDOs

Advances in Electrical and Computer Engineering, 2019

This paper presents novel circuitry for protection of the power transistor in LDOs with adjustabl... more

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Design Optimization of Analog Active Circuits Using the Genetic Algorithm

This paper presents an optimization tool for the design of analog circuits implemented with comme... more This paper presents an optimization tool for the design of analog circuits implemented with commercially-available discrete devices. It takes into consideration the standard values available for the passive components, as well as the nonidealities of commercially-available active devices. The multi-criteria optimization is based on a genetic algorithm developed in Matlab specifically for this task, that works in conjunction with components of the OrCAD package, namely the OrCAD CIS Capture and PSpice. The effectiveness of the proposed procedure is demonstrated by a real-life example, the optimized design of a fourth-order low-pass filter implemented with Operational Amplifiers and discrete resistors and capacitors.

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A novel approach to the stability analysis of conditionally stable circuits

This paper presents an intuitive analysis of a class of conditionally stable feedback circuits, t... more This paper presents an intuitive analysis of a class of conditionally stable feedback circuits, that are stable although the Bode stability criteria indicates otherwise: at the frequencies their loop gain phase characteristics first reach -180°, the magnitudes of their magnitude characteristics are far larger than unity. An easy-to-use stability criterion is introduced by means of two circuit examples. Only the usual loop gain Bode plots are required to apply this criterion, but it suits only conditionally stable systems with no right-hand plane (RHP) poles in the open loop transfer function, T(s), and no integrators. A separate, three-step method for assessing the stability of feedback circuits with RHP poles and integrators is also proposed. It applies to all conditionally stable circuits and involves extracting the poles and zeros of T(s) and plotting the corresponding Nyquist contour.

Design Options for Thermal Shutdown Circuitry with Hysteresis Width Independent on the Activation Temperature

Advances in Electrical and Computer Engineering, 2017

This paper presents several design options for implementing a thermal shutdown circuit with hyste... more

format_quoteThe thermal shutdown circuit's design specifies activation temperature at 180°C±10% and hysteresis width of 15°C±10% for automotive applications.format_quote

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OA-based programmable gain amplifier for UWB applications

ABSTRACT This paper presents an architecture for the analog baseband of an Zero-IF UWB receiver t... more ABSTRACT This paper presents an architecture for the analog baseband of an Zero-IF UWB receiver that is slightly different from the standard approach; the key block of this architecture is a high-linearity PGA with constant bandwidth, independent of gain settings. A transistor-level implementation of the PGA is presented; simulation results for a 0.15um CMOS process demonstrate the performance of the proposed PGA: gain programmable between 0 and 22dB, in 2dB steps; bandwidth ranging between 255 and 300MHz; O1dBCP above 13dBm for all gain settings.

Sub-band adaptive filtering for acoustic echo cancellation

Proceedings of European Conference on Circuit Theory and Design, ECCTD2009, Antalya, Turkey, 23-27 August 2009, Aug 1, 2009

Sub-band filtering is employed in various system identification applications. It reduces the comp... more Sub-band filtering is employed in various system identification applications. It reduces the computational complexity and adaptation time. The paper focuses on sub-band filtering for acoustic echo cancellation. A Simulink model for 2, 4, 8 sub-bands was created and simulated. The echo is created by applying a vocal test to a first Schroeder reverberator. The performance of the full- and sub-band echo canceller is measured in terms of error signal and echo-return loss enhancement.

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