Nobuhiko Koike

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Work in progress -a dual mode remote laboratory system supporting both real-time and batch controls by making use of virtual machines

This paper describes a dual mode remote laboratory system for an educational hardware experiment.... more This paper describes a dual mode remote laboratory system for an educational hardware experiment. There are two different approaches, namely real-time and batch modes, which control a laboratory system remotely. In the real-time mode, the spatially distributed hardware and test apparatuses are occupied by users during entire experiment periods exclusively. It gives the users interactive and real-laboratory like test environments, but the physical number of platforms will give the system usage limit. As for the batch mode approach, this mode resolves such shortcomings and achieves efficient equipment sharing among concurrent users, but the response-time is rather sacrificed. As neither of them does solve the problems, new remote laboratory environment which resolves the time restriction and the spatial restriction is proposed. The virtual machine (VM) technology has been employed to resolve these problems. As the VM controller allocates both real-time mode VMs and batch mode VMs dynamically, an efficient sharing of apparatuses and an improved interactivity can be achieved.

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Top-Down Education for Digital Logic Design Course Based on Cellular Methods

Frontiers in Education Conference, 2003

We propose a new top-down eLearning tool for hardware logic design course using the cellular meth... more We propose a new top-down eLearning tool for hardware logic design course using the cellular method, where students can keep focusing on their primary interests to achieve complex logic circuits design successfully. At a modern logic design classroom, hardware description languages such as VerilogHDL are mostly used to describe circuits for FPGAs (Field Programmable Gate Arrays). These HDL descriptions are wrapped in XML (Extensible Markup Language) with a specially arranged XML vocabulary, in order to share designed modules among students on the Web. Although XML gives us a common and convenient Web framework, it becomes difficult to verify and maintain conformance among designed modules if the system becomes very large. To overcome this problem, we employed the cellular models that ensure the consistency among design modules and support a top-down design methodology. The proposed system is expected to achieve higher efficiency for preparing logic design lecture courses. This paper presents the basic XML vocabulary design to describe hardware modules efficiently, and also presents a sample eLearning courseware on the Web employing this XML vocabulary.

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Multi-user/Multi-test-bed Remote Hardware Laboratory with Job Management System

A new remote hardware laboratory, supporting multiuser/multi-test-bed, has been developed. Learne... more A new remote hardware laboratory, supporting multiuser/multi-test-bed, has been developed. Learners can perform experiments remotely utilizing actual hardware and actual measurement tools. It employs FPGAs for design implementation test-beds. It can handle many experiment sessions concurrently, by making use of actual hardware test-beds in time and space division fashions. Learners at remote sites can perform actual hardware experiments in parallel. It realized seamless remote and actual hardware laboratories. The combinatorial use of FPGA/PC connected test hardware and PC-based measurement equipment has made it possible to develop a multi-user/multi-test-bed remote hardware experiment system. In order to allocate available experimental environments for users at the same time, a job management system is employed. The prototype system of self-learning experiment environment for digital circuit designs and experiments is in use for 3 rd class CS students at Hosei University.

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A New Remote Laboratory for Hardware Experiment with Shared Resources and Service Management

A new remote laboratory system for hardware experiment has been developed. It employs shared reso... more

Parallel and distributed processing laboratory for CS 2nd grade students: an active N to N networking approach

This work describes the authors' approach at their university in the last three years for com... more This work describes the authors' approach at their university in the last three years for computer science second grade undergraduate students to experience parallel and distributed computing. The goal is to give a solid understanding of parallel and distributed processing technologies and to build up basic skills in the field, such as parallel algorithms, multi-thread/network programming, IP/socket communication, MVC paradigm, RPC/remote method invocation (RMI), Database/SQL, and Java/JDBC. The course features a combination of active experimental learning and N to N networking approach. Unlike typical laboratories where central parallel servers or parallel machines are used (N users to one system networking), our laboratories do without them and instead organize groups of student PCs to form virtual parallel/distributed systems (N users to N systems networking). All PCs work as servers as well as clients. Parallel bucket sorting and virtual shopping mall implementations are employed for the course projects. The course consists of 14 ninety-minutes sessions within a semester, including introductory Java network programming and two projects. As the time is limited, homework and pre-laboratory experiments are encouraged. Web based course material distribution and the virtual laboratory environment contributed to student success.

Top-down eLearning tools for hardware logic design

ABSTRACT New top-down eLearning tools for hardware logic design courses using the cellular method... more ABSTRACT New top-down eLearning tools for hardware logic design courses using the cellular methods are presented that enable students to keep focusing on their primary interests so that they can achieve complex logic circuits design successfully. In a modern logic design classroom, hardware description languages such as VerilogHDL are mostly used to describe circuits for FPGAs. The circuit in each module is described in VerilogHDL and the entire circuit is implemented by combination of designed modules. These HDL descriptions are wrapped in XML and enriched by a specially extended XML vocabulary, in order to share designed modules among learners on the Web. Although XML gives us a common and convenient Web framework, it becomes difficult to verify, validate, and maintain conformance among designed modules if the system becomes very large. To overcome this problem, we employed the cellular models that ensure the consistency among design modules and support a top-down design methodology. The proposed top-down eLearning tools can generate these circuit design data, distribute them to the learner, and manage the design database. The circuit design data wrapped in XML vocabulary are offered to the learner as a self-learning material of the courseware using the top-down (i.e. goal-oriented) method, according to the demand.

New Virtual Remote Laboratory Environments for Logic Circuit Design Realizing an efficient sharing of Test Equipments and Concurrent User Support

... e-Learning System for Hardware Design and Experiment of Digital Circuits", 35thASEEIIEEE... more

IoT Remote Group Experiments in the Cyber Laboratory: A FPGA-based Remote Laboratory in the Hybrid Cloud

In accordance with the resent advancement in Internet of Things (IoT), the needs for IoT experime... more In accordance with the resent advancement in Internet of Things (IoT), the needs for IoT experiment platform have been ever increasing. IoT system consists of various technologies such as networking, sensor controller, edge-side computing, server-side big data collections, analysis and their visualizations. An experimental environment that can handle the development and experiments of such an IoT system become important. In the IoT system, a highly flexible system structure for applications using Field Programmable Gate Array (FPGA) is required. The authors propose the Remote Laboratory System for handling IoT experiments in the Cyber Laboratory, which is an educational FPGA-based remote laboratory for under-graduate university students. It enables not only to use available board-level small computers but also to use FPGA boards for prototyping IoT edges. It can also organize the IoT cloud-server side programs in the hybrid cloud. The FPGA based edge-side computing approach can have much more freedom and flexibility to implement various sensor controls those can be customized for specific IoT applications. The use of free micro-processor IP-core and re-organizing the available FPGA CAD design platform allow us to reduce the burden of design and implementation efforts for the construction of new Cyber Laboratory to accommodate IoT designs and experiments. It also contributed to reduce the students' amount of efforts to conduct their own IoT design and experiments, where students are required to have various skills in Information Technologies (IT): hardware design, edge-side computing, server-side computing, networking and infrastructure construction. The use of the Docker container/Swarm and the Docker File contributed to construct their own IoT experiment platforms for every student automatically, in the form of "Infrastructure as Code". Furthermore, these separately designed IoT experiment platforms can be combined to conduct a group of group experiment simultaneously. The paper showed the Cyber Laboratory's usefulness and applicability for IoT kinds of Remote experiments.

An E-Learning System Based on the Top-Down Method and the Cellular Models

International Journal of Distance Education Technologies, Oct 1, 2004

As the broadband connectivity to the Internet becomes common, Web based e-learning and distance l... more As the broadband connectivity to the Internet becomes common, Web based e-learning and distance learning have come to play the central roles for self-learning, where learners are given much flexibility in choosing place and time to study. However, the learners still have to spend a lot of time before reaching the learning goal. This discourages the learners from continuing their studies and diminishes their motivation. To overcome this problem and to let the learners keep focusing on their primary interests, we propose a top-down e-learning system called TDeLS. The TDeLS can offer learners the learning materials based on the top-down (i.e., goal-oriented) method, according to the learners' demands and purposes. Moreover, the TDeLS can distribute them to the learners through the Internet, and manage the database for learning materials. In order to share learning materials among learners through the Web, these learning materials are wrapped in XML with a specially designed vocabulary for TDeLS. We employed the cellular models that ensure the consistency among design modules and support a top-down design methodology. In this paper, we present the TDeLS for hardware logic design courses based on the cellular models. The primary goal is to design complex logic circuits in VerilogHDL, which is an industrial-standard hardware description language. This paper also presents the basic XML vocabulary designed to describe hardware modules efficiently, and a brief introduction to the structure and functions of the proposed system that implements the TDeLS.

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Work in Progress - A New Time-sharing Remote Laboratory e-Learning System for Hardware Design and Experiment of Digital Circuits

A new remote laboratory system for learning hardware design and experiment of digital circuit has... more A new remote laboratory system for learning hardware design and experiment of digital circuit has been developed. It employs shared resources and an e-learning system based on the top-down method specializing in the logic circuit design and featuring a quick acquisition of the Hardware-Description-Language-based design skill. Wide use of the Internet motivated us to develop seamless remote and actual hardware laboratories for hardware design laboratory course, and for students to learn the digital circuit design by themselves. The proposed remote laboratory utilizes actual hardware and actual measurement tools in a time-sharing fashion. The combinatorial use of FPGA/PC connected test hardware and PC-based measurement equipments has made it possible to develop a remote multi-user and time-sharing hardware experiment system. As all students are equipped with high-performance Laptop PCs, CPU intensive development tasks can be performed by each student's client PC in a rich-client environment. The prototype the remote-laboratory and self e-learning system are underconstruction, and will be used for the third grade CS students from year 2005.

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A Time-sharing Remote Laboratory for Hardware Design and Experiment with Shared Resources and Service Management

... A Time-sharing Remote Laboratory for Hardware Design and Experiment with Shared Resources and... more

Work in progress - development of a new multi-CPU parallel and distributed processing experiment platform for remote hardware laboratory

A new multi-CPU parallel and distributed processing experiment platform using plural FPGA (Field ... more A new multi-CPU parallel and distributed processing experiment platform using plural FPGA (Field Programmable Gate Array) platforms is under development. Students can remotely perform hardware and software experiments combining a number of FPGA-based experiment platforms. The authors have already developed a remote laboratory, namely Cyber Laboratory, which realized an efficient sharing of hardware platforms among on-site and remote-site students, both in space-division and time-division fashions. Multi-CPU parallel and distributed processing experiment environment is implemented on a combined use of multiple set of FPGA experiment platforms based on the Cyber Laboratory. Each FPGA platform consists of a FPGA board with a LAN port, host PC as an experiment server, a signal generator, a logic analyzer and a synchronizing mechanism. LAN is used to connect FPGA platforms to organize a parallel system. Therefore, the proposed system can provide each student not only with a CPU hardware design/experiment platform but also with an environment where he/she can conduct parallel and distributed processing as well. The project is at a detailed design phase, and the prototype will be operational in 2010.

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Cyber laboratory for hardware logic experiments: A seamless integration of actual laboratory and remote laboratory

Cyber Laboratory for FPGA-based logic design course is underdevelopment. It combines the existing... more Cyber Laboratory for FPGA-based logic design course is underdevelopment. It combines the existing actual hardware laboratory and the remote laboratory, with newly designed CAD services and FPGA-run services realized in the form of the Web Services. A Cloud-storage is employed to transfer large CAD files and simulation data files among laboratory FPGA-Platforms and student laptop/desktop home PCs. Design Files can be shared among students, TAs and Teachers for further consultations. Students can easily migrate from actual laboratory to remote laboratory and vice versa. The Cyber laboratory takes advantage of student PCs' active participations in the remote laboratory mode to off-load time consuming tasks, such as logic simulation, from actual laboratory's FPGA-design platforms. It is also effective to avoid network latency and to improve interactive response. Cyber laboratory uses commercial Verilog-HDL logic synthesis tools, FPGA Test-beds and logic analyzers, those are tightly integrated into specific hardware platforms and difficult to decouple. So, actual laboratory organization is still plays an important role in the remote laboratory mode. CAD Web services and FPGA-run Web services are developed to combine remote student PCs with actual laboratory FPGA-Platforms. Those handle compilation, FPGA-run and logic analyzer setup/measure tasks in the form of the Web services. As the laboratory FPGA-Platforms have to serve in two ways: actual laboratory services and remote laboratory services, two separate Virtual Machines are prepared for all laboratory PCs in the form of VM PC clusters. A VM managing PC handles the allocations of VMs to laboratory PCs, according to the usage of PCs. When the actual laboratory is in use, most PCs are assigned as the actual lab VMs. During off-class hours or at night-time, most PCs run the remote service VMs. In this way, a scalable and efficient FPGA based logic design cyber laboratory can be realized.

PROTON: a parallel detailed router on an MIMD parallel machine

ABSTRACT The authors describe a novel parallel detailed router named PROTON (parallel router on a... more ABSTRACT The authors describe a novel parallel detailed router named PROTON (parallel router on a parallel machine) with various new features. These features include: a parallelized line search algorithm based on parallel breadth first search; extraction of a higher degree of parallelism by simultaneous routing of multiple nets using the result of the global router; a parallel router on a quasi-shared-memory based MIMD parallel machine; and a detailed router supporting multilayer channelless gate arrays with complex industrial design rules. PROTON is implemented on an MIMD parallel machine named Cenju, which consists of 64 microprocessors. In order to improve routing speed, PROTON incorporates two levels of parallelism, namely magnet parallelism and net level parallelism. A speedup of 43 times has been achieved using 64 processors for a medium-scale channelless gate array (1537×1790 grids, 12591 pin pairs)

Parallel neural network simulation machine: Neuman

Neural Networks, 1988

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High speed logic simulation machine

A very high speed logic simulation machine which can simulate a large scale computer, including C... more A very high speed logic simulation machine which can simulate a large scale computer, including CPU, main memory, cache memory and microprogram memory is described. By making use of this machine, it becomes possible to debug the total system before the actual machine is made available. The machine employs parallel and pipeline processing and event-driven IC level logic simulation. With

A functional level simulation engine of MAN-YO: a special purpose parallel machine for logic design automation

Computer architecture news, May 1, 1986

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MAN-YO: Mixed level parallel logic simulation engine

Systems and Computers in Japan, 1989

ABSTRACT MAN-YO is a special-purpose parallel computing machine being developed for logic circuit... more ABSTRACT MAN-YO is a special-purpose parallel computing machine being developed for logic circuit design and simulation. It uses dedicated hardware to increase the speed of gate-level simulation, and a combination of dedicated microprograms and processors for functional level simulation. Furthermore, a multiprocessor architecture, interconnected by a loop-network, is used to provide concurrent processing capability for high performance, multilevel logic simulation. Experiments were conducted to assess the performance of the functional level simulation.

MICS - A Multi-Microprocessor System

IFIP Congress, 1974

HAL III: function level hardware logic simulation

A function-level hardware simulator, HAL III, is described. HAL III can simulate a circuit model ... more A function-level hardware simulator, HAL III, is described. HAL III can simulate a circuit model written by a register transfer level language FDL without translating it into gate level. It adopts parallel, pipeline, and flexible FDL evaluation architectures, and uses level sort and event-driven algorithms at register transfer level. HAL III is more than 10000 times faster than conventional gate-level software simulators in the case of 31 processors used. HAL III can be expanded to 127 processors. HAL III can also be used as a fault simulator. Its simulation speed can be estimated more than a hundred times faster than software simulators. HAL III has been successfully used in practical VLSI designs

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