Vincent Canals

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Papers by Vincent Canals

Self-Organizing Maps hybrid Implementation Based on Stochastic Computing

2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS)

Internet of Things (IoT) applications and mobile systems are more and more dependent on Machine L... more Internet of Things (IoT) applications and mobile systems are more and more dependent on Machine Learning based solutions, thus requiring a big computational power with a low cost in terms of power consumption. This fact has revived the interest in nonconventional hardware computing methods capable to implement complex functions in a simple way in contrast with the conventional ones. This work proposes a novel hardware/software hybrid Self-Organizing Map (SOM) implementation using stochastic computing. In turn, to support this development, several stochastic block designs are presented as the squared Euclidian distance, and the Winner-Take-All (WTA) similarity check. The capabilities and performance of the methodology is tested over a well-known classification task as the Iris flower benchmark, archiving the same classification performance than the software solutions. The proposed solution presents a low-cost methodology in terms of hardware resources and power, due to its inherent capacity to implement complex functions in a simple way. This enables the methodology to implement large self-learning classifiers based on SOM with low hardware requirements.

FPGA-Based Echo-State Networks

Contributions to Statistics, 2019

The hardware implementation of Echo State Networks (ESN) can be applied to situations where a qui... more The hardware implementation of Echo State Networks (ESN) can be applied to situations where a quick response is needed in relation to how a certain signal will evolve. This is due to the possibility of connecting the ESN’s neurons in parallel, which accelerates the calculation process considerably. In this article, we present a proposal for the compact implementation of ESN in Field Programmable Gate Arrays (FPGAs). To maximize the number of neurons, the synapses are implemented using adders and multiplexers instead of multipliers. The hardware implementation has been tested for the prediction of the Santa Fe time-series dataset. The proposed approach allows for significant savings in terms of energy, hardware resources, and computing time compared to other recently published solutions.

Ultra-Fast Data-Mining Hardware Architecture Based on Stochastic Computing

PLOS ONE, 2015

Minimal hardware implementations able to cope with the processing of large amounts of data in rea... more Minimal hardware implementations able to cope with the processing of large amounts of data in reasonable times are highly desired in our information-driven society. In this work we review the application of stochastic computing to probabilistic-based pattern-recognition analysis of huge database sets. The proposed technique consists in the hardware implementation of a parallel architecture implementing a similarity search of data with respect to different pre-stored categories. We design pulse-based stochastic-logic blocks to obtain an efficient pattern recognition system. The proposed architecture speeds up the screening process of huge databases by a factor of 7 when compared to a conventional digital implementation using the same hardware area.

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A New Stochastic Computing Methodology for Efficient Neural Network Implementation

IEEE Transactions on Neural Networks and Learning Systems, 2016

This paper presents a new methodology for the hardware implementation of neural networks (NNs) ba... more This paper presents a new methodology for the hardware implementation of neural networks (NNs) based on probabilistic laws. The proposed encoding scheme circumvents the limitations of classical stochastic computing (based on unipolar or bipolar encoding) extending the representation range to any real number using the ratio of two bipolar-encoded pulsed signals. Furthermore, the novel approach presents practically a total noise-immunity capability due to its specific codification. We introduce different designs for building the fundamental blocks needed to implement NNs. The validity of the present approach is demonstrated through a regression and a pattern recognition task. The low cost of the methodology in terms of hardware, along with its capacity to implement complex mathematical functions (such as the hyperbolic tangent), allows its use for building highly reliable systems and parallel computing.

format_quoteThe ESL NN classification achieved a 2.23% error rate, closely matching theoretical boundaries from MATLAB, verifying its effectiveness in pattern recognition.format_quote

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Probabilistic-based neural network implementation

The 2012 International Joint Conference on Neural Networks (IJCNN), 2012

This paper addresses a simple way for neural network hardware implementation based on probabilist... more This paper addresses a simple way for neural network hardware implementation based on probabilistic methodologies. We propose a new codification scheme that can be considered as an extension of stochastic computing (unipolar and bipolar codification formats), extending its representation range to any real number by using the ratio between two bipolar coded pulsed signals as codification method. Based on this codification, we propose the implementation of different linear and non-linear stochastic computational elements to be employed in artificial neural networks. Also this paper presents the accuracy associated to the proposed processing. The validation of the presented approach has been done with a sample application, (a spatial pattern classification example). The low cost in terms of hardware of the proposed methodology, along with the complexity of the mathematical expressions that can be implemented allows its use for massive parallel computing.

format_quoteThe Extended Stochastic Logic (ESL) simplifies arithmetic operations, enabling representation of any real number, enhancing neural network design capabilities.format_quote

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Hardware implementation of stochastic-based Neural Networks

The 2010 International Joint Conference on Neural Networks (IJCNN), 2010

Abstract In this work we review the basic principles of stochastic logic and its application to t... more Abstract In this work we review the basic principles of stochastic logic and its application to the hardware implementation of Neural Networks. In this paper we show the mathematical basis of stochastic-based neurons along with the specific circuits that are needed to implement the processing of each neuron. We also propose a new methodology to reproduce the non-linear activation function. The proposed methodology can be used to implement any kind of Neural Network.

Random Number Generation Based on the Rossler Attractor

IEICE Proceeding Series, 2014

Chaos-based mixed signal implementation of spiking neurons

International journal of neural systems, 2009

A new design of Spiking Neural Networks is proposed and fabricated using a 0.35 microm CMOS techn... more A new design of Spiking Neural Networks is proposed and fabricated using a 0.35 microm CMOS technology. The architecture is based on the use of both digital and analog circuitry. The digital circuitry is dedicated to the inter-neuron communication while the analog part implements the internal non-linear behavior associated to spiking neurons. The main advantages of the proposed system are the small area of integration with respect to digital solutions, its implementation using a standard CMOS process only and the reliability of the inter-neuron communication.

Neural Information Processing: between synchrony and chaos

Nature Precedings, 2012

The brain is characterized by performing many different processing tasks ranging from elaborate p... more The brain is characterized by performing many different processing tasks ranging from elaborate processes as pattern recognition, memory or decision-making to more simple functionalities as linear filtering in image processing. Understanding the mechanisms by which the brain is able to produce such a different range of cortical operations remains a fundamental problem in neuroscience. Some recent empirical and theoretical results support the notion that the brain is naturally poised near critically between ordered and chaotic states. As the largest number of metastable states exists at a point near the transition, the brain can therefore access to a larger repertoire of behaviours. Consequently, is of high interest to know which type of processing can be associated to both ordered and disordered states. Here we show an explanation of which processes are related to chaotic and synchronized states based on the study of in-silico implementation of biologically plausible neural systems. The measurements obtained reveals that synchronized cells (that can be understood as ordered states of the brain) are related to non-linear computations while uncorrelated neural ensembles are excellent information transmission systems that are able to implement linear transformations (as the realization of convolution products) and to parallelize neural processes. From these results we propose a plausible meaning for Hebbian and non-Hebbian learning rules as those biophysical mechanisms by which the brain creates ordered or chaotic ensembles depending on the desired functionality. The measurements that we obtain from the hardware implementation of different neural systems endorse the fact that the brain is working with two different states, ordered and chaotic, with complementary functionalities that imply a non-linear processing (synchronized states) and information transmission and convolution (chaotic states).

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Practical Hardware Implementation of Self-configuring Neural Networks

Lecture Notes in Computer Science, 2009

Abstract. This work provides practical guidelines for an efficient hardware implementation of Neu... more Abstract. This work provides practical guidelines for an efficient hardware implementation of Neural Networks. Networks are configured using a practical self-learning architecture that iterates a basic Genetic Algorithm. The learning methodology is based on the generation of random vectors that can be extracted from chaotic signals. The proposed solution is applied to estimate the processing efficiency of Spiking Neural Networks. Keywords: Neural Networks, Spiking Neural Networks, Hardware implementation of Genetic Algorithms.

Spiking Neural Network Self-configuration for Temporal Pattern Recognition Analysis

Lecture Notes in Computer Science, 2009

In this work we provide design guidelines for the hardware implementation of Spiking Neural Netwo... more In this work we provide design guidelines for the hardware implementation of Spiking Neural Networks. The proposed methodology is applied to temporal pattern recognition analysis. For this purpose the networks are trained using a simplified Genetic Algorithm. The proposed solution is applied to estimate the processing efficiency of Spiking Neural Networks.

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A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs

Design, Automation and Test in Europe, 2005

As technology scales down, the static power is expected to become a significant fraction of the t... more As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of highperformance ICs a key issue to compute the total power dissipated in next-generations. In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. The models developed are compared to measurements and SPICE simulations for a 0.12µm technology showing excellent results.

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Using stochastic logic for efficient pattern recognition analysis

2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence), 2008

Abstract We present a pattern recognition methodology based on stochastic logic. The technique im... more Abstract We present a pattern recognition methodology based on stochastic logic. The technique implements a parallel comparison of input data from a set of sensors to various pre-stored categories. Smart pulse-based stochastic-logic blocks are constructed to provide an efficient architecture that is able to implement Bayesian techniques, thus providing a low-cost solution in terms of gate count and power dissipation. The proposed architecture is applied to a specific navigation problem demonstrating that the system provides an almost ...

Stochastic-based pattern-recognition analysis

Pattern Recognition Letters, 2010

In this work we review the basic principles of stochastic logic and propose its application to pr... more In this work we review the basic principles of stochastic logic and propose its application to probabilistic-based pattern-recognition analysis. The proposed technique is intrinsically a parallel comparison of input data to various pre-stored categories using Bayesian techniques. We design smart pulse-based stochastic-logic blocks to provide an efficient pattern recognition analysis. The proposed architecture is applied to a specific navigation problem.

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A simple CMOS chaotic integrated circuit

IEICE Electronics Express, 2008

A chaotic integrated circuit is designed and fabricated using a 0.35 μm CMOS process. The circuit... more A chaotic integrated circuit is designed and fabricated using a 0.35 μm CMOS process. The circuit iterates an N-shaped transfer function using a small analog neural network. One of the advantages of the proposed circuit is its small circuit area with only 13 MOS transistors. The circuit generates both an analog and a digital signal that can be used to create true random bit sequences.

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Self-configuring spiking neural networks

IEICE Electronics Express, 2008

We present a simple architecture for Spiking Neural Networks self-configuration. It consists in t... more We present a simple architecture for Spiking Neural Networks self-configuration. It consists in the hardware implementation of a simple Genetic Algorithm that may be used to obtain optimum network configurations. The proposed solution is applied to estimate the processing efficiency of different networks. Based on the results we develop a new performance metric to calibrate the processing capacity of SNNs.

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A Fully CMOS Low-Cost Chaotic Neural Network

The 2006 IEEE International Joint Conference on Neural Network Proceedings

Abstract A chaotic IC is proposed and fabricated using a 0.35 mum CMOS technology. The circuit it... more Abstract A chaotic IC is proposed and fabricated using a 0.35 mum CMOS technology. The circuit iterates an N-shaped transfer function that can be modified using two external voltages, and is implemented using a three neurons network. The main advantages of the proposed circuit are based on its simplicity, small area (47 times 57 mum 2), and its MOS-only implementation requiring no more than 15 MOS transistors. Measurements show the suitability of the proposed system to reproduce a chaotic signal and to be used as a ...

Stochastic Computing co-processing elements for Evolving Autonomous Data Partitioning

2021 XXXVI Conference on Design of Circuits and Integrated Systems (DCIS)

Stochastic-based Neural Network hardware acceleration for an efficient ligand-based virtual screening

ArXiv, 2020

Artificial Neural Networks (ANN) have been popularized in many science and technological areas du... more Artificial Neural Networks (ANN) have been popularized in many science and technological areas due to their capacity to solve many complex pattern matching problems. That is the case of Virtual Screening, a research area that studies how to identify those molecular compounds with the highest probability to present biological activity for a therapeutic target. Due to the vast number of small organic compounds and the thousands of targets for which such large-scale screening can potentially be carried out, there has been an increasing interest in the research community to increase both, processing speed and energy efficiency in the screening of molecular databases. In this work, we present a classification model describing each molecule with a single energy-based vector and propose a machine-learning system based on the use of ANNs. Different ANNs are studied with respect to their suitability to identify biochemical similarities. Also, a high-performance and energy-efficient hardware ...

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Estimation of Global Solar Radiation from Air Temperature Using Artificial Neural Networks Based on Reservoir Computing

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