asirbad behera

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A Wide Range CMOS VCO for PLL Applications

2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems, 2013

This paper describes a six phase differential wide range CMOS voltage controlled oscillator (VCO)... more This paper describes a six phase differential wide range CMOS voltage controlled oscillator (VCO) designed for PLL applications. The VCO bias scheme includes a rail to rail operational trans-conductance amplifier (OTA), which enhances the useful control voltage range. A novel temperature compensation scheme is also proposed to minimize the temperature dependence of oscillation frequency. External trim bits are used to reduce frequency variation across process corners. Simulation results from a 65nm LP CMOS technology with supply voltage of 1.2V are also discussed. A wide frequency range from 1GHz to 4GHz is achieved.

A Novel Dedicated Low Power 64 Bit Digital Comparator Using Cmos Logic

Journal of Embedded Systems, May 25, 2014

In this paper we have designed a novel dedicated low power 64 bit digital comparator. Magnitude c... more In this paper we have designed a novel dedicated low power 64 bit digital comparator. Magnitude comparison is one of the basic functions used for sorting in microprocessor, digital signal processing, so a high performance, effective magnitude comparator is required. The main objective of this paper is to provide new low power, area solution for Very Large Scale Integration (VLSI) designers. A Low Power 64-bit CMOS binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on power delay product. Modifications are done in existing 64-bit binary comparator design to improve the PDP of the circuit. Simulation of the proposed design is performed at 180 nm technology in Tanner EDA Tool.

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