AIAA Guidance, Navigation, and Control Conference, 2010
This paper describes a MultiPurpose Cockpit Display of Traffic Information (MPCDTI), which integr... more This paper describes a MultiPurpose Cockpit Display of Traffic Information (MPCDTI), which integrates core functional capabilities that can be combined in various ways to perform ADS-B In applications in the NextGen environment. The MPCDTI is different from other CDTIs in that it packages the capability to manage multiple applications within a single piece of equipment. Four key elements of the MPCDTI have been defined: elemental functions, simultaneous enablement, automatic algorithm selection, and output arbitration. These elements allow compatible functions to be enabled and prevent the MPCDTI from outputting infeasible or conflicting guidance to the flight crew. The objectives of this paper are to present the key features of the MPCDTI and also to suggest a functional approach for developing MPCDTI and future application performance requirements.
Extended Abstracts of the 2016 International Conference on Solid State Devices and Materials, 2016
This work presents a novel circuit design to improve the data retention of logic-compatible gain ... more This work presents a novel circuit design to improve the data retention of logic-compatible gain cell DRAM. The proposed design utilizes a parasitic capacitance built between the common cell-body and the data storage node. During data write, a voltage toggle on the cell-body couples down the data storage levels. It results in enhancing the data retention in a compact bit-area. The technique also provides much strong immunity from the write disturbance. Measured results at 1.2 V and 85 ℃ from a 110 nm 64-kbit eDRAM test chip exhibit 63.6 % improved retention time over the conventional design.
This work presents a novel circuit design to improve the data retention of logic-compatible gain ... more This work presents a novel circuit design to improve the data retention of logic-compatible gain cell DRAM. The proposed design utilizes a parasitic capacitance built between the common cell-body and the data storage node. During data write, a voltage toggle on the cell-body couples down the data storage levels. It results in enhancing the data retention in a compact bit-area. The technique also provides much strong immunity from the write disturbance. Measured results at 1.2 V and 85 °C from a 110 nm 64-kbit eDRAM test chip exhibit 63.6 % improved retention time over the conventional design.
Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhib... more Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they either suffer one of disturbances or consume large bit-area overhead. Furthermore, some cell options have a limited write-ability. This paper presents a novel 8T static RAM for reliable subthreshold operation. The cell employs a fully differential scheme and features cross-point access. An adaptive cell bias for each operating mode eliminates the read disturbance and enlarges the write-ability as well as the half-select stability in a cost-effective small bit-area. The bit-cell also can support efficient bit-interleaving. To verify the SRAM technique, a 32-kbit macro incorporating the proposed cell was implemented with an industrial 180 nm low-power CMOS process. At 0.4 V and room temperature, the proposed cell achieves 3.6× better write-abil...
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Papers by siva sundar