Digital Circuits

A fundamental difference between ASICs and FPGAs is that wires in ASICs are designed such that they match the requirements of a particular design. Wire parameters such as length, width, layout and the number of wires can be varied to implement a desired circuit. Conversely, in an FPGA, area is fixed and routing resources exist whether or not they are used, so the goal becomes implementing a circuit within the limits of available resources. The architecture for existing routing structures in FPGAs has evolved over time to suit the requirements of large, localized digital circuits. However, FPGAs now have the capacity to implement networks of such circuits, and system-level interconnection becomes a key element of the design process. Following a standard design flow and using commercial tools, we investigate how this fundamental difference in resource usage affects the mapping of various network topologies to a modern FPGA routing structure. By exploring the routability of different multiprocessor network topologies with 8, 16 and 32 nodes on a single FPGA, we show that the difference between resource utilization of a ring, star, hypercube and mesh topologies is not significant up to 32 nodes. We also show that a fully-connected network can be implemented with at least 16 nodes, but with 32 nodes it exceeds the routing resources available on the FPGA. We also derive a cost metric that helps to estimate the impact of the topology selection based on the number of nodes.

In this paper, we propose an efficient IP-Level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance into the real power consumption of pattern pairs but still has high accuracy. In order to improve the efficiency of the characterization process, the Monte Carlo approach is used during the estimation of the average power to skip the samples that will not increase the accuracy too much. The experimental result shows the table sizes are only up to 107 entries for ISCAS'85 benchmark circuits and the estimation error is only 2.99% on average using the lookup table.

Logic gates are the fundamental building blocks of all digital electronic systems and form the basis of modern computing and communication technologies. Every digital device, ranging from simple calculators to complex computers, smartphones, and embedded systems, relies on logic gates to process, store, and transmit binary information. Logic gates operate on binary inputs, typically represented by the values 0 and 1, and generate a corresponding binary output according to logical rules defined by Boolean algebra.

This paper presents a detailed and comprehensive study of logic gates, focusing on their definitions, classifications, operating principles, and mathematical representations. The study examines the basic logic gates such as AND, OR, and NOT, as well as derived and universal gates including NAND, NOR, XOR, and XNOR. Truth tables and Boolean expressions are used to clearly explain the behavior of each gate and to demonstrate how logical operations are performed within digital circuits. In addition, the paper discusses the concept of universal gates and explains their significance in simplifying digital circuit design.

Furthermore, the role of logic gates in combinational and sequential circuits is explored to illustrate how simple logical operations are combined to build complex systems such as adders, memory units, processors, and control systems. Real-world applications of logic gates in computing, communication systems, automation, and embedded technologies are also highlighted. The primary objective of this study is to provide students and beginners in digital electronics and computer science with a clear, structured, and in-depth understanding of logic gates and their critical role in modern digital system design.

For the development and evaluation of CADtools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits available for use in evaluation tools, one could consider to actually generate synthetic circuits. In this paper, we extend a graph-based benchmark generation method to include functional information. The use of a user-specified component library, together with the restriction that no combinational loops are introduced, now broadens the scope to timing-driven and logic optimizer applications. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribution of real versus synthetic benchmark circuits is hardly influenced by the suggested extensions and that the resulting circuits are more realistic than before. An indirect validation verifies that existing partitioning programs have comparable behavior for both real and synthetic circuits. The problems of accounting for timing-aware characteristics in synthetic benchmarks are addressed in detail and suggestions for extensions are included.

Rent's rule has been successfully applied to a priori estimation of wire length distributions. However, this approach is very restrictive: the circuits are assumed to be homogeneous. In this brief, recursive clustering is described as a more advanced model for the partitioning behavior of digital circuits. It is applied to predict the variance of the terminal count distribution. First, the impact of the block degree distribution is analyzed with a simple model. A more refined model incorporates the effect of stochastic self-similarity. Finally, the model is further extended to describe the effects of heterogeneity. This model is a promising candidate for more accurate a priori estimation tools.

For the development and evaluation of CAD-tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable characteristic parameters is required. Observing the lack of industrial benchmark circuits for use in evaluation tools, one could consider to actually generate such circuits. In this paper, we extend a graph-based benchmark generation method to include functional information. The use of a user-specified component library, together with the restriction that no combinational loops are introduced, now broadens the scope to timing-driven and logic optimizer applications. Experiments show that the resemblance between the characteristic Rent curve and the net degree distribution of real versus synthetic benchmark circuits is hardly influenced by the suggested extensions and that the resulting circuits are more realistic than before. However, the synthetic benchmark circuits are still very redundant, compared to existing sets of real benchmarks. It is shown that a correlation exists between the degree of redundancy and key circuit parameters.

This switching DC-DC buck converter uses a -modulator controller with a scalable sampling frequency, in order to eliminate the spurs and minimize the noise floor at its output without sacrificing the power efficiency. Fabricated in 0.13-m digital CMOS, it achieves a spurious-free output with voltage ripples below 70mV over its full loading range (2mA to 800mA). Furthermore, its power efficiency is higher than 72% over this range, with 96% peak efficiency.

We propose a new top-down eLearning tool for hardware logic design course using the cellular method, where students can keep focusing on their primary interests to achieve complex logic circuits design successfully. At a modern logic design classroom, hardware description languages such as VerilogHDL are mostly used to describe circuits for FPGAs (Field Programmable Gate Arrays). These HDL descriptions are wrapped in XML (Extensible Markup Language) with a specially arranged XML vocabulary, in order to share designed modules among students on the Web. Although XML gives us a common and convenient Web framework, it becomes difficult to verify and maintain conformance among designed modules if the system becomes very large. To overcome this problem, we employed the cellular models that ensure the consistency among design modules and support a top-down design methodology. The proposed system is expected to achieve higher efficiency for preparing logic design lecture courses. This paper presents the basic XML vocabulary design to describe hardware modules efficiently, and also presents a sample eLearning courseware on the Web employing this XML vocabulary.

A new remote laboratory system for learning hardware design and experiment of digital circuit has been developed. It employs shared resources and an e-learning system based on the top-down method specializing in the logic circuit design and featuring a quick acquisition of the Hardware-Description-Language-based design skill. Wide use of the Internet motivated us to develop seamless remote and actual hardware laboratories for hardware design laboratory course, and for students to learn the digital circuit design by themselves. The proposed remote laboratory utilizes actual hardware and actual measurement tools in a time-sharing fashion. The combinatorial use of FPGA/PC connected test hardware and PC-based measurement equipments has made it possible to develop a remote multi-user and time-sharing hardware experiment system. As all students are equipped with high-performance Laptop PCs, CPU intensive development tasks can be performed by each student's client PC in a rich-client environment. The prototype the remote-laboratory and self e-learning system are underconstruction, and will be used for the third grade CS students from year 2005.

Many devices consist of low-power processor. Quantum-dot-cellular-automata (QCA) based processor designs provide enhanced performance compared with conventional metal-oxide-semiconductor (MOS) based processors. Nanocomputing-based processors are often energy-efficient. We have developed Nanotechnology QCA-based different subcomponents of processor such as 2-to-4 decoder, 3-to-8 decoder, Delay Flip-flop (D-FF), and sequence counter. A potential energy proof has been measured in the 2-to-4 decoder design. The synthesis approach algorithm has been presented for all designs. Further, the potential energy calculation results show for 2-to-4 decoder. According to the synthesis results 2-to-4 decoder has improved 82.3% cell count, 86% area, and 85% latency over previous work. Comparing the primitive results with the prior one, results improved by 64% and 76% in terms of cell count and area in the design of the 3-to-8 decoder. Among the different components of the processor is D-FF, which has an improvement of 66.37% in cell counts and 62.5% in area over the prior design. Primitive results have improved, including latency, cell count, and area, showing the proposed processor design is comparable to lowpower devices and high speed. In terms of balance power, the proposed subcomponent of the processor will benefit low power device.

In this paper, signal-to-noise ratio (SNR) gain is used to resolve the limits of circuit chip area and power consumption in multiple antenna systems. Multiple antennas promise greatly increased capacity, but increase chip area and power consumption due to multiple RF front ends and additional resources to process multiple streams. However, trading capacity for diversity gain decreases the SNR required for similar data rates as a single antenna system. For analog circuits, the SNR gain relaxes noise requirements, making viable both inductorless and reduced power consumption circuits. For example, simulations of a inductorless low noise amplifier (LNA) show a 3 dB increase in noise figure but threefold decrease in area when compared with a conventional narrowband LNA. Similarly, a narrowband LNA has a slightly higher noise figure when operated at half its original power consumption. For digital circuits, the lowered complexity of high diversity systems decreases the size and power consumption of the digital processor.

This article focuses on the properties of a fine grained reconfigurable transistor array currently under test at the Jet Propulsion Laboratory (JPL). This Field Programmable Transistor Array (FPTA) is integrated on a Complementary Metal-Oxide Semiconductor (CMOS) chip. The FPTA has advantageous features for hardware evolutionary experiments when compared to programmable circuits with a coarse level of granularity. Although this programmable chip is configured at a transistor level, its architecture is flexible enough to implement standard analog and digital circuits' building blocks with a higher level of complexity. This model and a first set of evolutionary experiments have been recently introduced. Here, the objective is to further illustrate its flexibility and versatility for the implementation of a variety of circuits in comparison with other models of re-configurable circuits. New evolutionary experiments are also presented, serving as a basis for the authors to devise an improved model for the FPTA, to be fabricated in the near future.

As IC technology scales down, power supply instability may dramatically contribute to signal integrity loss. In this paper, we propose a new methodology to enhance circuit tolerance to powersupply voltage (V DD ) local variations, without degrading its performance. The underlying idea is to add additional tolerance to the edge trigger of the clock signal driving specific memory cells. The clock duty-cycle (CDC) is thus dynamically modulated according to V DD . Two architectures are presented, and one of them is shown to be effective. The key module is a Clock Stretching Logic (CSL) block, used to increase CDC according to V DD -V SS variations. Moreover, when clock frequency reduction is inevitable, circuit tolerance when disturbances start to occur is enhanced, allowing the clock generator to react and reduce its frequency. Experimental results based on SPICE simulations for simple combinational, pipeline and finite-state machine (FSM) circuits are used to demonstrate the usefulness of the proposed methodology.

In the paper an application of evolutionary algorithm with multi-layer chromosomes to the design and multi-objective optimization of combinational digital circuits is presented. The optimization criterions are minimizations of: number of gates, number of transistors in the circuit, and circuit propagation time. Four combinational circuits, chosen from literature, are designed, and optimized using proposed method. Results obtained using this method are compared with results obtained by other methods. The results obtained using this method are in many cases better than those obtained using other methods.

In this paper a state of the art, main problems and future trends concerning evolutionary design of combinational digital circuits are presented. Several evolutionary algorithms for design and optimization of combinational digital circuits are also shortly described. In evolutionary design methods the main problem is related to "combinatorial explosion" existing in those methods. Because evolutionary design methods are based on "generate and test" model, therefore together with growing of digital circuit input number, the number of potential combinations which must be tested are growing exponentially. This problem is a "bottle-neck" of those methods, and therefore it is discussed in details in this paper. To solve this problem it becomes important to elaborate efficient decomposition techniques of the designed circuits to some less complex sub-circuits, and then to design each of them independently. Also, it is important to create novel genetic operators (as mutation and crossover) which will always lead to acceptable solutions (solutions which satisfy the truth table ). Due to such kind of operators, any repair mechanisms need not necessarily be used, and therefore the "generate and test" model will be simplified only to generation of new solutions, and therefore evolutionary design methods will become more effective.

In this paper posibility of design and optimization of combinational digital circuits using modified evolutionary algorithm is presented. Modification of evolutionary algorithm depends on introduction of multilayer chromosomes and genetic operators operating on them. Design results for four combinational circuits obtained using this method are compared with described in literature methods: Karnaugh Maps, Quine-McCluskey and NGA and MGA genetic algorithms. Described evolutionary algorithm leads in many cases to better results.

The windup phenomenon occurs when the output of a proportional-integral (PI) controller is saturated, which results in performance degradation or even instability. In this paper, three new anti-windup algorithms are proposed for a digital PI speed controller to improve the control performance of variable-speed motor drives. These designs are implemented in a Field Programmable Gate Arrays (FPGA) device and stochastic theory is employed to enhance the computational capability of FPGA. Compared with conventional digital anti-windup techniques, the proposed methods offer several advantages: large dynamic range, easy digital design, minimizing the scale of digital circuits, re-configurability, and direct hardware implementation, while maintaining high control performance. The developed controllers are applied to the speed control of a field-oriented controlled induction motor drive using a hardware-in-the-loop test bench. The improved speed responses confirm the effectiveness of the proposed anti-windup schemes.

It was shown recently [Murali et al., Phys. Rev. Lett. 102, 104101 (2009)] that when one presents two square waves as input to a two-state system, the response of the system can produce a logical output (NOR/OR) with a probability controlled by the interplay between the system noise and the nonlinearity (that characterizes the bistable dynamics). One can switch or “morph” the output into another logic operation (NAND/AND) whose probability displays analogous behavior; the switching is accomplished via a controlled symmetry-breaking dc input. Thus, the interplay of nonlinearity and noise yields flexible and reliable logic behavior, and the natural outcome is, effectively, a logic gate. This “logical stochastic resonance” is demonstrated here via a circuit implementation using a linear resistor, a linear capacitor and four CMOS-transistors with a battery to produce a cubiclike nonlinearity. This circuit is simple, robust, and capable of operating in very high frequency regimes; furthe...

This work presents a method for enhancing the mobility of polycrystalline-Si (poly-Si) thin-film transistors (TFTs) by pattern-dependent metal-induced-lateral-crystallization (PDMILC) using nanowire channels. Experimental results indicate that the field-effect mobility of PDMILC TFT was enhanced as the channel width decreased, because the lateral length of the poly-Si grains increased. The PDMILC poly-Si TFT with ten nanowire channels (M10) had the greatest field-effect mobility, 109.34cm2∕Vs and the lowest subthreshold swing, 0.23V∕dec, at a gate length of 2μm. The field-effect mobility also increased as the gate length in the M10 PDMILC poly-Si TFT device declined, because the number of poly-Si grain-boundary defects was reduced.

An idea of wireless tactile sensing chip using RF connection has been proposed for realizing a soft artificial robot skin. However, it is difficult to make the RF tactile sensing element smaller than several millimeters because the energy transmission efficiency decreases as the coil size becomes smaller. In this paper we propose a wireless tactile sensing element based on optical connection. The sensing chip with 1 mm cubic shape operates with optical power, and sends optical codes of 6 stress components measured by an optical sensing method. We describe the chip design and the 6 stress sensing principle, and show experimental results of the stress sensing using a prototype of a 4 mm cubic chip. Then we estimated the required optical power for the sensing chip, and checked the operation of the digital circuit on the chip.

Reversible logic is gaining interest of many researchers due to its low power dissipating characteristic. In this paper we proposed a new approach for designing online testable reversible circuits. The resultant testable reversible circuit can detect any single bit error whiles it is operating. Appropriate theorems and lemmas are presented to clarify the proposed design. The experimental results show that our design approach is superior in terms of number of number of gates, garbage outputs and quantum cost.

High Peak to Average Power Ratio (PAPR) is the major drawback of Orthogonal Frequency Division Multiplexing (OFDM) system. In this paper, we propose Zadoff-Chu matrix Transform (ZCT) precoding Selected Mapping (SLM) (SLM-OFDM) system for PAPR reduction. This technique is based on precoding the constellation symbols with ZCT precoder matrix (row the multiplication of phase rotation factor and before the Inverse Fast Fourier Transform (IFFT) in t based OFDM (SLM-OFDM) Systems. At the clipping rate of 10-3, simulation results show that our proposed system can reduce the PAPR up to 6.8 dB with N=64 or 256 (System subcarriers) and V=16 (Dissimilar phase sequences) for 4QAM modulation. ZCT based SLM-OFDM system can avoid signal degradation in performance when passes through a nonlinear High-Power-Amplifier (HPA).

Heuristics leading to improved ordering computation for binary decision diagrams (BDDs) are given. An initial step, based on the topology of the network, generates a hierarchical variable ordering. This initial result is further refined by incremental manipulation governed by the stochastic evolution technique. A new property of BDDs is introduced as well, which accelerates commonly used operations. Experimental results are presented. Binary decision diagrams (BDDs) have been known for a long time as a means to represent the structure of switching functions, but only recently their use emerged in the implementation of design automation tools for digital circuits.<<ETX>>

Volume 2 deals with sequential circuits and arithmetic and logic circuits. The logic state of the output of a sequential logic circuit can depend, at any given time, on the inputs but also on the previous logic state of the outputs. Depending on whether a clock signal is used to synchronize the output state change or not, a sequential circuit is said to be synchronous or asynchronous. Arithmetic circuits can be used to perform addition, subtraction, multiplication and division operations on digital data. Volume 2 contains the following seven chapters: 1) Latch and Flip-flop; 2) Binary Counters; 3) Shift Registers; 4) Arithmetic and Logic Circuits; 5) Digital Integrated Circuit Technology; 6) Semiconductor Memory; 7) Programmable Logic Circuits. This work is an indispensable tool for all engineering students on a bachelors or masters course who wish to acquire detailed and practical knowledge of digital electronics. It is detailed enough to serve as a reference for electronic, automation and computer engineers.

The design of a dual modulus prescaler 32/33 in a 0.35 /spl mu/m CMOS technology is presented. The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called extended true single phase clock (E-TSPC), an extension of the true single phase clock (TSPC) technique, was applied. Additionally some new structures to double the data output rate are also employed. Simulations, based on the prescaler layout, were carried out and the results indicate that the circuit can reach up to 4 GHz with 4.38 mW of power consumption and power supply of 3.3 V.

In this paper, an attempt is made to reduce the power consumption of a synchronous digital system by minimizing the total power consumed by the clock signals. This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. The basic idea is to assign multiple codes to states so as to enable more effective clock gating in the sequential circuit. Experimental results demonstrate that the priority encoding technique can result in sizable power saving.

Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are the reduced node capacitances and noise margins caused by feature size and supply voltage scaling. Static soft error optimization (such as concurrent error detection or gate resizing) can be very expensive in terms of power consumption if the circuit is not always exposed to high flux of particles. This paper proposes a scheme for dynamic control of soft error tolerance in digital circuits that has negligible power and delay overhead when the circuit is in its normal mode of operation. The key objective is to design circuits that can adapt to different radiation conditions with minimal power overhead. The soft error rate of the circuit is monitored by simple on-chip circuitry, and circuit soft error tolerance is controlled by using dynamic supply voltage and threshold voltage modulation together with variable capacitance banks.

Usage of dual supply voltages in a digital circuit is an effective way of reducing power consumption due to the quadratic relation of supply voltage to power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of applying dual supply voltages at gate level granularity without using level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS'85 benchmark circuits.

The decays B[J, Bj -► e+e~, are searched for in 3.5 million hadronic Z events, which constitute the full LEP I data sample collected by the L3 detector. No signals are observed, therefore upper limits at the 90% (95%) confidence levels are set on the following branching fractions: Br( B3 e+e~) < 1.4(1.8) x 1(T5; B r(B " -> e +e_ ) < 5.4(7.0) x 10~5; Br(B" -► < 1.0(1.4) x 10~5; Br(B" -► ¡m+ fx~) < 3.8(5.1) x 10~5; Br(BS ->■ e * / ^) < 1.6(2.0) x 1(T5; Br(B" -e * / ^) < 4.1 (5.3) x 10-5 . The results for B*1 -> e+e~ and B" -> e± /x:p are the first limits set on these decay modes.

A measurement of the K( S J and A inclusive production rates and momentum spectra in two-and three-jet events is presented. On the basis of about 3. J million Z decays collected with the L3 detector at LEP, we observe that the production of these particles is well modelled by string fragmentation.

This work proposes a body-biasing technique to optimize Vmin of the 6T-SRAM based on 5nm-node multi-Vt FD-SOI devices. Accounting for the process variation, the operating voltage, Vmin, is estimated at 6-sigma yield. By properly selecting the back bias, the lowest Vmin is achieved for each of the three operation modes for 6T-SRAM application. Thus, this proposed technique offers a design flexibility for optimizing the SRAM performance and yield by adjusting the back bias without complicated process technology requirements.

Three different non-planar MOSFETs including FinFET, and rectangular/circular gate-all-around (GAA) MOSFETs are compared based on the same electrostatic parameter-scale length. Device characteristics and intrinsic gate delay are predicted using 3-D numerical simulations. FinFET is found to have an advantage in speed though it is most sensitive to process variation on the fin width as compared with the GAA counterpart. Due to limited drive current of each GAA MOSFET, multiple wire or stack wire will be needed when performance is of concern.

When making predictions about ecosystems, we often have available a number of different ecosystem models that attempt to represent their dynamics in a detailed mechanistic way. Each of these can be used as simulators of large-scale experiments and make forecasts about the fate of ecosystems under different scenarios in order to support the development of appropriate management strategies. However, structural differences, systematic discrepancies and uncertainties lead to different models giving different predictions under these scenarios. This is further complicated by the fact that the models may not be run with the same species or functional groups, spatial structure or time scale. Rather than simply trying to select a &#39;best&#39; model, or taking some weighted average, it is important to exploit the strengths of each of the available models, while learning from the differences between them. To achieve this, we construct a flexible statistical model of the relationships between...

To study the connection between macroscopic hysteretic behavior and the microstructural properties, this paper presents and validates a new material dependent three-dimensional mesoscopic magnetic hysteresis model. In the presented mesoscopic description, the different micromagnetic energy terms are reformulated on the space scale of the magnetic domains. The sample is discretized in cubic cells, each with a local stress state, local bcc crystallographic axes, etc. The magnetization is assumed to align with one of the three crystallographic axes, in positive or negative sense, defining six volume fractions within each cell. The micromagnetic Gibbs free energy is described in terms of these volume fractions. Hysteresis loops are computed by minimizing the mesoscopic Gibbs free energy using a modified gradient search for a sequence of external applied fields. To validate the mesohysteresis model, we studied the magnetic memory properties. Numerical experiments reveal that (1) minor hy...

This paper compares two types of direct torque controllers for permanent magnet synchronous motors(PMSMs). These controllers both use a single-chip FPGA(Field Programmable Gate Array) but have differing hardware configurations. One of the controllers was constructed by programming a soft-core CPU and hardware logic circuits written in VHDL(Very high speed IC Hardware Description Language), while the other was constructed of only hardware logic circuits. The characteristics of these two controllers were compared in this paper. The results show the controller constructed of only hardware logic circuits was able to shorten the control period and it was able to suppress the low torque ripple.

This paper compares two types of direct torque controllers for permanent magnet synchronous motors(PMSMs). These controllers both use a single-chip FPGA(Field Programmable Gate Array) but have differing hardware configurations. One of the controllers was constructed by programming a soft-core CPU and hardware logic circuits written in VHDL(Very high speed IC Hardware Description Language), while the other was constructed of only hardware logic circuits. The characteristics of these two controllers were compared in this paper. The results show the controller constructed of only hardware logic circuits was able to shorten the control period and it was able to suppress the low torque ripple.

L'auteur a accordé une licence non exclusive permettant à la Bibliothèque nationale du Canada de reproduire, prêter, distribuer ou vendre des copies de cette thèse sous la forme de microfiche/film, de reproduction sur papier ou sur format électronique. L'auteur conserve la propriété du droit d'auteur qui protège cette thèse. Ni la thèse ni des extraits substantiels de celle-ci ne doivent être imprimés ou aturement reproduits sans son autorisation. l would like to thank my supervisor Zeljko Zilic. His guidance and patience has been greatly appreciated during my two years at McGill. He is always willing to review papers and to send his students to numerous conferences. He is partieularly adept at suggesting relevant and interesting research topies as well as accepting students' ideas. For these and many more reasons, l do not hesitate to spend the next three years as a student of his. Monty Newborn has graciously accepted to co-supervise this work. His knowledge in computer chess is well documented and l thank him for participating in my project. M. Newborn will also be an indispensable advisor for my up-coming doctorate in hardware-accelerated automated theorem proving. An unexpected contribution to my project was made by a recent acquaintance from www.talkchess.com.Keith Evans has spent numerous hours reading my work and sharing his thoughts through many email discussions. l would also like to thank the Natural Sciences and Engineering Research Council of Canada for the financial support. This has allowed me to select a research topic regardless of financial or commercial implications. J'aimerais remercier André St-Amand pour son aide lors de la recherche bibliographique. C'est grâce à lui et les nombreuses discussions sur la programmation des échecs que j'ai choisi ce suj et de maîtrise. Ses nombreuses analyses de parties démontrant les faiblesses de mon programme ont été une source de motivation indispensable. J'aimerais également remercier Normand Leclerc d'avoir créé les images des piecès et de l'échiquier qui ont servi à l'interface graphique de MBCHESS. Merci à Patrick Cardinal pour son aide avec Jb.TEX et à André Boulé pour m'avoir suggéré d'utiliser les "named pipe" .

Increasingly, electrical and computer engineers are making their careers in designing wireless embedded systems. This paper presents a teaching methodology and the associated laboratory setup designed to meet the needs in teaching wireless embedded systems. The courses allow the students not only to apply their previous knowledge of digital system design, computer architecture, electronic circuits, wireless networking, and software engineering, but experience actual systems engineering by designing and implementing a large-scale team project within a semester. A flexible hardware platform was developed and was accompanied by teaching methodologies that allow quick completion of ambitious course projects in this area.

Quantum computing offers immense speedup in performing tasks such as data encryption and searching. The quantum algorithms can be modeled using classical computing devices, however classical computer simulations cannot deal efficiently with the parallelism present in quantum algorithms. The quantum circuit model for quantum algorithms is sufficient to describe the known quantum algorithms. Using analogies between quantum and digital circuits, we design the emulator of quantum algorithms in FPGAs that allows efficient experimentation with new quantum algorithms. This paper concentrates on new techniques for modeling quantum circuits, including the entanglement and probabilistic computing realization, as well as the critical issues in the required precision of computing.

Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing two effects: a degradation of performances mainly impacting gate delays and a noisy contamination of the quiescent levels of the logic that drives the node. Both effects are presented together, in this paper, showing than both are a cause of errors in modern and future digital circuits. The paper groups both error mechanisms and shows how the global error rate is related with the voltage deviation and the period of the clock of the digital system.