G. Scotti

Università degli Studi "La Sapienza" di Roma, Dipartimento di Ingegneria dell'Informazione, Elettronica e Telecomunicazioni, Faculty Member

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Giuseppe Scotti received the Master and Ph.D. degree in Electronic Engineering from the University of Rome "La Sapienza" in 1999 and 2003 respectively. He is currently Associate Professor at the same University. From 2003 to 2010 he was Professor of Digital Electronics. Since 2006 he teaches a course in Active Filters desing and since 2010 he teaches a basic course of electronics. From 2004 to 2006 he participated in the European project SCARD, and from 2007 to 2009 he was involved in the European Integrated Project SHAPES. His main research interests include low voltage CMOS integrated circuits, current mode circuits cryptographic Hardware and side channel attacks.

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Papers by G. Scotti

CMOS body-enhanced cascode current mirror

2009 IEEE International Symposium on Circuits and Systems, 2009

A cascode current mirror with auxiliary body-driven feedback loop is proposed. Main performance p... more A cascode current mirror with auxiliary body-driven feedback loop is proposed. Main performance parameters are analytically evaluated and compared to those of a conventional high-swing cascode and of a recently-proposed body-driven topology. Simulations are also provided confirming improvements in the achievable output resistance (important for short channel technologies), DC accuracy, and input dynamic range. Linearity, bandwidth, noise and voltage requirements

Inverting closed-loop amplifier architecture with reduced gain error and high input impedance

2006 IEEE International Symposium on Circuits and Systems, 2006

Abstract We propose an inverting closed-loop amplifier architecture providing high input impedanc... more

Design Centering and Yield Optimisation of MMIC’s with Off-Chip Digital Controllers

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Phase detector and method of generating a differential signal representative of a phase-shift

Leakage Power Analysis attacks: Well-defined procedure and first experimental results

2009 International Conference on Microelectronics - ICM, 2009

In this paper, attacks aiming at recovering the secret key of a cryptographic core from measureme... more In this paper, attacks aiming at recovering the secret key of a cryptographic core from measurements of its static (leakage) power are presented. These attacks exploit the dependence of the leakage current of CMOS Integrated Circuits (ICs) on their inputs (e.g., the secret key of a cryptographic circuit). For this reason, these novel attacks are referred to as Leakage Power Analysis (LPA) attacks in this paper. Since the leakage power increases much faster than the dynamic power at each new technology node, LPA attacks are shown to be a serious threat to information security of cryptographic circuits in sub-100 nm technologies. For the first time in the literature, a well-defined procedure to perform LPA attacks is presented. Advantages and measurement issues are also analyzed in comparison with traditional Power Analysis attacks based on dynamic power measurements. An experimental attack to a register is finally performed for the first time.

Necessary and sufficient conditions for the stability of flows of incompressible viscous fluids

Archive for Rational Mechanics and Analysis, 1994

Impact of Process Variations on LPA Attacks Effectiveness

by Milena Djukanovic and G. Scotti

In this paper, leakage power analysis (LPA) attacks aiming at recovering the secret key of a cryp... more In this paper, leakage power analysis (LPA) attacks aiming at recovering the secret key of a cryptographic core from measurements of its static (leakage) power are discussed. These attacks exploit the dependence of the leakage current of CMOS integrated circuits (ICs) on their inputs (e.g., the secret key of a cryptographic circuit). The effectiveness of this kind of attacks in

CMOS Single-to-Differential Current Amplifier

by Alessandro Trifiletti and G. Scotti

2005 IEEE International Symposium on Circuits and Systems, 2005

A CMOS current amplifier which provides single-input to differential-output conversion is propose... more A CMOS current amplifier which provides single-input to differential-output conversion is proposed. The circuit exhibits high CMRR and allows an electrical tuning of the current gain. A simple model of the circuit is presented and design guidelines are provided. Simulations with the model parameters of a 0.35-μm process show good agreement with expected results.

Analysis and modelling of broad-band ferrite-based coaxial transmission-line transformers

by Alessandro Trifiletti, G. Scotti, and Armando Fanti

The work presented in the paper focuses on accuracy of models for broad-band ferrite based coaxia... more The work presented in the paper focuses on accuracy of models for broad-band ferrite based coaxial transmission-line transformers. Soft-ferrites are largely used in VHF/UHF components allowing band enlargement on the low-edge side. Degradation of frequency performance on the high-edge side are produced both by ferrite losses, and by parasitic capacitance due to connection to the thermal and electrical ground in high power applications. Both a circuital model for low-power applications and a scalable e.m. model for high-power applications are presented and discussed.

Validation of a Statistical Non-Linear Model of GaAs HEMT MMIC's by Hypothesis Testing and Principal Components Analysis

by Alessandro Trifiletti, Francesco Centurelli, and G. Scotti

2006 IEEE International Symposium on Circuits and Systems, 2006

A distance-dependent non-linear statistical model of the active part of a very short-length HEMT-... more A distance-dependent non-linear statistical model of the active part of a very short-length HEMT-based MMIC, expressed in terms of principal components, is presented. A statistical model has been extracted for 0.1 mum GaAs HEMT devices and MMIC&amp;amp;amp;amp;#x27;s. Validation of the model is presented, based on principal component analysis and statistical hypothesis testing

A 10 Gb/s CMU in SiGe BiCMOS commercial technology with multistandard capability

by Francesco Centurelli, Alessandro Trifiletti, and G. Scotti

A 10 Gb/s CMU has been fabricated in a commercial SiGe BiCMOS technology featuring multistandard ... more A 10 Gb/s CMU has been fabricated in a commercial SiGe BiCMOS technology featuring multistandard compliance with SDH/SONET and 10 GbE specifications,dual reference clock frequency and output jitter below 80 mUIpp.The phase tracking loop uses a charge pump with low common mode current to minimize frequency ripple.Power supply is 2.5 and 3.3 V and the total power consumption is below 480 mW.

Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks

by Alessandro Trifiletti, Francesco Centurelli, G. Scotti, and Simone Bongiovanni

Journal of Cryptographic Engineering, 2015

ABSTRACT Electrical and capacitive mismatches are outstanding issues in modern submicron technolo... more ABSTRACT Electrical and capacitive mismatches are outstanding issues in modern submicron technologies, and must be considered already during the design steps. In this work, we propose a novel hardware countermeasure based on the combination of a circuit- and a system-level methodology, which helps to reduce the data dependence of the instantaneous power consumption of cryptographic circuits. Accordingly, we define a specific design methodology, which is based on a novel data encoding and on the insertion of an on-chip filter implemented through capacitances in the layout. The new countermeasure, called time-enclosed logic (TEL), is able to hide the data dependence in a very short time interval (in the order of 100 ps in modern submicron technologies), constraining the minimum amount of bandwidth required from the attack setup. As a second and parallel contribution, we present a novel design time metric for validating our design, named frequency energy deviation, which is based on the investigation of the deviation of the frequency patterns of the current traces. By simulating a basic cell template under unbalanced capacitive condition, we show that standard dual-rail precharge logics exhibit a resilient leakage already at lower frequencies, whereas in TEL circuits the data dependence is shifted toward high frequencies. As a case study, we designed a TEL-featured cryptographic circuit using a 65-nm technology node, without any assumption on the routing of the logic gates. Correlation power analysis attacks with a Gaussian model have been then mounted against the circuit. Simulation results show that the proposed countermeasure can help to mitigate the electrical mismatches occurring in submicron technologies, offering a promising perspective for the design of power analysis resistant circuits.

A Mach-Zehnder modulator model for the design of optical-fiber analog transmitters

by Alessandro Trifiletti and G. Scotti

2011 Workshop on Integrated Nonlinear Microwave and Millimetre-Wave Circuits, 2011

A measurement-based model of Mach-Zehnder electrooptic modulators is proposed that allows the des... more A measurement-based model of Mach-Zehnder electrooptic modulators is proposed that allows the design of a transmitter for optical analog links. The model, extracted for a modulator fabricated at Avanex laboratories, has been used to design a circuit in monolithic CMOS technology that provides broad-band improvement of spurious-free dynamic range.

Design of broad-band power amplifiers by means of an impedance transforming lossy equalizer

by Alessandro Trifiletti, Milena Djukanovic, Francesco Centurelli, and G. Scotti

2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014

ABSTRACT A novel topology of lossy equalizer with impedance transformation and stabilization capa... more ABSTRACT A novel topology of lossy equalizer with impedance transformation and stabilization capability is presented, which allows the design of broadband very high-linearity and high-power amplifiers. Design equations are presented and used to design a 1-2.4 GHz 60W composite amplifier exploiting push-pull configuration.

Side Channel Analysis Resistant Design Flow

by Alessandro Trifiletti and G. Scotti

2006 IEEE International Symposium on Circuits and Systems, 2006

The threat of side-channel attacks (SCA) is of crucial importance when designing systems with cry... more The threat of side-channel attacks (SCA) is of crucial importance when designing systems with cryptographic hardware or software. The FP6-funded project SCARD 1 , enhances the typical micro-chip design flow in order to provide a means for designing side-channel resistant circuits and systems. Appropriate SCA-simulation tools and SCA analysis for the designer of secure systems are part of the project goals. We consider these enhancements for traditional design flows of micro-chips as necessary in order to enable the design for the next generation of secure and dependable devices. SCARD is in its final phase, the final result, a SCARD chip designed by using the developed design flow is currently implemented.

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On Practical Second-Order Power Analysis Attacks for Block Ciphers

by Alessandro Trifiletti and G. Scotti

Lecture Notes in Computer Science, 2010

We propose a variant for a published second-order power analysis attack [1] on a software masked ... more

A 10 Gb/s CDR in SiGe BiCMOS commercial technology with multistandard capability

by Francesco Centurelli, Alessandro Trifiletti, and G. Scotti

IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003, 2003

A 10 Gb/s CMU has been fabricated in a commercial SiGe BiCMOS technology featuring multistandard ... more A 10 Gb/s CMU has been fabricated in a commercial SiGe BiCMOS technology featuring multistandard compliance with SDH/SONET and 10 GbE specifications, dual reference clock frequency and output jitter below 80 mUIpp. The phase tracking loop uses a charge pump with low common mode current to minimize frequency ripple. Power supply is 2.5 and 3.3 V and the total power consumption is below 480 mW.

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Constant and maximum bandwidth feedback amplifier with adaptive frequency compensation

by Alessandro Trifiletti and G. Scotti

2012 IEEE International Symposium on Circuits and Systems, 2012

ABSTRACT We demonstrated the feasibility of the adaptive frequency compensation approach to desig... more ABSTRACT We demonstrated the feasibility of the adaptive frequency compensation approach to design maximum- and constant-bandwidth feedback amplifiers. A basic CMOS amplifier exhibiting 66-dB dc gain and 310-MHz gain-bandwidth product was designed. For closed-loop gains ranging from 1 to 10, the closed loop bandwidth was found never lower than 401 MHz. A similar amplifier with equal gain-bandwidth product, but adopting the traditional fixed compensation approach, would exhibit a closed-loop bandwidth decreased to 33 MHz when the gain magnitude is set to 10. The enhanced frequency performance is obtained with a 48% increase in current consumption, while the other main opamp performance parameters remain almost unchanged compared to the standard solution.

Autotuning technique for CMOS current mode capacitive sensor interfaces

by Alessandro Trifiletti and G. Scotti

2012 IEEE International Symposium on Circuits and Systems, 2012

ABSTRACT The main drawback of current-mode interface circuits for on-chip capacitive sensors is t... more ABSTRACT The main drawback of current-mode interface circuits for on-chip capacitive sensors is that the measurement sensitivity is adversely affected by the sensor parasitic capacitance. This causes a strong limitation in the range of applicability of CM interfaces. In this paper we propose a technique that avoids this problem and allows the design of high-performance CMOS interfaces. The proposed solution is based on a feedback loop that, during an autotuning phase, sets the driving current level, hence ensuring virtually the same accuracy irrespectively of the parasitic capacitance. The technique was implemented and designed using a 65-nm CMOS technology. Simulation results are found in close agreement with those theoretically expected, resulting also in an increased accuracy of the capacitive variation detection.

High-tuning-range CMOS band-pass IF filter based on a low- Q cascaded biquad optimization technique

by Alessandro Trifiletti and G. Scotti

International Journal of Circuit Theory and Applications, 2014

ABSTRACT SUMMARYA design procedure for high-order continuous-time intermediate-frequency band-pas... more ABSTRACT SUMMARYA design procedure for high-order continuous-time intermediate-frequency band-pass filters based on the cascade of low-Q biquadratic cells is presented. The approach is well suited for integrated-circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivity to component variations. A trade-off between noise and maximum linear range is also met. A novel, wide-tuning-range transconductor topology is also described. Based on these results, a 10-pole band-pass filter for a code division multiple-access satellite receiver has been designed and tested. The filter provides tunable center frequency (f0) from 10 to 70 MHz and exhibits a 28-MHz bandwidth around f0 = 70 MHz with more than 39-dB attenuation at f0/2 and 2f0. Third-order harmonic rejection is higher than 60 dB for a 1-Vpp 70-MHz input, and equivalent output noise is lower than 1 mVrms. The circuit is fabricated in a 0.25-µm complementary metal oxide semiconductor process, and the core consumes 12 mA from a 2.5-V supply, offering the best current/pole ratio figure. The die area resulted to be 0.9 × 1.1 mm2. Copyright © 2014 John Wiley &amp; Sons, Ltd.

G. Scotti

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